KR100623987B1 - Thin film transistor array panels, and methods for manufacturing and repairing the same - Google Patents

Abstract

First, a common wiring including a gate wiring including a gate line, a gate electrode, and a gate pad and a common wiring including a common electrode line having a dual structure and a connection part connecting the dual common electrode line are formed in parallel with the gate line. Next, a gate insulating film, a semiconductor layer, and an ohmic contact layer are deposited, respectively, and a data line including a data line, a source electrode connected to the data line, a data pad, and a drain electrode is formed. Subsequently, after the etching of the ohmic contact layer covered by the data line, the protective layer is laminated and patterned together with the semiconductor layer to form a contact hole exposing the gate insulating layer, the drain electrode, and the data pad on the gate pad. In this case, the passivation layer and the semiconductor layer are formed along the shape of the data line in the pixel area in which the plurality of pixels are arranged. Most of the pad portion is left in the pad portion in which a plurality of pads are formed. Next, an organic insulating film having a low dielectric constant is formed on the substrate and patterned together with the protective film and the semiconductor layer to form a contact hole exposing the drain electrode and the data pad. At this time, the gate insulating film on the gate pad is also etched to form a contact hole in the gate insulating film. Next, an ITO film is stacked and patterned to form pixel electrodes, auxiliary gate pads, and auxiliary data pads respectively connected to the drain electrodes, the gate pads, and the data pads through contact holes. In this case, the auxiliary gate and the data pad are preferably formed to contact only the upper portion of the substrate and the gate insulating layer in the contact hole.

Opening ratio, organic insulating film, ITO, aluminum

Description

Thin film transistor array substrate, manufacturing method thereof and repair method thereof {THIN FILM TRANSISTOR ARRAY PANELS, AND METHODS FOR MANUFACTURING AND REPAIRING THE SAME}

1 is a layout view illustrating a structure of a thin film transistor array substrate according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1;

3 is a cross-sectional view taken along the line III-III 'of FIG. 1,

4A, 5A, 6A, and 7A are layout views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention according to a process sequence thereof;

4B, 5B, 6B and 7B are respective cross-sectional views taken along lines IVb-IVb ', Vb-Vb', VIb-VIb 'and VIIb-VIIb' in FIGS. 4A, 5A, 6A and 7A, respectively;

4C, 5C, 6C and 7C are respective cross-sectional views taken along lines IVc-IVc ', Vc-Vc', VIc-VIc 'and VIIc-VIIc' in FIGS. 4A, 5A, 6A and 7A, respectively;

8 is a layout view illustrating a structure of a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view taken along the line IX-IX 'of FIG. 8;

FIG. 10 is a cross-sectional view taken along the line X-X 'of FIG. 8;                 

11 is a layout view illustrating a repairing method of a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

The present invention relates to a thin film transistor array substrate, a method for manufacturing the same, and a method for repairing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. Device to display an image by adjusting the amount of transmitted light.

Here, since the wiring is used as a means for transmitting a signal, it is required to minimize the signal delay. In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since aluminum-based wiring is weak in physical or chemical properties, corrosion occurs when connected to other conductive materials at the contact portion, thereby degrading the characteristics of the semiconductor device. In particular, in the case of reinforcing contact characteristics of the pad portion by using indium tin oxide (ITO) in the pad portion, as in the liquid crystal display device, aluminum or aluminum alloy and ITO may have poor contact characteristics, and may interpose other metals. In order to form the wiring, not only different etching liquids are required but also several etching processes are required, which makes the manufacturing process complicated.

On the other hand, in manufacturing a thin film transistor array substrate for a liquid crystal display device in which a thin film transistor is formed, it is desirable to have a wiring structure capable of repairing disconnection or short circuit of the wiring in order to improve process yield.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array substrate and a method of manufacturing the same, which can secure an aperture ratio and secure contact characteristics of a pad portion.

Another technical problem to be solved by the present invention is to simplify a method of manufacturing a thin film transistor array substrate.

Another object of the present invention is to provide a method of repairing a thin film transistor array substrate.

In order to achieve the above object, in the present invention, a contact hole exposing a conductive layer for interconnecting a conductive layer formed by forming an organic insulating layer between the wiring and the pixel electrode and etching the protective film to form another layer when forming a semiconductor pattern is formed. Formed together to simplify the manufacturing process.

First, a gate wiring including a gate line extending in the horizontal direction and a gate electrode connected to the gate line is formed on an insulating substrate, and a gate insulating film covering the gate wiring is laminated. Next, the semiconductor layer is stacked on the gate insulating layer, and the data includes a resistive contact layer on the semiconductor layer, a data line connected to the source and drain electrodes separated from each other, and the source electrode and crossing the gate line to define a pixel. Form the wiring. Subsequently, a protective film covering the data wiring and the semiconductor layer is laminated, the protective film is patterned together with the semiconductor layer, and then an insulating film covering the protective film and the semiconductor layer is formed. Next, a protective film, a semiconductor layer, and an insulating film are patterned.

In the patterning of the passivation layer and the semiconductor layer, the passivation layer, the semiconductor layer, and the insulating layer, first and second contact holes exposing the drain electrode are formed in the passivation layer and the insulating layer, and the drain electrode is formed through the first and second contact holes on the insulating layer. The pixel electrodes connected to each other may be formed.

The common wiring may be formed on the same layer as the gate wiring to form an organic capacitance, and the common wiring may include a connection portion connecting the common electrode line having a dual structure parallel to the gate line and the dual common electrode line to each other. Do. In this case, the passivation layer and the semiconductor pattern may be formed to extend to the upper portion of the common electrode line, and the opening may be formed to expose the gate insulation layer over the common electrode line in the insulating layer, the passivation layer, and the semiconductor layer patterning step.

In the data line forming step, a repair conductive film may be formed in which both ends overlap the gate line and the common electrode line.

Here, it is preferable to form a 2nd contact hole in the inside of a 1st contact hole.                     

The gate wiring includes a gate pad connected to the gate line and receiving a scan signal from the outside, and transmitting the scan signal to the gate line. The data wiring includes a data pad connected to the data line and transferring the image signal from the outside to the data line. can do. In this case, the gate insulating film, the insulating film, the semiconductor pattern, and the protective film may have third and fourth contact holes exposing the gate pad, and the insulating film, the protective film, or the semiconductor pattern may have fifth and sixth contact holes exposing the data pad. The auxiliary gate pad and the auxiliary data pad may be further formed of the same material as the pixel electrode and connected to the gate pad and the data pad through the third and fourth contact holes and the fifth and sixth contact holes, respectively.

The third contact hole may be formed by forming a seventh contact hole corresponding to the third contact hole in the protective film and the semiconductor layer patterning step to expose the gate insulating film, and etching the protective film, insulating film and the semiconductor layer patterning step to form the gate insulating film. desirable. The third contact hole can be formed smaller than the fourth contact hole, and the third and fourth contact holes can be formed larger than the gate pad, and the auxiliary gate pad covers the third contact hole and is inside the boundary of the fourth contact hole. It is preferable to form.

The third contact hole may be formed smaller than the gate pad, the fourth contact hole may be formed larger than the gate pad, and the auxiliary gate pad may be formed only on the upper portion of the gate insulating layer inside the boundary of the fourth contact hole.

The fifth and sixth contact holes may be formed larger than the data pad, and the gate insulating film is exposed through the fifth and sixth contact holes in the insulating layer, the protective layer, and the semiconductor layer patterning step, and the auxiliary data pad is formed only on the gate insulating layer. It is preferable.

Next, a thin film transistor substrate, a manufacturing method, and a repair method thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily perform the same. .

First, the structure of the thin film transistor substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a layout view illustrating a structure of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views taken along lines II-II 'and III-III' of FIG. 1.

First, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), copper (Cu) or Gate wirings made of metal or a conductor such as a copper alloy, and holding wirings or common wirings are formed. The gate wiring is formed of a scan signal line or gate line 22 extending in the horizontal direction, a gate pad 24 and a part of the gate line 22 for transmitting the scan signal or gate signal to the gate line 22 from the outside. The gate electrode 26 is included. In addition, the common wire is formed in parallel with the gate line 22 and includes a common electrode line 23 and 25 having a double structure and a common electrode line connection part 27 connecting the two common electrode lines 23 and 25. . Here, the sustain wirings 23, 25, and 27 overlap with the pixel electrode 82 to be described later, and have a function of improving charge preservation capability of the pixel, and the repair wiring to be described later when the gate line 22 is disconnected or shorted. The conductive film 67 has a function of bypassing a signal transmitted to the gate line 22. The common wiring can be omitted when the gate wirings 22, 24, and 26 overlap the pixel electrode 82 to secure the charge storage capability of the pixel.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the substrate 10 to cover the gate wirings 22, 24, and 26 and the common wirings 23, 25, and 27, and the gate insulating film 30. The contact hole 34 is formed larger than the gate pad 24 to expose the gate pad 24 and the substrate 10 around the gate pad 24.

The semiconductor patterns 42 and 47 of the thin film transistor formed of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 30. On the semiconductor patterns 42 and 47, ohmic contact layers 55 and 56 including amorphous silicon or microcrystalline silicon or metal silicide doped at a high concentration with n-type impurities such as phosphorus (P). 57 is formed separately.

On the ohmic contacts 55 and 56, aluminum-based or copper-based or silver-based conductive materials having low resistance or molybdenum (Mo) or molybdenum-tungsten (MoW) alloys having good contact properties, chromium (Cr) and tantalum (Ta) And a data wiring made of a conductive material, such as a conductive material, and a repair conductive film 67 made of the same material as that of the data wiring is formed on the ohmic contact layer 57. The data line is formed in a vertical direction, the data line 62 defining the gate line 22 and the unit pixel, a data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and A data line portion 62, 65, 68 connected to the data line 62 and including a source electrode 65 of a thin film transistor positioned on the ohmic contact layer 55 and formed on the ohmic contact layer 55; A drain electrode 66 of the thin film transistor, which is separated from the data line parts 62, 65, and 68, and is positioned above the ohmic contact layer 56 opposite to the source electrode 65 with respect to the gate electrode 26. . Both ends of the repair conductive film 67 formed on the ohmic contact layer 57 overlap the gate line 22 and the common electrode line 25.

The data lines 62, 65, 66, and 68 may be formed of a single layer of a conductive material having a low resistance like the gate lines 22, 24, and 26, but may be formed of a double layer or a triple layer. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

In this case, the ohmic contacts 55 and 56 have the same shape as the data wires 62, 65, 66 and 68.

The passivation layer 70 is formed on the data lines 62, 65, 66, and 68 and the semiconductor pattern 42 not covered by the data line, and the passivation layer 70 forms a contact hole 76 exposing the drain electrode 66. The protective film 70 may be made of silicon nitride or silicon oxide. In the protective film 70, a contact hole 78 exposing the data pad 68 is formed. In addition, the passivation layer 70 is formed along the data lines 62, 65, 66, and 68 to expose the semiconductor pattern 42 and the gate insulating layer 30 of the unit pixel, and to the upper portions of the common lines 23 and 25. It is extended.

In this case, the passivation layer 70 is formed in a shape similar to that of the semiconductor pattern 42. Specifically, the protective film 70 except for the contact holes 76 and 68 is formed in the same shape as the semiconductor pattern 40.

An organic insulating layer 90 made of an organic material having low dielectric constant and excellent planarization is formed on the passivation layer 70 and the gate insulating layer 30. In the organic insulating layer 90, contact holes 96 and 98 are formed to expose the drain electrode 66 and the data pad 68. The organic insulating layer 90 contacts the gate pad 24 together with the passivation layer 70 and the semiconductor pattern 42. A contact hole 94 exposing the gate insulating film 30 around the hole 34 and an opening 92 exposing the gate insulating film 30 over the sustain electrodes 23 and 25. Here, the contact hole 96 of the organic insulating film 90 is smaller than the contact hole 76 of the protective film 70, but may be formed in the same size.

A pixel electrode 82 is formed on the gate insulating film 30 exposed through the organic insulating film 90 and the opening 92 of the pixel to receive an image signal from the thin film transistor and to generate an electric field together with the electrode of the upper plate. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is physically and electrically connected to the drain electrode 66 through a contact hole 76 to receive an image signal. I receive it. Meanwhile, an auxiliary gate pad 84 made of the same material as the pixel electrode 82 and connected to the gate pad 24 through the contact hole 34 is formed in the contact hole 94. An auxiliary data pad 88 is formed over the contact hole 78 via the contact hole 78, and the pads 84 and 88 complement the pad 24 and 68 with the external circuit device, It is not essential to play a role in protecting them, and their application is optional.

In the thin film transistor array substrate according to the first exemplary embodiment of the present invention, an organic insulating layer 90 having a dielectric constant is formed on the gate line 22 and the data line 62, so that the gate line 22 and the data line 62 are formed. ) And the edge portion may overlap the pixel electrode 82. Therefore, a high aperture ratio can be ensured, and the pixel electrode 82 is overlapped with the gate insulating film 30 exposed through the opening 92 to ensure sufficient storage capacity.

Next, a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 4A to 7C and FIGS. 1 and 3.

First, as shown in Figs. 4A to 4C, molybdenum (Mo) or molybdenum-tungsten (MoW) alloys, chromium (Cr), tantalum (Ta), aluminum (Al) or aluminum alloys (Al alloys), or A conductive material having a low resistance, such as copper or a copper alloy or silver series, is deposited by a method such as sputtering in a single layer or a multilayer film in turn, and dry or wet etching by a photolithography process using a mask to form a gate line on the substrate 10. 22, the gate wiring including the gate electrode 26 and the gate pad 24, and the common electrode lines 23 and 25 parallel to the gate line 22 and having a double structure, and the common electrode lines 23 and 25 having a dual structure. The common wiring including the common electrode line connecting portion 27 connecting the two to each other is formed. In a preferred embodiment of the present invention, the gate wirings 22, 24, 26 and the common wirings 23, 25, 27 are formed of an upper film made of a chromium lower film and an aluminum-based metal.

Next, as shown in FIGS. 5A to 5C, the gate insulating film 30, the semiconductor layer 40, and the ohmic contact layer 50 are respectively deposited by chemical vapor deposition, and molybdenum (Mo) or molybdenum-tungsten ( MoW) alloy, chromium (Cr), tantalum (Ta), aluminum (Al) or aluminum alloy (Al alloy), or laminated a conductive material such as copper or copper alloy or silver series, and then dry by a photo process using a mask Alternatively, the data line 62 may be patterned by wet etching to intersect the gate line 22 to define a matrix pixel, and the source electrode 65 may be connected to the data line 62 and extend to the upper portion of the gate electrode 26. And a drain electrode 66 which is separated from the data pad 68 and the source electrode 65 connected to one end of the data line 62 and faces the source electrode 65 around the gate electrode 26. The data wiring and the repair conductive film 67 The Castle. In the exemplary embodiment of the present invention, the data lines 62, 65, 66, and 68 and the repair conductive layer 67 are formed of a lower layer of chromium and an upper layer of an aluminum series.

Subsequently, the doped amorphous silicon layer 50 not covered by the data lines 62, 65, 66, and 68 is etched and separated from both sides around the gate electrode 26, while the doped amorphous silicon layers 55 on both sides are etched. , The semiconductor layer 40 between the 56 is exposed. At this time, the doped amorphous silicon layer 57 remains in the lower portion of the repair conductive film 67.                     

Next, as shown in FIGS. 6A to 6C, the protective film 70 made of an insulating material such as silicon nitride or silicon oxide is laminated, and then dry etching together with the semiconductor layer 40 by a photolithography process using a mask. By patterning, the semiconductor pattern 42 and the protective film 70 having the contact holes 74, 76, and 78 exposing the gate pad 24, the drain electrode 66, and the data pad 68 are formed. In this case, the passivation layer 70 and the semiconductor pattern 42 are patterned along the data lines 62, 65, and 66 in a pixel area in which a plurality of pixels are arranged in a matrix shape, as shown in FIGS. 6A and 6B. 42 has a shape similar to that of the data lines 62, 65, and 66, most of the gate insulating film 30 is exposed, and the semiconductor pattern 47 is shown below the repair conductive film 67 as shown in FIG. 6C. This is left without being etched, and as shown in FIG. 6A, the semiconductor pattern 42 is formed to extend to the upper portions of the sustain lines 23 and 25. In addition, in the pad portion where the gate pad 24 and the data pad 68 are formed, as shown in FIG. 6C, the semiconductor pattern 42 and the passivation layer 90 are formed to remain mostly except the contact holes 74 and 78. do. In the pixel region, the semiconductor pattern 42 has the same shape as the passivation layer 70 except for the contact hole 76, and in the pad part, the passivation layer 70 is the same as the semiconductor pattern 42 except for the lower portion of the data pad 68. Has a shape. In this case, both the semiconductor pattern 42 and the passivation layer 70 may be removed from the pad part, and both contact holes 74 and 78 may be formed wider than the pads 24 and 69 and may be made smaller. .

At this time, as in the embodiment of the present invention, when forming the data wirings 62, 65, 66, and 68 as the lower film as chromium and the upper film as aluminum-based metal, the pixel electrode 82 of ITO formed thereafter and In order to improve contact characteristics between the auxiliary data pad 88, the drain electrode 66, and the data pad 68, aluminum front etching is performed to expose the drain electrode 66 and the data pad exposed through the contact holes 76 and 78. It is preferable to remove the aluminum-based metal in 68).

Next, as shown in FIGS. 7A to 7C, an insulating film 90 of an organic material having a low dielectric constant of 4 or less and excellent planarization characteristics is formed on the substrate 10 and etched by a photolithography process using a mask. Openings 92 forming contact holes 96, 94, 98 exposing the drain electrode 66, the gate pad 24, and the data pad 68 and exposing the gate insulating film 30 over the common wirings 23, 25. ). At this time, when the gate insulating film 30 is etched until the gate insulating film 30 is exposed, the gate insulating film 30 is formed at the portion corresponding to the contact hole 74 when the contact hole 74 is formed larger than the gate pad 24 in FIG. 6C. A contact hole 34 is etched to expose the gate pad 24, and a portion of the gate insulating layer 30 is exposed around the edge of the contact hole 94. Here, in the process of patterning the protective film 70 and the semiconductor pattern 40 together, the contact hole 78 exposing the data pad 68 is also formed wider than the data pad 68, and the contact hole 78 of the protective film 70 is formed. In the case where the contact hole 98 of the organic insulating film 90 is formed larger than the contact hole 98 of the organic insulating film 90, the substrate 10 and the gate insulating film 30 are also exposed around the data pad 68. It can be seen that it can form). In the process of patterning the protective film 70 and the semiconductor pattern 40 together, the contact holes 74 and 78 of the protective film 70 are formed smaller than the pads 24 and 68, and the contact holes of the organic insulating film 90 are formed. In the case where the 94 and 98 are formed larger than the pads 24 and 68, it can be seen that the contact holes 94 and 98 can be formed around the pads 24 and 68 so that the gate insulating film 30 is exposed. have. Therefore, in order to expose the substrate 10 or the gate insulating film 30 around the pads 24 and 68, the contact holes 94 and 98 of the organic insulating film 90 are formed to be larger than the pads 24 and 68. desirable.

Here, as in the embodiment of the present invention, when the gate wirings 22, 24, and 26 are formed of the lower layer of chromium and the upper layer of aluminum-based metal, the auxiliary gate pad 84 and the gate pad of ITO formed thereafter are formed. In order to improve the contact characteristics of 28, it is preferable to perform aluminum front side etching to remove the aluminum-based metal from the gate pad 24 exposed through the contact holes 34 and 94.

Next, as shown in FIGS. 1 to 3, an ITO or IZO film is stacked and patterned using a mask to connect the pixel electrode 82 and the contact hole (which is connected to the drain electrode 66 through the contact hole 76). The auxiliary gate pad 84 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed through the 94 and 98. In this case, the pixel electrode 82 is formed to overlap the gate line 22 and the data line 62 to improve the aperture ratio.

In the thin film transistor array substrate and the method of manufacturing the same according to the first embodiment of the present invention, the thin film transistor array is formed by a photolithography process using five masks by forming contact holes 74 and 78 exposing the pad portion together with the semiconductor pattern. The substrate can be completed to simplify the manufacturing process. In addition, the auxiliary gate and data pads 84 and 88 of the ITO connected to the pads 74 and 78 may be formed to contact only the upper portion of the substrate 10 and the passivation layer 70, thereby improving contact characteristics of the pads. have.

In the first embodiment of the present invention, the opening 92 is formed on the common wirings 23 and 25 so that the pixel electrode 82 and the common wirings 23 and 25 are interposed only between the gate insulating film 30. Overlapping, sufficient holding capacity can be secured. An opening may not be formed when the holding capacity is sufficient, and will be described in detail with reference to the drawings.

8 is a layout view illustrating a structure of a thin film transistor array substrate according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are cross-sectional views taken along the lines IX-IX 'and X-X' of FIG. 8, respectively.

8 to 10, most of the structure of the thin film transistor array substrate according to the second embodiment of the present invention is the same as the first embodiment.

However, the organic insulating film 90 does not have an opening that exposes the gate insulating film 30 on the common wirings 23 and 25, and the drain electrode 66 is along the common wirings 23 and 25 than in the first embodiment. Contact holes 76 and 96 extending in the horizontal direction and exposing the drain electrode 66 are also formed extending in the horizontal direction. In addition, the contact hole 34 of the gate insulating film 30 exposing the gate pad 24 is formed to be smaller than the gate pad 24, and the organic insulating film 90, together with the protective film 70 and the semiconductor pattern 42, is formed. A contact hole 94 exposing the gate pad 24 is formed wider than the gate pad 24. In the organic insulating layer 90, a contact hole 98 exposing the data pad 68 together with the protective film 70 and the semiconductor pattern 42 is formed wider than that of the data pad 24. At this time, the auxiliary gates and the data pads 84 and 88 covering the gates and the data pads 24 and 68 are formed on the gate insulating layer 30 exposed through the contact holes 94 and 98.

In the method of manufacturing the thin film transistor array substrate according to the second embodiment of the present invention, as shown in FIGS. 6A to 6C, the gate pad 24 and the data pad (such as the passivation layer 70 and the semiconductor layer 40) are patterned. The contact holes exposing 68 are formed smaller than the gate pads 24 and the data pads 68, and when the organic insulating film 90 is patterned to form the contact holes 94 and 98, the gate pads 24 and the data pads are formed. Contact holes 94 and 98 are formed larger than 68 so that the gate insulating film 30 is exposed around the periphery of the pads 24 and 68. Subsequently, in forming the pixel electrode 82, auxiliary gates and data pads 84 and 88 are formed only on the gate insulating layer 30 around the pads 24 and 68.

Meanwhile, in the structure of the thin film transistor array substrate according to the first and second embodiments of the present invention, the disconnection of the gate line 22 may be repaired by using the repair conductive film 67. This will be described.

11 is a layout view illustrating a method of repairing disconnection of a gate line in a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

As shown in Fig. 11, in the case where the gate line 22 is disconnected in the A portion, the repair conductive film 67 and the gate line are irradiated with lasers on the B1, B2, B3, and B4 portions located on both sides of the A portion. (22) and the common electrode line 25 are short-circuited, and the signal transmitted to the gate line 22 is bypassed using the common electrode line 25 between B2 and B3. At this time, in order to prevent the signal of the gate line 22 from being transmitted to the entire common wirings 23, 25, and 27, the C portion of the common wirings 25 and 27 adjacent to B2 and B3 is disconnected using a laser.

As described above, in the thin film transistor array substrate and the method of manufacturing the same according to the embodiment of the present invention, the aperture ratio may be secured by forming the pixel electrode, the gate line, and the data line to overlap each other with an organic insulating layer having a low dielectric constant therebetween. Auxiliary pads of ITO connected to the gate and the data pad may be formed on the substrate or the passivation layer to secure contact characteristics of the pads. In addition, the semiconductor pattern and the passivation layer or the organic insulating layer may be patterned together to form contact holes together to simplify the manufacturing process.

Claims (37)

Insulation board, A gate line formed on the substrate and including a gate line extending in a horizontal direction and a gate electrode connected to the gate line; A gate insulating film formed on the substrate and covering the gate wiring; A semiconductor pattern formed on the gate insulating layer pattern; An ohmic contact layer formed on the semiconductor pattern; A data line formed over the ohmic contact layer, the data line being separated from each other and connected to a source and drain electrode and the source electrode and including a data line crossing the gate line to define the pixel; A protective film covering the data line and the semiconductor pattern and formed along the shape of the data line together with the semiconductor pattern; An insulating layer formed on the gate insulating layer and covering the protective layer pattern and the semiconductor pattern Thin film transistor array substrate comprising a. In claim 1, The protective layer and the insulating layer have first and second contact holes exposing the drain electrode, And a pixel electrode connected to the drain electrode through the first and second contact holes and formed on the insulating layer. In claim 2, And a common wiring formed of the same layer as the gate wiring and overlapping the pixel electrode to form an organic capacitance. In claim 3, The common wiring line includes a connection unit connecting a common electrode line and a dual common electrode line, which are formed in parallel to the gate line, to each other. In claim 4, The passivation layer and the semiconductor pattern extend to the upper portion of the common electrode line. In claim 5, And the insulating film, the protective film, and the semiconductor pattern have an opening that exposes the gate insulating film over the common electrode line. In claim 4, And a repair conductive layer formed on the same layer as the data line and having both ends overlapping the gate line and the common electrode line. In claim 2, And the second contact hole is formed inside the first contact hole. In claim 2, The protective film except for the first contact hole is formed in the same shape as the semiconductor pattern. In claim 2, An edge of the pixel electrode overlaps the gate line and the data line with the insulating layer interposed therebetween. In claim 2, The gate line is connected to the gate line and includes a gate pad receiving a scan signal from the outside to the gate line, The data line includes a data pad connected to the data line and transferring the data line to the data line to receive an image signal from the outside. The gate insulating film, the insulating film, the semiconductor pattern, and the protective film have third and fourth contact holes exposing the gate pad, The insulating layer and the protective layer or the semiconductor pattern have fifth and sixth contact holes exposing the data pad, And an auxiliary gate pad and an auxiliary data pad formed of the same material as the pixel electrode and connected to the gate pad and the data pad through the third and fourth contact holes and the fifth and sixth contact holes, respectively. A thin film transistor array substrate. In claim 11, And the third contact hole is smaller than the fourth contact hole. In claim 12, And the third and fourth contact holes are larger than the gate pad. In claim 13, The auxiliary gate pad covers the third contact hole and is formed inside the boundary of the fourth contact hole. The method of claim 14, And the auxiliary gate pad is in contact with the substrate and the gate insulating layer. In claim 12, And the third contact hole is smaller than the gate pad and the fourth contact hole is larger than the gate pad. The method of claim 16, And the auxiliary gate pad is formed only on an upper portion of the gate insulating layer inside the boundary of the fourth contact hole. In claim 11, And the fifth and sixth contact holes are larger than the data pad. The method of claim 18, The fifth and sixth contact holes have the same shape. The method of claim 19, The gate insulating layer is exposed through the fifth and sixth contact holes, and the auxiliary data pad is formed only on the gate insulating layer. Forming a gate line on the insulating substrate, the gate line including a gate line extending in a horizontal direction and a gate electrode connected to the gate line; Stacking a gate insulating film covering the gate wiring; Stacking a semiconductor layer on the gate insulating layer; Forming an ohmic contact layer on the semiconductor layer; Forming a data line including source and drain electrodes separated from each other, and a data line connected to the source electrode and crossing the gate line to define the pixel; Stacking a passivation layer covering the data line and the semiconductor layer; Patterning the passivation layer together with the semiconductor layer; Forming an insulating film covering the protective film and the semiconductor layer; Patterning the passivation layer, the semiconductor layer, and the insulating layer Method of manufacturing a thin film transistor array substrate comprising a. The method of claim 21, Forming first and second contact holes exposing the drain electrode in the passivation layer and the insulating layer in the passivation layer and the semiconductor layer, the passivation layer, the semiconductor layer, and the insulating layer patterning step; And forming a pixel electrode connected to the drain electrode through the first and second contact holes on the insulating layer. The method of claim 22, And forming a common wiring overlapping the pixel electrode to form an organic capacitor on the same layer as the gate wiring. The method of claim 23, The common wiring may include a connection part connecting a common electrode line having a dual structure parallel to the gate line and a dual common electrode line to each other. The method of claim 24, The passivation layer and the semiconductor pattern is formed to extend to the upper portion of the common electrode line. The method of claim 25, And forming an opening that exposes the gate insulating film on the common electrode line in the insulating film, the protective film, and the semiconductor layer patterning step. The method of claim 24, And forming a repair conductive film at both ends of the data line forming step, wherein both ends overlap the gate line and the common electrode line. The method of claim 22, And the second contact hole is formed inside the first contact hole. The method of claim 22, The gate line is connected to the gate line and includes a gate pad receiving a scan signal from the outside to the gate line, The data line includes a data pad connected to the data line and transferring the data line to the data line to receive an image signal from the outside. The gate insulating film, the insulating film, the semiconductor pattern, and the protective film have third and fourth contact holes exposing the gate pad, The insulating layer and the protective layer or the semiconductor pattern have fifth and sixth contact holes exposing the data pad, And an auxiliary gate pad and an auxiliary data pad formed of the same material as the pixel electrode and connected to the gate pad and the data pad through the third and fourth contact holes and the fifth and sixth contact holes, respectively. A method of manufacturing a thin film transistor array substrate. The method of claim 29, The third contact hole is A thin film transistor array forming a seventh contact hole corresponding to the third contact hole in the protective layer and the semiconductor layer patterning step to expose the gate insulating layer, and etching the gate insulating layer in the protective layer, the insulating layer and the semiconductor layer patterning step. Method of manufacturing a substrate. The method of claim 30, And forming the third contact hole smaller than the fourth contact hole in the passivation layer, the semiconductor layer, and the insulating layer patterning step. The method of claim 31, And forming the third and fourth contact holes larger than the gate pad. 33. The method of claim 32, The auxiliary gate pad covers the third contact hole and is formed inside the boundary of the fourth contact hole. The method of claim 30, And forming the third contact hole smaller than the gate pad and the fourth contact hole larger than the gate pad. The method of claim 34, And the auxiliary gate pad is formed only on an upper portion of the gate insulating layer inside the boundary of the fourth contact hole. The method of claim 29, And the fifth and sixth contact holes are larger than the data pad. The method of claim 36, The gate insulating film is exposed through the fifth and sixth contact holes in the insulating film, the protective film, and the semiconductor layer patterning step, and the auxiliary data pad is formed only on the gate insulating film.

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