KR100621763B1 - method for manufacturing capacitors of the semiconductor of memory device - Google Patents

Abstract

The present invention discloses a capacitor manufacturing method of a semiconductor memory device. According to this, in order to form a fine investment contact for the bar pattern of the storage electrode, a photo process by forming a pattern of the photosensitive film having a small opening corresponding to each investment contact and etching the insulating film of the investment contact portion by using this as a mask Unlike the conventional method of causing defects such as electrical connection of neighboring storage electrodes due to the limitation of the present invention, by forming a pattern of a large size photosensitive film having a common opening of each investment contact, it is possible to prevent defects such as electrical connection of neighboring storage electrodes. Can be.

Description

Method for manufacturing capacitors of the semiconductor of memory device             

1 is a layout diagram illustrating a cell of a general semiconductor memory device.

FIG. 2 is a cross-sectional view illustrating a capacitor structure of a semiconductor memory device according to the prior art, and taken along line A-A of FIG. 1.

3 is a cross-sectional view showing a capacitor structure of a semiconductor memory device according to the prior art, taken along the line B-B of FIG.

4 to 9 are process diagrams illustrating a method of manufacturing a capacitor of a semiconductor memory device according to the present invention, in which a and b are cross-sectional views taken along line AA and BB of FIG. 1.

The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor of a semiconductor memory device to overcome the difficulty of the photo process for forming a fine investment contact to prevent the bridge electrode of the storage electrode. It is.

The present invention relates to a method for forming a load resistance of a semiconductor device to prevent the addition of a photo process to simplify the manufacturing process.

In general, an increase in the cell capacitance of a DRAM improves the readability of the memory cell and decreases the soft error rate, thus greatly contributing to improving the memory characteristics of the cell. As the density of memory cells increases, the area occupied by unit cells in one chip decreases, which leads to a reduction in the area of the cell capacitor. Therefore, many studies have been continuously introduced to increase cell capacitance since the increase of unit cell density and the capacitance of the cell capacitor are essential. Most of them are related to the structure of the storage electrode constituting the cell capacitor. The pin structure electrodes of Toshiba Corp., the box structure electrodes of Toshiba Corp., and the cylindrical structure electrodes of Mitsubishi Corp. are the mainstream. Attempts to increase the capacitance of the cell capacitor by improving the structure of the storage electrode have been criticized for its manufacturability due to problems such as limitations of design rules and increase in error rate due to complex processes.

Thus, there has been a growing need for a new cell capacitor manufacturing method that overcomes these problems. Capacitor over bitline (COB) cells, which have cell capacitors formed on the bit lines, have been introduced as structures suitable for 64M DRAM cells or 256M DRAM cells, which use buried contacts to prevent bad contact of the bit lines. come. However, in the DRAM of more than 256M, forming a buried contact is almost the limit of the photo process, so to solve this problem, self-aligned contact (SAC) to secure enough unmatched margins began to be introduced. It was. Representative of such a technique is disclosed in US Patent No. 5977583, US Patent No. 5879986 and the like. The problem with this technique is that it can only be determined by the technical limitations of the photographic process. 1 to 3, the word lines W / L pass through the channel region between the source / drain S / D of each transistor of the memory cell, as shown in FIG. 1. The wires extend in the longitudinal direction, and the bit lines B / L vertically intersect the word lines W / L with each transistor interposed therebetween, and extend in the lateral direction. Is electrically connected to the corresponding bit line (B / L) via the D / C contact hole, and the cell pads 60 defined by a dashed line are overlapped and electrically connected to both drains D of each transistor. The storage electrodes 100 defined by the dashed lines are electrically connected to each other while overlapping the corresponding cell pads 60.

As shown in FIG. 2, the isolation layer 11 is formed in the field region of the silicon substrate 10 by shallow trench isolation (STI), and is formed on the channel region between the source and drain (S / D) of the transistor. A gate oxide film 13 and a gate electrode 15 for word line (W / L) thereon are formed, an insulating film 17 is formed on the gate electrode 15, and both side walls of the gate electrode 15 are formed. Spacers 19 of the insulating film are formed. The oxide film 50 on the cell region and the peripheral region (not shown) is planarized, formed between the spacers 19 facing each other so that the cell pads 60 are connected to the corresponding drain D, and planarized on the oxide film 50. To achieve. The nitride film 70 is stacked on the oxide film 50 and the cell pads 60. Of course, the pattern of the bit line 81 passes through the word line on the nitride film 70 and is contacted to the cell pad (not shown) on the source via the bit line contact hole (not shown). The oxide film 90 is planarized on the nitride film 70 including the bit line, and the nitride film 91 is stacked thereon. The bar pattern 110 of the cylindrical storage electrode 100 is electrically connected to the cell pad 70 through an investment contact hole. The gate electrode 15 may be formed of a lower polysilicon layer 15a and an upper silicide layer 15b in order to reduce the resistance of the word line. The bit line 81 may be formed of a Ti / TiN layer, which is a lower barrier metal layer 81a, and a tungsten layer 83, an upper layer.

As shown in FIG. 3, an isolation layer 11 is formed in the field region of the silicon substrate 10 with the drain D of each transistor interposed therebetween, and an oxide film formed on the drain D and the isolation layer 11. 50 is planarized, the cell pad 60 is connected to each drain D, and planarized on the oxide film 50, and the nitride film 70 is laminated on the oxide film 50 and the cell pads 60. do. A pattern of the bit line 81 is formed on the nitride layer 70 and overlaps the isolation layer 11. A nitride film 85 having the same pattern is formed on the bit line 81, and a spacer 87 of the nitride film is formed on both side walls of the bit line 81. An oxide film 90 is planarized on the cell region and a peripheral region (not shown) outside thereof, and a nitride film 91 is stacked thereon. The bar pattern 110 of the cylindrical storage electrode 100 is electrically connected to the cell pad 60 through a buried contact hole. The bit line 81 may include a lower Ti / TiN layer 81a and an upper tungsten layer 81b.

However, in the conventional highly integrated DRAM configured as described above, since the upper surface of the oxide film 90 is positioned higher than the upper surface of the cell pad 50, a buried contact must be formed in the oxide film 90 by a photographic process. Therefore, when the pattern of the photoresist film for the buried contact is formed on the oxide film 90 by the photolithography process, only the region where each buried contact is to be formed should be opened and all remaining areas should be covered.

However, if the distance X between investment contacts is defined as the minimum size, in spite of having to open only the area where each investment contact is to be formed and cover all the remaining areas, it actually corresponds to the distance X between investment contacts. Since it is highly unlikely to cover a portion A on the bit line 80 properly, the oxide film 90 on the bit line 81 during the subsequent etching process of etching the oxide film 90 in the region for the buried contact. It is also easy to etch some.

In this state, when the polysilicon layer is stacked and etched back on the entire surface of the oxide layer 90 to form the bar pattern 110 of the storage electrode 100, the bar pattern 110 is formed in the buried contact and the bit line is formed. Part of the polysilicon layer remains on the oxide film 90 on the 81, so that the bridge phenomenon in which the adjacent bar patterns 110 are connected to each other is likely to occur frequently. As a result, two fail failures occur in which two bit lines are bad. In order to overcome this, the precision of photographic process must be further increased, which requires huge expensive photographic process equipment, resulting in an increase in manufacturing cost.

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device to prevent the bridge phenomenon of the storage electrode while reducing the difficulty of the photo process for forming a fine buried contact.

Another object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device which prevents an increase in manufacturing cost and prevents bridge phenomenon of a storage electrode.

Capacitor manufacturing method of a semiconductor memory device according to the present invention for achieving the above object

Forming an isolation layer in the field region to isolate the active region of the semiconductor substrate;

Forming a word line in the active region;

Forming cell pads in contact with the active region;

Forming a bit line passing across the word line in a field region between the cell pads;

Exposing cell pads between the word lines using a common etch mask; And

And forming a bar pattern of the storage electrode to be buried in the cell pads, respectively.

Preferably, forming the bar pattern

Thickly depositing a polysilicon layer to be buried in the cell pads; And

And etching the polysilicon layer to separate the bar pattern. Moreover, it is preferable to laminate | stack the said polycrystalline silicon layer to thickness of 1000 micrometers or more.

Hereinafter, a method of manufacturing a capacitor of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are assigned to the same components and parts of the same operation as the conventional parts.

4 to 9 are process diagrams illustrating a method for manufacturing a capacitor of a semiconductor memory device according to the present invention, in which a and b are cross-sectional views taken along line AA and BB of FIG. 1, and FIG. 10 is a cross-sectional view of the semiconductor memory device of the present invention. A plan view showing a pattern of a photosensitive film for forming an investment contact applied to a capacitor manufacturing method.

Referring to FIGS. 4A and 4, first, an isolation layer 11 is formed in a field region by shallow trench isolation (STI) to isolate an active region of a substrate, for example, a silicon substrate 10. Thereafter, the gate oxide film 13 is grown on the active region of the silicon substrate 10 by a thermal oxidation process, and the polycrystalline silicon for the gate electrode 15 is formed on the entire surface of the silicon substrate 10 including the gate oxide film 13. A layer 15a and a silicide layer 15b, for example a tungsten silicide layer, are formed thereon and an insulating film of a first material, for example, a nitride film 17, is laminated on the silicide layer 15b. Then, the nitride film 17, the silicide layer 15b, and the polysilicon layer 15a are formed in a pattern of a word line in FIG. 1 by using a photolithography process. After the word line is formed, a lightly doped drain (LDD) region is formed by ion implanting impurities of a desired conductivity type into the active region of each transistor at low concentration using the word line as a mask to form a spacer on the front surface of the silicon substrate 10. A thick insulating film for (19) is stacked and then etched back until the active region is exposed to form spacers 19 on both side walls of the word line. By using the word line and the spacer 19 as a mask, ion-implanted impurities of a desired conductivity type are implanted in the active region at high concentration to form a source / drain (S / D) together. After the source / drain is formed, an insulating film of a second material, for example, an oxide film 50 is laminated on the entire surface of the resulting structure higher than the upper surface of the nitride film 19 and then planarized by a mechanical polishing process. Afterwards, the oxide film 50 on the source S and the drain D in which the bit line contact hole is to be formed is selectively etched using a photolithography process to expose the source / drain S / D below it. Subsequently, the polysilicon layer for the cell pad 60 is thickly stacked on the oxide film 50 including the source / drain (S / D) and polished by a mechanical chemical process to each cell pad 60 by the source / drain (S / D). D) and all of the polysilicon layers on the oxide film 50 on the outside thereof are left on the spacer 19 around it. Therefore, each cell pad 60 is separated and planarized on the oxide film 50.

Referring to FIGS. 5A and 5B, after the cell pad 60 is formed, the nitride film 70 is laminated on the cell pad 60 and the oxide film 50 together, and the bit line contact is formed by using a photolithography process. The nitride layer 70 and the oxide layer 50 under the portion are etched until the cell pad 60 is exposed to form a bit line contact hole (not shown). Then, a barrier metal layer 81a including a lower Ti film and an upper TiN film is laminated on the entire surface of the nitride film 70 including the cell pad in the bit line contact hole, and a tungsten layer 81b is stacked thereon to form a bit line. After the investment contact is formed, a nitride film 85 is laminated on the tungsten layer 81b. Subsequently, a photoresist pattern (not shown) corresponding to the pattern of the bit line passing across the word line is formed on the nitride film 85 using a photolithography process, and the nitride film 85 and the tungsten layer 81b are used as a mask. Dry etching the barrier metal layer 81a to form a pattern of the bit line, and then removing the pattern of the photoresist layer.

6A and 6B, after the bit line pattern is formed, a nitride film is stacked on the nitride film 70 including the bit line pattern and etched back to form a spacer of the nitride film on both sidewalls of the pattern of the bit line. 87). Subsequently, the oxide film 90 is thickly stacked for electrical insulation between the bit line and the storage electrode, and then the oxide film 90 is polished using a mechanical chemical polishing process to planarize the nitride film 85.

7A and 7B, once the oxide film 90 is planarized, a pattern of the photoresist film 91 having a common opening for exposing the cell pads 60 to be buried is formed on the oxide film 90 and then formed. Using the mask, the oxide film 90 and the nitride film 70 between the word lines are dry-etched until the cell pad 60 below them is exposed. Here, since the nitride film 85 on the bit line acts as an etch stopper and the word line and the peripheral area are masked by the pattern of the photosensitive film 91, defects such as electrical connection of the bar pattern of the storage electrode can be prevented. In addition, since the dry etching is terminated on the surface of the cell pad 60, a safe etching is possible.

Referring to FIGS. 8A and 8B, after the nitride film 70 is etched, the polycrystalline silicon for storage electrode is formed on the front surface of the resultant structure to a thickness thick enough to fill the buried contact hole after removing the pattern of the photosensitive film 91. The bar pattern 110 is planarized on the nitride layer 85 by stacking and etching back the layer to leave the bar pattern 110 only in the buried contact hole and removing the polysilicon layer on the remaining area. Accordingly, the present invention can easily prevent the bridge phenomenon of neighboring investment contacts without being affected by the margin limits of the self-aligned contact (SAC) and the fine investment contact.

9A and 9B, after the bar pattern 110 is formed, the nitride film 120 is stacked to a thickness of 200 μm or more as an etch stopper when the storage node is formed on the entire surface of the resulting structure, and the oxide film 130 is disposed thereon. The layer is thickly stacked and the oxide layer 130 in the region for forming the storage node is etched using the photolithography process until the cell pad 60 is exposed. Then, after stacking the polysilicon layer for the storage electrode on the front of the resulting structure and etched back to separate each storage electrode (100). Subsequently, the dielectric film 140 is stacked on the entire surface including the story electrode 100, and a polysilicon layer for the plate electrode 150 is stacked thereon, and formed into a pattern of the plate electrode 150 using a photolithography process. Complete the capacitor of the invention.

As described above, in the method of manufacturing a capacitor of a semiconductor memory device according to the present invention, a pattern of a photoresist film having a small opening corresponding to each investment contact is formed in order to form a fine investment contact for a bar pattern of a storage electrode. By using this as a mask, the insulating film of the buried contact portion is etched so that a pattern of a large size photoresist film having a common opening of each buried contact, unlike the conventional one, which causes defects such as electrical connection of neighboring storage electrodes due to the limitation of the photo process. By forming it, it is possible to prevent defects such as electrical connection of neighboring storage electrodes.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (3)

Forming an isolation layer in the field region to isolate the active region of the semiconductor substrate; Forming a word line in the active region; Forming cell pads in contact with the active region; Forming a bit line passing across the word line in a field region between the cell pads; Exposing cell pads between the word lines using a common etch mask; And And forming a bar pattern of a storage electrode buried in the cell pads, respectively. The method of claim 1, wherein the forming of the bar pattern Thickly depositing a polysilicon layer to be buried in the cell pads; And And separating the bar pattern by etching back the polysilicon layer. 3. The method of claim 2, wherein the polysilicon layer is laminated to a thickness of 1000 Å or more.

Images