KR100607817B1 - Method of manufacturing a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein when a junction is formed in a predetermined region of a semiconductor substrate, a selective epitaxial growth (SEG) process or a surface area enhanced (SAES) process is performed before a silicide layer is formed on the junction or a metal wiring process is performed. By increasing the area of the junction by growing the junction by the silicon process, the semiconductor device can improve the reliability of the process and the electrical characteristics of the device by securing more alignment margin between the junction and the contact plug and preventing contact resistance from increasing. A method of producing is disclosed.

Joint, Joint Area, SEG, SAES, Boulderless Contact

Description

Method of manufacturing a semiconductor device             

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

2A through 2E are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 201: semiconductor substrate 102, 202: device isolation film

103 and 203 gate oxide films 104 and 204 gate

105, 205: insulating film spacer 106, 206: source / drain

107 and 207 silicon growth layer 108 and 208 silicide layer

109, 209: nitride film 110, 210: interlayer insulating film

111, 211: contact plug 112, 212: contact surface

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for increasing the contact area between the junction and the contact plug.

Numerous studies have been conducted to improve the performance and the degree of integration of semiconductor devices. As a result of this research, a technology for reducing the line width of the gate or forming metal wiring using copper is being developed. In the case of a contact hole connecting a source / drain / gate and the metal wiring, a borderless contact technology is used. This improves the performance and integration of the device.

However, as devices become more and more highly integrated, there is a limit to the application of Boulderless contact technology. For example, when the design rule is 0.13 um, the critical dimension (CD) of the contact hole is only about 0.16 um. In this case, the contact area between the contact plug and the joint becomes difficult to predict.

As a result, contact resistances in the same cell may be locally different according to regions, and fatal defects may occur in the operation of the device.

Therefore, when the junction is formed in a predetermined region of the semiconductor substrate in order to solve the above problems, the present invention prior to forming a silicide layer on the junction or proceeding the metal wiring process, the surface area enhanced (SEG) process or surface area enhanced (SAES) By increasing the area of the junction by growing the junction by the silicon process, the semiconductor device can improve the reliability of the process and the electrical characteristics of the device by securing more alignment margin between the junction and the contact plug and preventing contact resistance from increasing. Its purpose is to provide a process for the preparation.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, a gate is formed on a semiconductor substrate which is separated into an isolation region and an active region by an isolation layer, and a source and a drain are formed in the semiconductor substrate of both active regions of the gate. Forming a silicon growth layer by growing silicon on the gate, the source and the drain, silicating the silicon upper layer to form a salicide layer, and forming an interlayer insulating film on the entire surface And forming a contact hole exposing the salicide layer in the interlayer insulating film, and forming a contact plug in the contact hole.
In the above, the silicon growth layer may form a SEG process using any one selected from SiH ₄ , Si ₂ H ₆ and Si ₂ Cl ₂ H ₂ as the source gas and using HCl or Cl ₂ as the reaction gas. In this case, the SEG process may be performed while supplying a source gas of 20 to 200 sccm and a reaction gas of 50 to 100 sccm at a temperature of 700 to 800 ° C. and a pressure of 20 to 100 Torr.

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Meanwhile, the silicon growth layer may be formed by a SAES process using any one selected from SiH ₄ , Si ₂ H _6, and Si ₂ Cl ₂ H ₂ as a source gas. In this case, the SAES process may be performed while supplying a source gas of 100 to 800 sccm at a temperature of 450 to 550 ° C. and a pressure of 20 to 100 Torr.

After forming the silicide layer and before forming the interlayer insulating film, the method may further include sequentially forming an oxide film over the entire portion including the junction and subsequently forming any one of a nitride film, a nitride oxide film, and a carbide film.

In addition, after forming the contact hole and before forming the contact plug, the device isolation layer exposed through the contact hole may be dry-etched using CF-based gas, wet-etched using HF-based fluorine-containing etchant, or NH ₄ OH. Alternatively, the method may further include exposing a side surface of the silicide layer by removing a predetermined depth by a wet etching process using an oxide etchant such as HCl.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, various elements for forming a semiconductor device are formed on a semiconductor substrate on which an isolation layer 102 is formed in an isolation region. For example, when forming a transistor, the gate oxide film 103, the gate 104, the insulating film spacer 105, and the source / drain 106 are formed in a conventional process. In the case of forming the transistor in this way, the gate 104 and the source / drain 106 become a junction to be in contact with the contact plug to be formed in a subsequent process. Hereinafter, the gate 104 and the source / drain 106 will be referred to as a junction.

Referring to FIG. 1B, the silicon growth layer 107 is formed on the gate 104 and the source / drain 106 by growing silicon by about 100 to 1000 microseconds by a selective epitaxial growth (SEG) process. In the above, the SEG process is performed using any one selected from SiH ₄ , Si ₂ H ₆ and Si ₂ Cl ₂ H ₂ as the source gas, using HCl or Cl ₂ as the reaction gas. Specifically, the SEG process is performed while supplying a source gas of 20 to 200 sccm and a reactant gas of 50 to 100 sccm at a temperature of 700 to 800 ° C. and a pressure of 20 to 100 Torr to form the silicon growth layer 107. As described above, by forming the silicon growth layer 107 on the junctions 104 and 106, the contact area with the contact plug to be formed in a subsequent process is increased.

Referring to FIG. 1C, the silicon growth layer 107 is silicided through a salicide (Self-Aligned Silicide) process to form a silicide layer 108 on the junctions 104 and 106. In this case, the silicide layer 108 may be formed of a tungsten silicide layer using tungsten or a cobalt silicide layer using cobalt.
The salicide process is described in more detail as follows.
After forming a metal layer (not shown) on the entire structure including the silicon growth layer 107, heat treatment is performed. Then, the silicon component included in the silicon growth layer 107 and the metal component included in the metal layer cause a silicide reaction to form the silicide layer 108. At this time, since the device isolation film 102 or the insulating film spacer 105 does not react with the metal layer, no silicide layer is formed on the device isolation film 102 or the insulating film spacer 105. Subsequently, when the unreacted metal layer is removed, only the silicide layer 108 remains on the junctions 104 and 106.
The silicide layer 108 may be formed on the junctions 104 and 106 by the above method.

Referring to FIG. 1D, in order to form a borderless contact (BLC), the nitride layer 109 is formed over the entire surface, and then the interlayer insulating layer 110 is sequentially formed. Here, the nitride film 109 may be formed to a thickness of 100 to 500 GPa, and instead of the nitride film, a nitride oxide film or a carbide film (SiC) having a different etching selectivity with respect to the oxide film may be formed. On the other hand, an oxide film (not shown) is first formed to a thickness of 10 to 200 kPa before the nitride film 109 is formed in order to prevent the interfacial property between the nitride film 109 and the silicide layer 108 from deteriorating. Subsequently, the interlayer insulating layer 110 may be formed of BPSG or PE-TEOS.

Referring to FIG. 1E, a contact hole exposing the silicide layer 108 is formed by selectively etching the interlayer insulating layer 110 and the nitride layer 109 by a photolithography process, and then filling the contact hole with a conductive material to form a contact plug. (111) is formed. In this case, the contact hole is formed by first removing the interlayer insulating layer 110 on the junction portion 106 and then removing the nitride layer 109 by wet etching using a nitride etchant such as phosphoric acid.

Subsequently, when not only the silicide layer 108 but also a portion of the device isolation layer 102 is exposed through the contact hole, the exposed device isolation layer 102 is partially removed to a predetermined depth to thereby remove the side surface 112 of the silicide layer 108. ), Thereby increasing the contact area. In this case, the device isolation layer 102 may be a dry etching method using a CF-based gas, a wet etching method using an HF-based fluorine-containing etchant, or a wet etching process using an oxide etchant such as NH ₄ OH or HCl. Removal, by a thickness of 10 to 500 mm 3.

As described above, by using the silicon growth layer formed by the SEG process (107 in Fig. 1b) to form a contact plug 111 on the junction 106 in the state of increasing the area to secure a margin for alignment error and At the same time, the contact area can be prevented from being reduced, thereby increasing the contact resistance.

Although the area of the junction is increased by the SEG process, the area of the junction may be increased by the surface area enhanced silicon (SAES) process. Hereinafter, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described.

2A through 2E are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 2A, various elements for forming a semiconductor device are formed on a semiconductor substrate on which an isolation layer 202 is formed in an isolation region. For example, when forming a transistor, the gate oxide film 203, the gate 204, the insulating film spacer 205, and the source / drain 206 are formed in a normal process. In the case of forming the transistor in this way, the gate 204 and the source / drain 206 become a junction to be in contact with the contact plug to be formed in a subsequent process. Hereinafter, the gate 204 and the source / drain 206 will be referred to as a junction.

Referring to FIG. 2B, the silicon growth layer 207 is formed on the junctions 204 and 206 by growing about 30 to 1000 microseconds of silicon through a surface area enhanced silicon (SAES) process. In the above, the SAES process is carried out using any one selected from SiH ₄ , Si ₂ H ₆ and Si ₂ Cl ₂ H ₂ as the source gas. Specifically, the SAES process is performed while supplying a source gas of 100 to 800 sccm at a temperature of 450 to 550 ° C. and a pressure of 20 to 100 Torr to form the silicon growth layer 207. As described above, by forming the silicon growth layer 207 on the junctions 204 and 206, the contact area with the contact plug to be formed in a subsequent process is increased.

Referring to FIG. 2C, a silicide layer 208 is formed on the junctions 204 and 206 by suicide of the silicon growth layer 207 using a salicide (Self-Aligned Silicide) process. In this case, the silicide layer 208 may be formed of a tungsten silicide layer using tungsten or a cobalt silicide layer using cobalt.
The salicide process is described in more detail as follows.
After forming a metal layer (not shown) on the entire structure including the silicon growth layer 207, heat treatment is performed. Then, the silicon component included in the silicon growth layer 207 and the metal component included in the metal layer cause a silicide reaction to form the silicide layer 208. At this time, since the device isolation film 202 or the insulation film spacer 205 does not react with the metal layer, no silicide layer is formed on the device isolation film 202 or the insulation film spacer 205. Subsequently, when the unreacted metal layer is removed, only the silicide layer 208 remains on the junctions 204 and 206.
The silicide layer 208 may be formed on the junctions 204 and 206 by the above method.

Referring to FIG. 2D, in order to form a Boulderless Contact (BLC) in the same manner as described in FIG. 1D, an interlayer insulating film 210 is sequentially formed after the nitride film 209 is formed over the entire surface. . Similarly, an oxide film (not shown) is first formed to a thickness of 10 to 200 kPa before the nitride film 209 is formed in order to prevent the interfacial property between the nitride film 209 and the silicide layer 208 from deteriorating.

Referring to FIG. 2E, after the contact hole is formed in the same manner as described in FIG. 1E, the contact hole is filled with a conductive material to form the contact plug 211. Similarly, when not only the silicide layer 208 but also the part of the device isolation layer 202 is exposed through the contact hole, the exposed device isolation layer 202 is partially removed to a predetermined depth, so that the side surface 212 of the silicide layer 208 is removed. ), Thereby increasing the contact area. Meanwhile, the silicide layer 208 and the contact plug 211 are formed by forming the silicide layer 208 after the silicon growth layer 207 of FIG. 2B is unevenly formed by the SAES process. The contact area of the liver can also be increased.

As described above, the silicon growth layer (207 of FIG. 2B) is formed by the SAES process to form the contact plug 211 in the state of increasing the surface area, thereby securing a margin for alignment error and preventing the contact area from being reduced. This can prevent an increase in contact resistance.

As described above, the present invention increases the area of the junction by growing silicon in a selective epitaxial growth (SEG) process or a surface area enhanced silicon (SAES) process, thereby further securing alignment margins between the junction and the contact plug and making contact resistance. This increase can be prevented to improve process reliability and device electrical properties.

Claims (7)

Forming a gate on a semiconductor substrate separated by an isolation layer and an active region by an isolation layer, and forming a source and a drain in the semiconductor substrate of the active region on both sides of the gate; Growing silicon on the gate and the source and drain to form a silicon growth layer; Silicidating the silicon top layer to form a salicide layer; Forming an oxide film on the entire surface; Forming a film selected from one of a nitride film, a nitride oxide film, and a carbide film on the oxide film; Forming an interlayer insulating film on the entire surface; Forming a contact hole in the interlayer insulating layer exposing the salicide layer and a portion of the device isolation layer adjacent to the source and drain; Removing the device isolation layer exposed through the contact hole to a predetermined depth to expose a side surface of the silicide layer; And forming a contact plug in the contact hole. The method of claim 1, The silicon growth layer is a semiconductor device characterized in that to form a SEG process using any one selected from SiH ₄ , Si ₂ H ₆ and Si ₂ Cl ₂ H ₂ as a source gas and using HCl or Cl ₂ as a reaction gas Method of preparation. The method of claim 2, The SEG process is performed while supplying the source gas of 20 to 200 sccm and the reactant gas of 50 to 100 sccm at a temperature of 700 to 800 ° C. and a pressure of 20 to 100 Torr. The method of claim 1, The silicon growth layer is a method of manufacturing a semiconductor device, characterized in that formed by the SAES process using any one selected from SiH ₄ , Si ₂ H ₆ and Si ₂ Cl ₂ H ₂ as the source gas. The method of claim 4, wherein The SAES process is carried out while supplying a source gas of 100 to 800 sccm at a temperature of 450 to 550 ℃ and a pressure of 20 to 100 Torr. delete The method of claim 1, The device isolation film removal process may include a dry etching process using a CF-based gas, a wet etching process using an HF-based fluorine-containing etchant, or a wet etching process using an oxide etchant such as NH ₄ OH or HCl. The manufacturing method of the semiconductor element characterized by the above-mentioned.

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