KR100599646B1 - Plasma Display Panels and Anomaly Detection Method - Google Patents

Abstract

The present invention relates to a plasma display panel and an abnormality detection method of the plasma display panel for detecting and determining an abnormality of an address output signal. The present invention detects address data and a clock output from the control unit of the plasma display panel to the address driver to detect address data corresponding to the clock. In this case, the plurality of switching ICs respectively detect the address data by operating an internal clock corresponding to the clock, and the digital signal processor controls the plurality of switching ICs to convert the address data detected by the plurality of switching ICs into the original image signal. The presence of abnormality of the plasma display panel is determined by comparing with the address data. Through this, it is possible to prevent the plasma display panel from being damaged in advance by determining whether the plasma display panel is abnormal.

PDP, DSP, Address Data, Switching IC

Description

Plasma display panel and anomaly detection method {PLASMA DISPLAY PANEL AND ABNORMALITY DETECTION METHOD THEREOF}

1 is a partial perspective view of an AC plasma display panel.

2 is a diagram illustrating an electrode array of a plasma display panel.

3 is a schematic plan view of a plasma display panel according to an embodiment of the present invention.

4 is a diagram showing in detail the address data detection / determination section and peripheral blocks according to the embodiment of the present invention.

5 is a diagram illustrating an internal block of the switching IC.

6 is a flowchart illustrating a method of detecting an abnormality of a plasma display panel according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) and a plasma display panel abnormality detection method, and more particularly, to a plasma display panel and a plasma display panel abnormality detection method for detecting and determining an abnormality of an address output signal. .

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display panel have been actively developed. Among these flat panel display devices, the plasma display panel has advantages of higher luminance and luminous efficiency and wider viewing angle than other flat panel display devices. Therefore, the plasma display panel is in the spotlight as a display device to replace a conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, the electrode is exposed without the discharge space insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for current limitation must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, the scan electrode 4 and the sustain electrode 5 covered with the dielectric layer 2 and the protective film 3 on the glass substrate 1 are formed in pairs in parallel. On the glass substrate 6, a plurality of address electrodes 8 covered with the insulator layer 7 are formed. The partition 9 is formed on the insulator layer 7 between the address electrodes 8 in parallel with the address electrode 8, and the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition 9. Is formed. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space at the intersection of the scan electrode 4 and the sustain electrode 5 paired with the address electrode 8 forms a discharge cell 12.

2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel are arranged in a matrix of m × n. Specifically, the address electrodes A1 -Am are arranged in the column direction and n rows of scan electrodes in the row direction ( Y1-Yn and sustain electrodes X1-Xn are arranged in a zigzag. The discharge cell 12 of FIG. 2 corresponds to the discharge cell 12 of FIG.

In general, the driving method of the AC plasma display panel includes a reset period, an address period, and a sustain period.

The reset period is a period for initializing the state of each cell in order to smoothly perform an addressing operation on the cell. The address period is an address voltage for a cell (addressed cell) that is turned on to select a cell that is turned on and a cell that is not turned on. It is a period of time to perform the operation to accumulate wall charge by applying a. The sustain period is a period in which a discharge is applied to actually display an image in the addressed cells by applying a sustain pulse.

In the address period, when a cell to be turned on and a cell not to be turned on are selected, when a scan voltage is sequentially applied to the scan electrodes Y1 to Yn, an address voltage is selectively applied to the address electrodes A1 to Am. Is applied. In this case, the application of the address voltage is controlled by a signal output by the logic unit (ie, the controller). When the plasma display panel is operated in a state where an abnormality occurs in the logic unit (ie, the controller), the address driving circuit is applied. This is directly connected to the burnout of an address driving IC (Integrated Circuit) and a power supply circuit, resulting in deterioration of the plasma display panel.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the prior art, and to detect an abnormal output of a logic unit (ie, a controller) of a plasma display panel by detecting an abnormal output of the plasma display panel and a plasma display panel. It is to provide.

Plasma display panel according to a feature of the present invention for achieving the above object is

A plasma display panel which divides an image of each field displayed on the plasma display panel in response to an input image signal into a plurality of subfields, and displays a gray level according to the combination of the subfields to display an image corresponding to the image signal. In

A control unit which receives the input video signal and the synchronization signal, divides one frame into several subfields, and generates and outputs a control signal corresponding to the subfields;

An address driver which receives address data, a synchronization signal, and an address control signal among the control signals output from the controller and applies the address data to an address electrode of the plasma display panel; And

Detecting the address data by using the address data and the synchronization signal output from the control unit to the address driver, and comparing the detected address data with the address data of the input image signal to determine the abnormality of the plasma display panel And an address data detection / determination section, wherein the input video signal is a still input video signal. At this time, the address data detection / determination unit is included in the plurality of switching ICs for detecting the address data by operating a clock contained therein corresponding to the synchronization signal, and in the plurality of switching ICs in response to the synchronization signal. And a digital signal processing unit for combining the address data outputted from the plurality of switching ICs by controlling the clock, and detecting the abnormality of the plasma display panel by comparing the combined address data with the address data of the input image signal. Characterized in that.

An abnormality detection method of the plasma display panel according to another aspect of the present invention

An abnormality of the plasma display panel in which an image of each field displayed on the plasma display panel in response to an input video signal is divided into a plurality of subfields, and a gray level is displayed according to the combination of the subfields to display an image corresponding to the video signal. In the method for detecting,

(a) detecting a synchronization signal input to an address driver included in the plasma display panel and detecting address data corresponding thereto;

(b) detecting a synchronization signal input after the detected synchronization signal in step (a) and detecting address data corresponding thereto; And

 (c) comparing the address data detected in steps (a) and (b) with the address data of the input video signal, wherein the input video signal is a still picture signal. In this case, when the address data are different from each other in the step (c), the method may further include displaying that the plasma display panel is abnormal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A plasma display panel and an abnormality detection method according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

3 is a schematic plan view of a plasma display panel according to an embodiment of the present invention.

As shown in FIG. 3, the plasma display panel according to the embodiment of the present invention includes a plasma panel 100, an address driver 200, a scan / hold driver 300, a controller 400, and an address data detection / determination unit ( 500).

The plasma panel 100 includes a plurality of address electrodes A1-Am arranged in the column direction, and a plurality of scan electrodes Y1-Yn and sustain electrodes X1-Xn arranged in a zigzag pattern in the row direction. . The address driver 200 may include address data, clocks, and address drive control signals of the input image signals (including R, G, and B data) output from the address output unit 420 (see FIG. 4) of the controller 400. Is applied to each of the address electrodes A1-Am to receive and select a discharge cell to be displayed. The scan / hold driver 300 receives a control signal from the control unit 400 (exactly, the scan / hold output unit of the control unit 400) and maintains a sustain voltage at the scan electrodes Y1-Yn and the sustain electrodes X1-Xn. Alternately inputs sustain discharge to the selected discharge cells.

The control unit 400 includes a plurality of logic blocks (for example, an address output unit, a scan / maintenance output unit, etc.), and receives R, G, and B image signals and a synchronization signal from an external source, and converts several frames into one frame. The plasma display panel is driven by dividing into subfields and dividing each subfield into a reset period, an address period, and a sustain discharge period. At this time, the controller 400 adjusts the number of sustain pulses in each sustain period of the subfield in one frame and supplies the necessary control signals to the address driver 200 and the scan sustain driver 300. In this case, the address output unit 420 (shown in FIG. 4) of the control unit 400 outputs address data, a clock, and a control signal of the input image signal to the address driver 200 and the address driver 200. Receives these signals and applies them to the address electrodes A1-Am to select the cell to be displayed.

The address data detection / decision unit 500 detects address data using address data and a clock of an input video signal output from the address output unit 420 of the controller 400 to the address driver 200. The controller 400 (ie, the logic unit) detects an abnormality by determining whether the input video signal is equal to the input video signal.

The following describes how the address data detection / decision unit 500 specifically detects the address data to determine whether there is an abnormality in the control unit (i.e., the logic unit).

4 is a diagram showing in detail the address data detection / decision unit 500 and peripheral blocks according to the embodiment of the present invention.

The address data detection / decision unit 500 according to an embodiment of the present invention includes seven switching ICs 520, 521, 522, 523, 524, 525, and 526 and a digital signal processing unit (DSP unit). 540). In this case, the DSP unit may be replaced by a microcontroller, and the number of the switching ICs may vary depending on the resolution of the plasma display panel.

The seven switching ICs 520, 521, 522, 523, 524, 525, and 526 respectively address data of an input video signal transmitted from the address output unit 420 of the controller 400 to the address IC of the address driver 200. Detect. In this case, for example, when the resolution is 852x480, the number of address electrodes is 852x3 (bit) = 2556, considering R, G, and B, and the input of the address IC included in the address driver 200 has 6 inputs. For bits and 96 channels of output, a total of 28 address ICs are required. Here, if four address ICs are grouped into one block COF, seven address IC blocks 220, 221, 222, 223, 224, 225, and 226 are required. Here, the switching IC and the address IC block are connected to each other. 4 illustrates the relationship between the address IC and the switching IC in the case where the resolution is 852 × 480, so that the number of the address ICs and the number of the switching ICs can vary depending on the resolution. Each of the switching ICs 520, 521, 522, 523, 524, 525, and 526 detects 12 bits of data in a switching operation, so that when four address ICs are grouped into one address IC block, each switching IC 520, 521, 522, 524, 524, 525, and 526 must be detected twice to detect 24 bits of address data (bits input into the address block IC are 24 bits). Therefore, two clocks (for example, Mclk1 and Mclk2) are required inside the switching IC. That is, the switching IC 1 520 alternately uses two clocks Mclk1 and Mclk2 to detect the first and third input data of the address IC block 220 (COF1) at Mclk1 and the address at Mclk2. The second and fourth input data of the IC block 220 (COF1) is detected. At this time, the DSP unit 540 detects the edges of the clocks Clk1 and Clk2 that are output from the address output unit 420 to the address IC block 220 and then the clocks Mclk1 and Mclk2 of the switching IC 1 520. ) To detect address data every 12 bits. Here, the other address IC blocks 221, 222, 223, 224, 225, and 226 also detect the address data of the input video signal under the control of the DSP unit 540 using two clocks.

In FIG. 4, the clocks output from the address output unit 420 to the address IC blocks 220, 221, 222, 223, 224, 225, and 226 are shown as Clk1 to Clk6, but Clk 1, 3, and 5 are clocks in the same state. And Clk 2, 4, 6 are the same clock. It uses different clocks for fan out of the circuit that generates the clocks, but in practice Clk 1, 3, 5 are the same clocks and Clk 2, 4, 6 are the same clocks as above. .

5 is a diagram illustrating an internal block of the switching IC. As shown in Fig. 5, the switching IC alternately detects the address data signal using ENABLE 1, 2 and the buffer. In this case, in the case of the switching IC 1 520, the enable 1 is connected to Mclk1 and operates in response to the Clk1 output from the address output unit 420 under the control of the DSP unit 540. 2 (ENABLE 2) is connected to Mclk2 and operates corresponding to Clk2 output from the address output unit 420 under the control of the DSP unit 540, and Mclk1 and 2 alternate with each other.

At this time, in FIG. 4, the clocks of the respective switching ICs 520, 521, 522, 523, 524, 525, and 526 are clocks, and the switching ICs 1,2 and 3 (520, 521, and 522) are clocks of Mclk1 and Mclk2. (clock) and switching ICs 4,5, 6 (523, 524, 525) use the clocks of Mclk3 and Mclk4, and switching IC7 526 use the clocks of Mclk7. Another clock is used as a problem of fan out in the clock generating circuit. Mclk1, Mclk3, Mclk5 are the same and Mclk2, Mclk4, Mclk6 are the same in the clock state.

Accordingly, the switching IC 1 to the switching IC 7 520, 521, 522, 523, 524, 525, and 526 are controlled by the DSP unit 540 so that each address IC block 220, 221 from the address output unit 420 can be controlled. The data corresponding to half of the address data output to 222, 223, 224, 225, and 226 are detected once corresponding to the clocks Clk1, Clk3, and Clk5, and the next clocks Clk2, Clk4, and Clk 6 are detected. Correspondingly, the other half of the address data is detected.

It is assumed here that the input video signal is a still image. Therefore, since the input image signal has the same address data in two frames, each switching IC 520, 521, 522, 523, 524, 525, 526 has two clocks Clk1, 3, 5 and Clk 2, The detection of address data in 4 and 6 does not cause any problem.

The DSP unit 540 combines the address data detected by the respective switching ICs 520, 521, 522, 523, 524, 525, and 526 to compare the address data of the originally input still image signal to compare the address data of the plasma display panel. Judge whether it is abnormal. That is, it is determined whether the plasma display panel is abnormal by comparing the address data of the still image signal that is originally input with the address data processed inside the plasma display panel. Here, it will be apparent to those skilled in the art that the DSP unit 540 may be replaced by a microcontroller and may be replaced by other means for comparing address data. In addition, since the DSP unit 540 compares the address data in detail and determines whether an abnormality is easily realized by those skilled in the art, a detailed description thereof will be omitted.

6 is a flowchart illustrating a method of detecting an abnormality of a plasma display panel according to an exemplary embodiment of the present invention.

 First, a still input image signal is input to the plasma display panel (S100 and S110). This may be forcibly made and input, even when the image signal input when the plasma display panel is operated is a still image signal.

In this case, the first synchronization signal Vsync of the input image signal is checked and the address output unit 420 is performed by the switching ICs 520, 521, 522, 523, 524, 525, and 526 described above and the DSP unit 540. Address data input to the address IC of the address driver is detected (S120, S130). At this time, only the address data synchronized with the clocks Clk1, 3, and 5 are detected by the first synchronization signal Vsync. This detects only half of the address data of the input still image signal.

 Next, in order to detect the remaining address data of the input image signal, it is checked whether the input synchronization signal is the second synchronization signal Vsync + 1 (S140). At this time, if the input video signal is not the address data of the second frame, step S130 is repeated. It is assumed that the address data of the second frame is not input.

When the second sync signal Vsync + 1 of the input video signal is input, the DSP unit 540 changes the internal clocks of the switching ICs 520, 521, 522, 523, 524, 525, and 526 so that the remaining address data is retained. (S150, S160). For example, the change from clock Mclk1 to switching Mclk2 of switching IC1 520 is detected to detect the remaining address data.

Next, the DSP unit 540 compares the detected address data with the address data of the input still image signal (170). In this case, when the data are the same, since there is no abnormality in the plasma display panel (S230).

However, if it is determined that the address data is different from the comparison of the address data, the DSP unit 540 may determine the abnormality of the logic unit (ie, the controller) of the plasma display panel to limit the operation of the plasma display panel. The signal is transmitted to the power supply to turn off the power supply (S180, S190). At this time, by installing an LED, which is a separate device in the plasma display panel to make it blink, it can be notified to the user (S200, S210). In this case, the user may be notified of the abnormality by displaying an abnormality on the plasma display panel with an alarm or the like.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

 As described above, according to the present invention, by detecting address data transmitted by the address driving of the plasma display panel from the control unit (ie, the logic unit) of the plasma display panel, the plasma display panel is determined in advance by determining whether there is an abnormality of the plasma display panel. The burnout of various devices can be prevented.

Claims (10)

A plasma display panel for dividing an image of each field displayed on a plasma display panel in response to an input video signal into a plurality of subfields, and displaying a gray level according to a combination of the subfields to display an image corresponding to the video signal. , A control unit which receives the input video signal and the synchronization signal, divides one frame into several subfields, and generates and outputs a control signal corresponding to the subfields; An address driver which receives address data, a synchronization signal, and an address control signal among the control signals output from the controller and applies the address data to an address electrode of the plasma display panel; And The controller detects the abnormality of the plasma display panel by detecting the address data by using the address data and the synchronization signal output from the controller to the address driver, and comparing the detected address data with the address data of the input image signal. Including address data detection and determination unit, And the input video signal is a still input video signal. The method of claim 1, The address data detection and determination section A plurality of switching ICs configured to detect the address data by operating a clock included therein corresponding to the synchronization signal; By controlling the clocks included in the plurality of switching ICs in response to the synchronization signal, the address data outputted from the plurality of switching ICs are combined, and the combined address data is compared with the address data of the input video signal. And a digital signal processor for detecting an abnormality of the plasma display panel. delete The method of claim 2, The plurality of switching ICs have two clocks included therein, and detect half of the address data when the first clock of the two clocks is operated, and the rest of the address data when the second clock is operated. And detecting the plasma display panel. The method of claim 4, wherein Two clocks included in each of the plurality of switching ICs are alternately operated by the digital signal processor. The method of claim 1, And when it is determined that the plasma display panel is abnormal by the address data detection / determination unit, the switching power supply included in the plasma display panel is turned off by the address data detection / determination unit. . An abnormality of the plasma display panel in which an image of each field displayed on the plasma display panel in response to an input video signal is divided into a plurality of subfields, and a gray level is displayed according to the combination of the subfields to display an image corresponding to the video signal. In the method for detecting, (a) detecting a synchronization signal input to an address driver included in the plasma display panel and detecting address data corresponding thereto; (b) detecting a synchronization signal input after the detected synchronization signal in step (a) and detecting address data corresponding thereto; And  (c) comparing the address data detected in steps (a) and (b) with address data of the input video signal, And the input image signal is a still image signal. The method of claim 7, wherein And displaying an abnormality in the plasma display panel when the address data is different from each other in the step (c). The method of claim 7, wherein And turning off a power supply included in the plasma display panel when the address data is different from each other in the step (c). delete

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