KR100549566B1 - Capacitor Formation Method of Semiconductor Device - Google Patents
Capacitor Formation Method of Semiconductor DeviceInfo
- Publication number
- KR100549566B1 KR100549566B1 KR1019980045871A KR19980045871A KR100549566B1 KR 100549566 B1 KR100549566 B1 KR 100549566B1 KR 1019980045871 A KR1019980045871 A KR 1019980045871A KR 19980045871 A KR19980045871 A KR 19980045871A KR 100549566 B1 KR100549566 B1 KR 100549566B1
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- forming
- capacitor
- tantalum oxide
- present
- Prior art date
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- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 title description 6
- 239000010409 thin film Substances 0.000 claims abstract description 40
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 34
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000010574 gas phase reaction Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000002425 crystallisation Methods 0.000 claims description 2
- 230000008025 crystallization Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000001939 inductive effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체장치의 캐퍼시터 형성방법에 관한 것으로, 반도체 캐퍼시터 소자의 유전체 박막 형성공정에서 탄탈륨옥사이드 박막 증착시 Al2O3와 같은 산화막(AlxOy)을 계면에 얇게 형성시킴으로써 하부전극인 폴리실리콘이 산화되어 전기적 특성이 열화되는 문제점을 개선시킨 캐퍼시터 형성방법에 관한 것이다. 본 발명에 따르면 종래의 탄탈륨옥사이드 캐퍼시터보다 큰 충전용량을 얻을 수 있으며, 같은 충전용량을 얻기 위한 종래의 이중 또는 삼중 구조의 캐퍼시터 모듈을 형성하는 종래의 공정보다 공정 시간을 단축할 수 있고, 생산 원가를 절감할 수 있다.The present invention relates to a method of forming a capacitor of a semiconductor device, and to forming a thin film of oxide (Al x O y ), such as Al 2 O 3 , at the interface during deposition of a tantalum oxide thin film in a dielectric thin film forming process of a semiconductor capacitor device. The present invention relates to a method of forming a capacitor which improves a problem in which silicon is oxidized to deteriorate electrical characteristics. According to the present invention, it is possible to obtain a larger charging capacity than a conventional tantalum oxide capacitor, and to shorten the process time compared to a conventional process of forming a capacitor module having a conventional double or triple structure to obtain the same charging capacity, and a production cost. Can reduce the cost.
Description
본 발명은 반도체 DRAM 제조공정에서 사용되는 새로운 전하저장전극(storage node electrode) 및 캐퍼시터의 형성방법에 관한 것으로서, 특히 MIS(Metal/Insulator/Silicon) 구조를 갖는 종래의 탄탈륨옥사이드 캐퍼시터에서 탄탈륨옥사이드 박막 증착시 Al2O3와 같은 산화막(AlxOy)을 계면에 얇게 형성시킴으로써 하부전극인 폴리실리콘이 산화되어 전기적 특성이 열화되는 문제점을 개선시킨 캐퍼시터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a new storage node electrode and a capacitor used in a semiconductor DRAM manufacturing process. In particular, a tantalum oxide thin film is deposited in a conventional tantalum oxide capacitor having a metal / insulator / silicon (MIS) structure. By forming a thin oxide film (Al x O y ), such as Al 2 O 3 at the interface thinner is a method of forming a capacitor that improves the problem that the polysilicon as the lower electrode is deteriorated electrical properties.
DRAM의 집적도가 64M에서 256M로 증가함에 따라, 셀의 크기의 감소는 더욱 가속화되고 있고, 이로 인하여 캐퍼시터의 면적감소는 필연적 요소가 되고 있다. 따라서, 한정된 면적에 큰 정전용량을 가지는 캐퍼시터를 실현시키기 위하여 유전율이 큰 캐퍼시터 유전체를 사용하려는 연구가 계속되어 왔으며, 이러한 노력의 결과로 종래에 사용되어 오던 Si3N4 보다 유전율이 높은 탄탈륨옥사이드(Ta2O5) 박막이 캐퍼시터의 유전막으로 사용되기에 이르렀다.As the density of DRAM increases from 64M to 256M, the reduction in cell size is further accelerated, which inevitably reduces the area of the capacitor. Therefore, studies have been made to use a capacitor dielectric with a high dielectric constant to realize a capacitor having a large capacitance in a limited area, and as a result of this effort, a tantalum oxide having a higher dielectric constant than Si 3 N 4 has been used. Ta 2 O 5 ) thin film has been used as the dielectric film of the capacitor.
반도체 DRAM 소자에 사용되는 탄탈륨옥사이드 캐퍼시터를 제조하는 방법은 도 1 에 도시된 바와 같이 전하저장전극(storage node)인 하부전극(bottom electrode)으로 도프트 폴리실리콘(doped polysilicon)을 사용하고, 그 층위에 유전체 막으로서 탄탈륨옥사이드 박막을 PECVD, LPCVD, UV-photo-CVD, RF 마그네틱 스퍼터링 등과 같은 방법을 사용하여 증착한다. 또한 상부전극(plate electrode)은 TiN을 사용하거나 폴리실리콘을 함께 적층하여 DRAM 용 캐퍼시터를 형성하여 사용하고 있다. A method of manufacturing a tantalum oxide capacitor used in a semiconductor DRAM device uses a doped polysilicon as a bottom electrode, which is a storage node, as shown in FIG. 1, and a layer thereof. As a dielectric film, a tantalum oxide thin film is deposited using a method such as PECVD, LPCVD, UV-photo-CVD, RF magnetic sputtering, or the like. In addition, the upper electrode (plate electrode) is used to form a capacitor for DRAM by using TiN or by stacking polysilicon together.
최근에는 탄탈륨옥사이드 박막의 질이 우수한 PECVD와 상대적으로 박막의 질은 떨어지지만 스텝커버리지(step coverage)가 우수한 LPCVD 방법을 주로 이용하여 탄탈륨옥사이드 박막을 증착하고 있다. 그러나, 상기 어느 방법을 이용하든지 관계없이 탄탈륨옥사이드 박막은 그 자체가 불안정한 화학양론비(stoichiometry)를 갖고 있기 때문에 Ta 과 O의 조성비 차이에 기인한 치환형 Ta 원자(vacancy atom)가 박막 내에 존재하게 된다. 그리고, 탄탈륨옥사이드의 전구물질인 Ta(OC2H5)5, TaCl5 등의 금소유기화합물(metal-organic)과 O2 (또는 N2O) 가스의 반응으로 인하여 불순물인 탄소원자와 탄소화합물(C, CH4 등) 및 물(H2O)도 함께 존재하게 된다.Recently, tantalum oxide thin films are mainly deposited using PECVD which has excellent quality of tantalum oxide thin film and LPCVD method which has relatively low quality but thin film quality of step coverage. However, regardless of which method is used, the tantalum oxide thin film itself has an unstable stoichiometry so that a substitutional Ta atom (vacancy atom) due to the difference in the composition ratio of Ta and O exists in the thin film. do. Then, the precursor of the tantalum oxide Ta (OC 2 H 5) 5 , TaCl 5 , etc. geumso organic compound (metal-organic) and O 2 (or N 2 O) due to reaction impurities, carbon and carbon compounds of the gas (C, CH 4, etc.) and water (H 2 O) will also be present.
결국 탄탈륨옥사이드 박막내에 불순물로 존재하는 탄소원자, 이온 및 라디칼로 인하여 캐퍼시터의 누설전류가 증가하게 되고, 유전특성이 열화되는 문제를 내포하고 있다.As a result, the leakage current of the capacitor is increased due to the carbon atoms, ions, and radicals present as impurities in the tantalum oxide thin film, and the dielectric properties are deteriorated.
한편, 이와 같은 전기적 특성을 개선하기 위해 O2, N2O 또는 UV-O3 분위기에서 고온 어닐링 공정을 추가로 진행하거나 탄탈륨옥사이드 박막 증착시 병행하고 있다. 이와같은 과정을 통해서 산화제인 O2 성분이 폴리실리콘과 탄탈륨옥사이드 박막의 계면으로 이동하여 저유전율 층인 산화막(SiO2)(5)이 형성됨으로써 등가산화막이 증가하게 된다. 결국 탄탈륨옥사이드의 유전율(ε)이 25임에도 불구하고 종래에는 탄탈륨옥사이드 박막(30)을 80∼150Å 정도 증착할 때 사실상 도 1 에서와 같이 폴리실리콘(10)과의 계면에 실리콘이 산화된 SiOxNy과 같은 저유전율층의 산화막 (ε=4∼5)(15)이 10∼20Å 정도가 형성되기 때문에 충전용량이 종래의 Si3N4/SiO2(NO) 커패시터에 비해 1.5 배 정도 밖에 향상되지 못하고 있는 실정이다.On the other hand, in order to improve such electrical characteristics, the high temperature annealing process is further performed in O 2 , N 2 O or UV-O 3 atmosphere or tantalum oxide thin film deposition in parallel. Through this process, the oxidant O 2 component is moved to the interface between the polysilicon and tantalum oxide thin film to form an oxide layer (SiO 2 ) 5 which is a low dielectric constant layer, thereby increasing the equivalent oxide film. After all, even though the dielectric constant (ε) of tantalum oxide and silicon oxide 25 at the interface between the polysilicon 10, as the prior art, the tantalum oxide thin film 30 and in fact Figure 1 when depositing SiO x about 80~150Å Since the oxide film (ε = 4 to 5) (15) of the low dielectric constant layer such as N y is formed in about 10 to 20 mV, the charge capacity is only about 1.5 times that of the conventional Si 3 N 4 / SiO 2 (NO) capacitor. The situation is not improving.
따라서, 본 발명이 이루고자 하는 기술적 과제는 TiN/Ta2O5/도프트 폴리실리콘과 같은 MIS(Metal/Isulator/Silicon) 구조를 갖는 탄탈륨옥사이드 캐퍼시터에서 하부전극 위에 Al2O3와 같은 산화막(AlxOy)을 얇게 형성시켜 종래의 탄탈륨옥사이드 캐퍼시터에서 탄탈륨옥사이드 박막 증착시 하부전극인 폴리실리콘이 산화되어 전기적 특성이 열화되는 문제점을 개선시킨 캐퍼시터 형성방법을 제공하는 데에 있다.Accordingly, an object of the present invention is to provide an oxide film such as Al 2 O 3 on a lower electrode in a tantalum oxide capacitor having a metal / isulator / silicon (MIS) structure such as TiN / Ta 2 O 5 / doped polysilicon. The present invention provides a method of forming a capacitor which improves a problem of deteriorating electrical characteristics by oxidizing polysilicon as a lower electrode when depositing a thin film of tantalum oxide in a conventional tantalum oxide capacitor by forming a thin layer of x O y ).
상기 기술적 과제를 달성하기 위한 본 발명에 따르는 캐퍼시터 형성방법은 반도체 캐퍼시터 소자의 유전체 박막 형성공정에서 도프트 폴리실리콘과 감광막을 증착하고 식각하여 하부전극을 형성하는 단계; Al2O3 박막을 형성하는 단계; 및 탄탈륨옥사이드 박막을 증착하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, a method of forming a capacitor includes depositing and etching a doped polysilicon and a photosensitive layer in a dielectric thin film forming process of a semiconductor capacitor device to form a lower electrode; Forming an Al 2 O 3 thin film; And depositing a tantalum oxide thin film.
본 발명의 캐퍼시터 형성방법에서 Al2O3 박막 형성단계 및 탄탈륨옥사이드 박막 형성단계는 LPCVD 방법으로 수행하는 것이 바람직하며, 300∼600℃ 1torr 이하의 LPCVD 챔버내에서 기상반응을 억제시키면서 Al(OC2H5)3 용액과 Ta(OC2H5)5 용액을 각각 180∼250℃와 150∼200℃ 온도 범위내에서 증발시켜 얻은 화학증기를 이용하여 형성시킬 수 있다.In the capacitor forming method of the present invention, the Al 2 O 3 thin film forming step and the tantalum oxide thin film forming step are preferably performed by the LPCVD method, and the Al (OC 2) while suppressing the gas phase reaction in the LPCVD chamber of 300 to 600 ° C. H 5 ) 3 solution and Ta (OC 2 H 5 ) 5 solution can be formed using chemical vapor obtained by evaporation within the temperature range of 180 ~ 250 ℃ and 150 ~ 200 ℃, respectively.
본 발명의 캐퍼시터 형성방법에서는 Al2O3 박막 형성단계 및/또는 탄탈륨옥사이드 박막형성단계에서 박막형성후 추가로 어닐링 하는 단계를 포함할 수 있으며, 이 어닐링 방법은 RTP(Rapid Thermal Process) 또는 전기로(furnace)를 사용하여 800∼900℃에서 N2O 또는 O2 분위기에서 30초∼30분 정도 어닐링시키는 것이 바람직하며, 이 과정을 거침으로써 결정화를 유도하고, 일부 잔존해있는 탄소 및 수소성분을 산화제거하여 유전률을 증가시킬 수 있다.The capacitor forming method of the present invention may include annealing after the thin film formation in the Al 2 O 3 thin film forming step and / or tantalum oxide thin film forming step, the annealing method is RTP (Rapid Thermal Process) or electric furnace ( It is preferable to anneal for 30 seconds to 30 minutes in an N 2 O or O 2 atmosphere at 800 to 900 ° C. using a furnace), which induces crystallization and oxidizes some remaining carbon and hydrogen components. Can increase the permittivity.
이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 2 내지 도 6 은 본 발명의 실시예에 따른 캐퍼시터 형성방법을 설명하기 위한 캐퍼시터의 단면도이다.2 to 6 are cross-sectional views of a capacitor for explaining a method of forming a capacitor according to an embodiment of the present invention.
먼저, 도 2 에서와 같이 콘택이 형성된 실리콘 기판상에 도프트 폴리실리콘(10)을 증착하고 전하저장전극을 형상화하기 위해 감광막(20)을 덮고 식각하여 도 3 에서와 같이 간단한 스택 구조의 하부전극을 형성한다.First, as shown in FIG. 2, the doped polysilicon 10 is deposited on the silicon substrate on which the contact is formed, and the lower electrode of the simple stacked structure as shown in FIG. 3 is covered by etching and covering the photoresist film 20 to shape the charge storage electrode. To form.
여기에 MFC (Mass Flow Controller)와 같은 유량 조절기를 통해 증발기 또는 증발관으로 공급된 일정량의 Al(OC2H5)3 용액을 180∼250℃ 온도 범위에서 증발시켜 얻은 Al 성분의 화학증기를 반응가스인 과잉 O2 가스와 함께 LPCVD 챔버내에서 300∼600℃ 1torr 이하의 LPCVD 챔버내에서 기상반응을 억제시키면서 표면반응시켜 도 4에서와 같이 Al2O3 박막(30)을 형성한다.The chemical vapor of the Al component obtained by evaporating a predetermined amount of Al (OC 2 H 5 ) 3 solution supplied to the evaporator or the evaporation tube through a flow controller such as MFC (Mass Flow Controller) at a temperature range of 180 to 250 ° C In the LPCVD chamber together with the excess O 2 gas, which is a gas, the Al 2 O 3 thin film 30 is formed by surface reaction while suppressing the gas phase reaction in the LPCVD chamber of 300 to 600 ° C. or less.
그 다음에 Al2O3 박막형성과정과 마찬가지로 유량 조절기를 통해 증발기 또는 증발관으로 공급된 일정량의 Ta(OC2H5)5 용액을 150∼200℃ 온도 범위내에서 증발시켜 얻은 Ta 성분의 화학증기를 반응가스인 과잉 O2 가스와 함께 LPCVD 챔버내에서 300∼600℃ 1torr 이하의 LPCVD 챔버내에서 기상반응을 억제시키면서 표면반응시켜 도 5에서와 같이 탄탈륨옥사이드 박막(40)을 형성한다.Then, as in the Al 2 O 3 thin film formation process, the chemical composition of the Ta component obtained by evaporating a predetermined amount of Ta (OC 2 H 5 ) 5 solution supplied to the evaporator or the evaporator tube through a flow controller within a temperature range of 150 to 200 ° C. Vapor is reacted with excess O 2 gas, which is a reactant gas, in a LPCVD chamber to surface-react while suppressing gas phase reaction in an LPCVD chamber of 300 to 600 ° C. or less, and to form a tantalum oxide thin film 40 as shown in FIG. 5.
이렇게 얻어진 탄탈륨옥사이드 박막(40)을 800∼900℃, N2O(또는 O2) 분위기에서 RTP(Rapid Thermal Process) 또는 전기로에서 1∼30분 정도 어닐링시킨 다음, 도 6 에서와 같이 600∼700℃, 1∼50torr 분위기의 단일 챔버내에서 TiCl4를 사용하여 CVD 방식으로 비정질 탄탈륨옥사이드 박막(40) 위에 TiN 막(50)을 200∼1000Å 두께로 적층하여 상부전극을 형성하고 도프트 폴리실리콘(60)을 적층시켜 상부전극을 형성함으로써 캐퍼시터 형성공정을 완료한다.The tantalum oxide thin film 40 thus obtained is annealed for about 1 to 30 minutes in a rapid thermal process (RTP) or an electric furnace in an atmosphere of N 2 O (or O 2 ) at 800 to 900 ° C., and then 600 to 700 as shown in FIG. 6. The TiN film 50 was deposited on the amorphous tantalum oxide thin film 40 by CVD using TiCl 4 in a single chamber of 1 to 50 torr atmosphere to form a top electrode to form a top electrode. 60) is stacked to form the upper electrode to complete the capacitor formation process.
본 발명의 또 다른 실시예에서는 상기 실시예에서와 같이 하부전극을 형성하고, Al2O3 박막을 형성한 다음 추가로 800∼900℃, N2O(또는 O2) 분위기에서 RTP 또는 전기로에서 30초∼30분 정도 어닐링시키고, 후속 상부전극을 형성시키는 캐퍼시터 형성공정을 제공한다.In another embodiment of the present invention, as in the above embodiment, the lower electrode is formed, an Al 2 O 3 thin film is formed, and then additionally 800 to 900 ° C. in an N 2 O (or O 2 ) atmosphere in an RTP or electric furnace. A capacitor forming step of annealing for about 30 seconds to 30 minutes and forming a subsequent upper electrode is provided.
본 발명에 따르면, 하부전극인 폴리실리콘의 산화로 인하여 저유전층인 SiO2 (ε=3.9)막이 형성되는 것을 방지하고, 유전율이 큰 Al2O3 박막 (ε=9.3)을 계면에 형성시킴으로써 종래의 탄탈륨옥사이드 캐퍼시터보다 큰 충전용량을 얻을 수 있기 때문에 캐퍼시터 모듈이 간단한 스택 구조라 하더라도 256M 급 이상의 DRAM에서 요구되는 25fF/cell 이상의 충전용량을 충분히 얻을 수 있다.According to the present invention, the SiO 2 (ε = 3.9) film, which is a low dielectric layer, is prevented from being formed due to oxidation of polysilicon, which is a lower electrode, and an Al 2 O 3 thin film having high dielectric constant (ε = 9.3) is formed at the interface. Since the charging capacity is larger than that of the tantalum oxide capacitor of, even if the capacitor module has a simple stack structure, the charging capacity of 25 fF / cell or more required in the DRAM of 256M or more can be sufficiently obtained.
또한, 같은 충전용량을 얻기 위한 종래의 이중 또는 삼중 구조의 캐퍼시터 모듈을 형성하는 종래의 공정보다 공정 시간을 단축할 수 있고, 생산 원가를 절감할 수 있다. In addition, it is possible to shorten the process time and reduce the production cost than the conventional process of forming a conventional double or triple capacitor module to obtain the same charge capacity.
또한, 종래의 탄탈륨옥사이드 박막 형성시 하부전극인 폴리실리콘의 산화로 인한 실리콘 산화막 형성을 막기위한 전처리 세정공정 및 RTN(Rapid Thermal Nitridation)과 같은 별도의 질화공정이 필요하지 않으므로 더욱 경제적이다.In addition, the conventional tantalum oxide thin film formation is more economical because it does not require a separate nitriding process such as a pre-treatment cleaning process and rapid thermal nitridation (RTN) to prevent the formation of a silicon oxide film due to oxidation of polysilicon as a lower electrode.
한편, 구조적으로도 기계적, 전기적 강도가 우수한 Al2O3 와 같은 산화막이 탄탈륨옥사이드 박막과 계면사이에 얇게 형성되어 누설전류에 대한 장벽 역할을 해주므로 종래의 탄탈륨옥사이드 캐퍼시터보다 누설전류의 수준이 낮아지고 절연파괴 전압이 높아져 전기적 특성이 우수하다.On the other hand, since the oxide film such as Al 2 O 3 having excellent mechanical and electrical strength is formed thinly between the tantalum oxide thin film and the interface to act as a barrier against leakage current, the level of leakage current is lower than that of the conventional tantalum oxide capacitor. High electrical breakdown voltage.
도 1 은 종래의 캐퍼시터 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a conventional capacitor forming method.
도 2 은 내지 6 은 본 발명의 실시예에 따른 캐퍼시터 형성방법을 설명하기 위한 캐퍼시터 구조도이다.2 to 6 is a structure diagram of a capacitor for explaining a method of forming a capacitor according to an embodiment of the present invention.
* 도면 중의 주요 부분에 대한 부호설명** Explanation of Codes on Major Parts of Drawings *
10 : 도프트 폴리실리콘 20 : 감광막10: doped polysilicon 20: photosensitive film
30 : 산화알루미늄막 40 : 탄탈륨옥사이드막30 aluminum oxide film 40 tantalum oxide film
50 : TiN 막 60 : 도프트 폴리실리콘50: TiN film 60: doped polysilicon
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| KR19990018186A (en) * | 1997-08-26 | 1999-03-15 | 윤종용 | Semiconductor devices |
| KR19990084635A (en) * | 1998-05-08 | 1999-12-06 | 정선종 | Ferroelectric Transistor Memory Devices |
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| KR930003383A (en) * | 1991-07-03 | 1993-02-24 | 김광호 | Semiconductor device and manufacturing method thereof |
| KR19990018186A (en) * | 1997-08-26 | 1999-03-15 | 윤종용 | Semiconductor devices |
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