KR100536315B1 - Semiconductor packaging substrate and manufacturing method thereof - Google Patents

Abstract

The present invention forms a cavity in which a semiconductor device is built in one side of the carrier metal layer, and forms a multi-layered circuit layer by a build-up on the other side, and then the semiconductor device and the circuit layer By forming a structure electrically connected to each other, the present invention relates to a semiconductor package substrate and a method for manufacturing the thin plate build-up circuit layer.

Description

Semiconductor packaging substrate and manufacturing method

The present invention relates to a semiconductor package substrate and a method of manufacturing the same.

More specifically, a multilayer coreless circuit layer is formed on one side of the carrier metal layer by a build-up, and the semiconductor element die-attached to the circuit layer on the other side. The present invention relates to a semiconductor package substrate having a cavity in which is embedded and a method of manufacturing the same.

As electronic products become smaller and thinner, thinner, denser, more compact, and smaller in size, more and more, multilayer printed circuit boards are also undergoing fine patterns, miniaturization, and packaging. Accordingly, in order to increase the micropattern formation, reliability, and design density of multilayer printed circuit boards, there is a tendency to change the structure of the multilayer structure of the circuit together with the change of raw materials, and the parts are also SMT (Dual In-Line Package) type. As the surface mount technology type is changed, the mounting density is also increasing. In addition to the portableization of electronic devices, high functionalization, the Internet, moving pictures, and high-capacity data transmission and reception make the design of printed circuit boards complicated and require high-level technology.

The printed circuit board includes a single-sided PCB in which wiring is formed only on one side of the insulated substrate, a double-sided PCB in which wiring is formed on both sides, and an MLB (Multi Layered Board) that is wired in multiple layers. In the past, single-sided PCBs were used because of simple components and simple circuit patterns. However, in recent years, due to increased complexity of circuits and increased demand for high-density and miniaturized circuits, it is common to use double-sided PCBs or MLBs. The present invention relates to a process for producing MLB among them.

The MLB is an additional wiring layer formed to enlarge the wiring area. Specifically, MLB is divided into an inner layer and an outer layer, and a four-layer MLB (two inner layers and two outer layers) having a thin core (T / C) as a material of the inner layer and pre-gluing the outer layer and the inner layer with a preplex. Floor). That is, the multilayer printed circuit board has at least four layers. As the complexity of the circuit increases, it may be composed of six, eight, and ten or more layers.

A power circuit, a ground circuit, a signal circuit, and the like are formed in the inner layer, and a preplex is sandwiched between the inner layer and the outer layer or between the outer layers to insulate and bond. At this time, the wiring of each layer is connected using a via hole (conducting hole).

MLB has a great advantage that it can significantly increase the wiring density, but there is a difficulty that the manufacturing process is complicated. In particular, since the inner layer is not deformable when the process is completed according to the conventional build-up method, if there is an error in the inner layer, all the finished products become defective. Many inspection devices have been developed and used to prevent such errors in advance.

Hereinafter, a manufacturing process of a package substrate formed by a conventional build-up method will be described in detail with reference to FIG. 1.

Here, the build-up method refers to a manufacturing method of forming an inner layer on which a circuit pattern is formed, and additionally stacking outer layers one by one.

First, as shown in FIG. 1A, a copper clad laminate (CCL) 101 having a thin copper foil 102 formed on both surfaces thereof is provided through an insulating layer 103.

Here, the copper-clad laminate 101 is a disk made of a printed circuit board is generally a thin laminated plate with a thin copper coating on the insulating layer, depending on the purpose of use, glass / epoxy copper-clad laminate, heat-resistant resin copper-clad laminate, paper / phenol copper-clad laminate There are many kinds of high frequency copper clad laminates, flexible copper clad laminates (polyimide films) and composite copper clad laminates, but glass / epoxy copper clad laminates are mainly used for double-sided PCBs and multilayer PCBs.

Glass / epoxy copper clad laminates are made of copper foil and reinforcing substrates that have impregnated epoxy resin (a combination of resin and hardener) into glass fibers. Glass / epoxy copper clad laminates are classified according to reinforcement materials. Generally, grades according to reinforcement materials and heat resistance are determined by standards set by the National Electrical Manufacturers Association (NEMA), such as FR-1 to FR-5. have. Among these grades, FR-4 is most commonly used, but in recent years, the demand for FR-5, which has improved the Tg (glass transition temperature) characteristics of resins, has also increased.

Thereafter, as shown in FIG. 1B, via holes 104 for interlayer connection are formed in the copper-clad laminate 101 by drilling.

As described above, after forming the via hole 104 in the copper foil laminated disc 101, as shown in Figure 1c, by performing electroless copper plating and electrolytic copper plating on the copper foil layer and the via hole copper plating layer 105 To form.

Here, electroless copper plating is performed first and then electrolytic copper plating is performed because electrolytic copper plating that requires electricity cannot be performed on the insulating layer. That is, in order to form the electroconductive film required for electrolytic copper plating, electroless copper plating is thinly performed as the pretreatment. Since electroless copper plating has a disadvantage in that it is difficult to process and economical, it is preferable to form the conductive portion of the circuit pattern by electrolytic copper plating.

After the electroless and electrolytic copper plating is performed as described above, as shown in FIG. 1D, paste is applied to the inner region of the via hole to protect the electroless and electrolytic copper plating layer 105 formed on the inner wall of the via hole 104. Fill (106).

Here, the paste 106 generally uses an insulating ink material, but a conductive paste may also be used depending on the purpose of the printed circuit board. The conductive paste is obtained by mixing a metal such as Cu, Ag, Au, Sn, Pb as a main component alone or in an alloy form with an organic adhesive. However, this paste filling process may be omitted depending on the purpose of producing MLB.

As described above, after the paste is filled in the inner region of the via hole, as shown in FIG. 1E, an etching resist pattern 107 for forming a circuit pattern of the inner layer circuit is formed.

In order to form the etching resist pattern 107, the circuit pattern printed on the artwork film must be transferred onto the substrate. There are various methods of transferring, but the most commonly used method is a method of transferring a circuit pattern printed on an artwork film by ultraviolet light to a dry film using a photosensitive dry film. Recently, LPR (Liquid Photo Resist) is used instead of dry film.

The dry film or LPR to which the circuit pattern is transferred serves as the etching resist 107, and when the substrate is immersed in the etching solution, as shown in FIG. 1F, the copper foil layer in the region where the etching resist pattern 107 is not formed. 105 is removed to form a predetermined circuit pattern.

After the circuit pattern is formed, the appearance of the circuit is inspected by AOI (Automatic Optical Inspection) or the like to check whether the inner layer circuit is properly formed thereon, and the surface treatment such as black oxide treatment is performed.

AOI (Automatic Optical Inspection) is a device that automatically inspects the appearance of the PCB. The device automatically checks the appearance of the substrate using image sensors and computer pattern recognition technology. The pattern information of the circuit to be inspected is read by the image sensor and compared with the reference data to read the defect.

Using AOI inspection, it is possible to inspect the minimum of the annular ring of the land (the part where the component of the PCB will be mounted) and the ground state of the power supply. In addition, the width of the wiring pattern can be measured and missing holes can be checked. It is not possible to check the condition inside the hall.

A blackening process is a process performed to strengthen adhesive force and heat resistance, before bonding the inner layer in which the wiring pattern was formed with an outer layer.

After the circuit pattern is formed as described above, as shown in FIG. 1G, both sides of the substrate are laminated using Resin Coated Copper (RCC) or a coreless material.

In this invention, the method to form using RCC is demonstrated.

Here, the RCC is a substrate in which the copper foil layer 109 is formed only on one surface of the resin layer 108, and the resin layer 108 serves as an insulator between the circuit layers.

Thereafter, as illustrated in FIG. 1H, the blind via hole 110 serving as a folding connection between the inner layer and the outer layer is processed.

In this case, the blind via hole 110 may be mechanical drilling, but it is preferable to use YAG (Yttrium Aluminum Garnet) laser or CO2 laser because it requires more precise processing than when processing the through hole. The YAG laser is a laser capable of processing both a copper foil layer and an insulating layer, and the CO2 laser is a laser capable of processing only an insulating layer.

After forming the blind via hole as described above, as illustrated in FIG. 1I, the outer layer 111 is laminated by a plating process.

Thereafter, as illustrated in FIG. 1J, the circuit pattern is formed on the outer layer by using the same method as the above-described inner circuit pattern forming method on the outer layer 111. Then, circuit inspection and surface treatment are performed again, similarly after forming an inner layer circuit pattern.

Thereafter, as shown in FIG. 1K, lamination is performed on both sides of the substrate using RCC or coreless materials for additional outer layer deposition.

In this invention, the method to form using RCC is demonstrated.

Here, the RCC also includes a resin layer 112 and a copper foil layer 113 on one side, and the resin layer 112 serves as an insulator from other circuit layers.

After forming the RCC layer as described above, as shown in FIG. 1L, the blind via hole 114 for connection between the original outer layer and the additional outer layer is processed by laser drilling as described above.

Thereafter, as shown in FIG. 1M, an additional outer layer 115 is laminated by a plating process.

After the additional outer layer 115 is formed as described above, as illustrated in FIG. 1N, a bump is formed to die attach the semiconductor chip by performing a predetermined circuit pattern process on the added outer layer 115. To form a region 116.

Thereafter, as shown in FIG. 10, a die attach bump 117 formed of solder paste for attaching the semiconductor element is finally formed, thereby forming a six-layer package substrate.

After forming the final package substrate as described above, as shown in Figure 1p, by attaching a predetermined semiconductor element 118 to the die attach bump 117 and then performing a molding process, The semiconductor package was formed.

However, in the case of the conventional semiconductor package, since the build-up layer is formed on the upper and lower layers of the CCL-type thick core layer, the thickness of the substrate is inevitably thick, which makes it impossible to cope with high density, high speed, and miniaturization. In addition, there was a problem in forming the integration of the system.

In addition, since the semiconductor package has a build-up layer formed on the upper and lower layers of the CCL-type thick core layer as described above, there is a limit to cope with the trend of lighter and shorter reduction, as well as the manufacturing cost as it is multi-layered in response to high functionalization. There was also a problem of rapidly increasing.

According to the present invention, in order to solve the above problems, a cavity in which a semiconductor device is built is formed on one side of the carrier metal, and a multilayer circuit layer is formed on the other side by a build-up. The present invention provides a semiconductor package substrate and a method of manufacturing the same.

The semiconductor package substrate according to the present invention for achieving this object, the carrier metal layer; A circuit layer formed on one side of the carrier metal layer by a buildup method; A cavity formed by an etching process on the other side of the carrier metal layer and in which a semiconductor element die-attached with the circuit layer is embedded; And a molding part configured to mold the cavity having the semiconductor chip embedded therein into a predetermined insulating member.

In addition, another method of manufacturing a semiconductor package according to the present invention includes a first step of providing a core layer having a structure in which a pair of carrier buried layers oppose each other through an adhesive material; A second step of forming a circuit layer by a build-up method on one side of the carrier buried layer constituting the core layer; A third step of dissolving the adhesive material of the core layer by a predetermined method to separate the carrier buried layer in which the circuit layer is formed; A fourth step of forming a cavity for embedding the semiconductor device by an etching process on the other side of the separated carrier buried layer; Die attaching the semiconductor element embedded in the cavity to the circuit layer by bump bonding; And a sixth step of molding the cavity having the semiconductor device embedded therein using a predetermined insulating member.

Hereinafter, a package substrate and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

First, with reference to FIG. 2, the structure of the package substrate in which the multilayer circuit layer by the buildup system which concerns on this invention is formed is demonstrated.

As shown in FIG. 2, the semiconductor package substrate 100 having the build-up circuit layer according to the present invention includes a cavity 130 in which the carrier metal layer 110, the circuit layer 120, and the semiconductor device 140 are embedded. ) And the molding unit 150.

That is, the carrier buried layer 110, as shown in Figure 3, the core member 1000 having a three-layer structure having a structure attached to the carrier buried layer 110 to face each other via the adhesive 200. Heat treatment at a predetermined temperature or by dissolving the adhesive 200 using a solvent, the carrier buried layer 110 is formed to be separated from the core member 1000.

Here, the carrier metal layer 110 serves as a support for the circuit layer 120 formed on one side by a build-up method, such as aluminum (Al), nickel (Ni), copper (Cu), and the like. It is made of metal.

That is, the circuit layer 120 having a multilayer structure formed by a build-up method is formed on one side of the carrier metal layer 110.

At this time, one side of the carrier metal layer 110 on which the circuit layer 120 is formed to prevent damage to the circuit layer 120 by a nicking process for forming the cavity 130. A metal barrier layer (not shown) may be formed.

Here, the metal barrier layer serves to prevent damage to the circuit layer formed by the build-up method, and is formed on one side of the carrier metal layer on which the circuit layer is formed by nickel plating.

That is, the metal barrier layer serves to prevent damage to the circuit layer in the process of performing an etching process for forming a cavity for embedding a semiconductor device on the other side of the carrier metal layer.

In addition, on the other side of the carrier metal layer 110, a cavity 130 in which a semiconductor element or a passive element 140 as an active element is embedded is formed by a predetermined etching process.

Here, the cavity 130 serves as a heat sink that performs heat dissipation for the passive element or the active element 140 that is die attached to the circuit layer 120 formed by the build-up method.

The circuit layer 120 is a multilayer circuit layer formed by a build-up on one side of the carrier metal layer 110, and the cavity formed on the other side of the carrier buried layer 110. 130 is electrically connected to a passive element or an active element 140 which is die attached to it.

Here, the circuit layer 120 formed by the build-up method is not formed by the build-up method using a thick core layer in the form of a conventional copper clad laminate, but using the carrier metal layer 110 as a core layer. It is a built-up thin coreless circuit layer.

Accordingly, in the semiconductor package substrate 100 according to the present invention, since the circuit layer 120 is not formed on both sides of a thick core layer in the form of a copper clad laminate disc, the semiconductor package substrate 100 has a high density, high speed, and a miniaturized semiconductor package. It can form.

The semiconductor device 140 is embedded in the cavity 130 formed in the carrier metal layer 110 and die-attached to the circuit layer 120. The semiconductor device 140 may include not only active devices such as semiconductor chips, but also capacitors, resistors, and coils. It may be a passive element.

As described above, the die 130 is attached to the cavity 130 of the carrier metal layer 110 by the semi-element element 140, which is an active element or a passive element, and then the cavity 130 is defined as a predetermined charging member, more specifically. By forming the molding unit 150 by molding using a resin, thereby finally forming the semiconductor package 100 on which the circuit layer 120 is formed by a build-up method that can cope with high density, high productivity and high speed.

Hereinafter, a semiconductor package manufacturing process in which a buildup circuit layer according to the present invention is formed will be described in detail with reference to FIG. 4.

First, as shown in FIG. 4A, a core member 1000 having a structure in which a pair of carrier buried layers 110 are formed to face each other via an adhesive 200 is provided.

Here, the carrier buried layer 110 is made of metal such as aluminum (Al), nickel (Ni), copper (Cu), and serves as a support for the build-up circuit layer 120 formed on one side. Rather, it serves as a core layer for the build-up circuit layer 110.

4B and 4C, a predetermined circuit pattern 400 is formed using the dry film 300 having the circuit pattern formed on one side of the carrier metal layer 110.

In this case, before the circuit pattern 400 is formed, a metal barrier layer (not shown) may be formed by performing nickel plating on one side of the carrier metal layer 110.

Here, the metal barrier layer serves to prevent damage to the circuit layer by an etching process for forming the cavity 130 in which the semiconductor device 140 is embedded on the other side of the carrier metal layer 110. Do this.

After the circuit pattern 400 is formed on one side of the carrier metal layer as described above, as shown in FIG. 4D, the insulating layer 500 is formed on the carrier buried layer 110 in which the circuit pattern 400 is formed. Laminate

Thereafter, as illustrated in FIG. 4E, the via hole region 600 is formed by performing laser processing on the insulating layer 500 and via hole processing using a CNC drill.

After the via hole region is formed as described above, as shown in FIG. 4F, the carrier buried layer 110 is formed by performing electroplating on the formed via hole region 600 or filling the conductive paste 700. The via-interconnect with the circuit pattern 400 formed in FIG.

Thereafter, as shown in FIG. 4G, the multi-layer circuit layer 120 is formed on the carrier metal layer 110 of the core member 1000 layer by a build-up method by a conventional semi-additive process. Form.

After the build-up circuit layer is formed on one side of the carrier metal layer as described above, as shown in FIG. 4H, the core member 1000 is heat-treated at a predetermined temperature, or the adhesive ( The carrier metal layer 110 in which the build-up circuit layer 120 is formed by dissolving 200 is separated from the core member 1000.

Thereafter, as shown in FIG. 4I, the dry film 800 having a predetermined circuit pattern for forming the cavity 130 in which the semiconductor device 140 is to be built is formed on the other side of the carrier metal layer 110. Cover it.

After coating the dry film as described above, as shown in FIG. 4J, a cavity 130 in which a predetermined semiconductor device 140 is embedded is formed by performing exposure, development, and etching processes on the dry plume 800. To form.

Thereafter, as shown in FIG. 4K, the semiconductor device 140, which is die-attached by the circuit layer 120 and the bump junction, is embedded in the cavity 130, and then the cavity 130 is formed of resin 150. By molding using a), the semiconductor package substrate 100 on which a thin coreless circuit layer 120 is formed by a build-up method is finally completed.

As described above, according to the semiconductor package substrate and the manufacturing method thereof according to the present invention, it is possible to remove the existing thick core portion and to replace the role of the carrier metal layer, and to be active and inside the carrier metal layer. By embedding passive devices, the system package can be realized by reducing the thickness, versatility, and system integration of semiconductor package substrates, and increasing the mechanical strength of the substrate. to provide.

In addition, the present invention provides a design freedom by eliminating the existing thick core portion and applying the existing build-up method, more specifically, semi-additive method, to all layers. It also provides the effect of increasing the density of the circuit and also.

In addition, according to the present invention, an active chip is embedded in a cavity formed in a carrier metal layer and die-attached to a circuit layer, thereby shortening a connection length with the circuit layer, thereby increasing signal processing time and increasing impedance matching. This provides the effect that it is possible to respond to high frequency signals of 20GHz or more.

In addition, the present invention serves to solve the heat generation problem in the high frequency region by serving as a heat-sink for the active element and the passive element embedded in the cavity formed in the carrier metal layer.

In addition, the present invention provides an effect of improving productivity by having a core layer having a structure in which a pair of carrier metal layers face each other.

Herein, the present invention described above has been described with reference to preferred embodiments, but those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that this can be changed.

FIG. 1 (FIGS. 1A to 1O) is a process diagram showing a manufacturing process of a semiconductor package substrate by a conventional build-up method.

2 is a cross-sectional view of a semiconductor package substrate according to the present invention;

3 is a cross-sectional view of a core member providing a carrier metal layer according to the present invention.

4 (FIG. 4A to FIG. 4K) are process diagrams illustrating a manufacturing process of a semiconductor package substrate according to the present invention. FIG.

Explanation of symbols on the main parts of the drawings

100: semiconductor package

110: carrier metal layer

120 coreless circuit layer

130: cavity

140: semiconductor device

150: molding member

200: adhesive material

300: dry film

400: circuit pattern

500: insulation layer

600: via hole

700: conductive paste

800: dry film

1000: core member

Claims (10)

A carrier metal layer; A circuit layer formed on one side of the carrier metal layer by a buildup method; A cavity formed by an etching process on the other side of the carrier metal layer, and including a semiconductor element die-attached to the circuit layer; And A molding part for molding the cavity having the semiconductor chip embedded therein into a predetermined insulating member; A semiconductor package substrate comprising a. The method of claim 1, And a metal barrier layer between the carrier metal layer and the circuit layer to protect the circuit layer from an etching process for forming the cavity. The method of claim 1, The circuit layer is a semiconductor package substrate, characterized in that the thin coreless (coreless) circuit layer built up using the carrier metal layer as a core layer. The method of claim 1, And the cavity serves as a heat sink for dissipating heat to a semiconductor device die-attached to the circuit layer. The method of claim 1, The insulating member constituting the molding portion is a semiconductor package substrate, characterized in that the resin. A first step of providing a core layer having a structure in which a pair of carrier buried layers oppose each other through an adhesive material; A second step of forming a circuit layer by a build-up method on one side of the carrier buried layer constituting the core layer; A third step of dissolving the adhesive material of the core layer by a predetermined method to separate the carrier buried layer in which the circuit layer is formed; A fourth step of forming a cavity for embedding the semiconductor device by an etching process on the other side of the separated carrier buried layer; A fifth step of die attaching the semiconductor element embedded in the cavity to the circuit layer by bump bonding; And A sixth step of molding the cavity having the semiconductor device embedded therein using a predetermined insulating member; Method of manufacturing a semiconductor package substrate comprising a. The method of claim 6, A seventh step of forming a metal barrier layer between the carrier metal layer and the circuit layer to prevent damage of the circuit layer from an etching process for forming the cavity The semiconductor package substrate manufacturing method characterized in that it further comprises. The method of claim 6, wherein the second step, Step 2-1 of coating a dry film having a circuit pattern formed on one side of the carrier metal layer; Performing a exposure and development on the coated dry film to form a predetermined circuit pattern on the carrier buried layer; Laminating the insulating layer on the carrier buried layer in which the circuit pattern is formed; A second to fourth step of forming via hole regions by performing via hole processing on the laminated insulating layer by a predetermined method; Filling the via hole region with a conductive paste to perform via-interconnection with a circuit pattern formed in the carrier buried layer; And A second to sixth step of forming a multilayer circuit layer by a build-up method using a semi-additive process on one side of the carrier buried layer Method of manufacturing a semiconductor package substrate comprising a. The method of claim 8, wherein the step 2-4, And forming the via hole region by laser machining, CNC drill and template imprint of the insulating layer. The method of claim 6, wherein the third step, And heat-treating at a predetermined temperature or dissolving the adhesive using a solvent to separate the carrier buried layer from the core layer.