KR100509471B1 - Improved PN Code Generator - Google Patents

Abstract

The present invention relates to an improved PN code generator.

The generator is a PN generator for generating an I PN code and a Q PN code from a long channel, an I channel short code and a Q channel short code of a plurality of channels, and converts each of the long code and the short code into a parallel code by a predetermined bit. A plurality of serial-to-parallel converters for outputting the conversion results in parallel; A plurality of memories for storing the parallel codes converted by the plurality of serial-to-parallel converters; A write address generator for generating a code corresponding to a current symbol time as a write address; A read address generator configured to generate a value corresponding to a difference between a current symbol time and a symbol offset as a read address; A memory selector for selecting a memory to be written and a memory to be read according to the decoded value of the write address, the write address and the read address; And a PN code selector for generating an I PN code and a Q PN code by combining parallel codes read from the plurality of memories by a channel selection signal.

According to the present invention, since the setting of the PN offset is easy, not only the performance of the searcher is improved but also the coupling operation of the fingers is easy. In addition, it is easy to process a large number of rakes to maximize the efficiency of the parallel structure in a modem that accommodates multiple channels.

Description

Improved PEN Code Generator

The present invention relates to Code Division Multiple Access (CDMA), and more particularly, to a PNudo code generator (PN) for use in a CDMA transmitter and receiver.

The CDMA method introduces spread spectrum technology, which was originally used for military use, in civilian mobile communication. It can dramatically increase the capacity and is wider than the existing analog method, resulting in fewer cells, simpler frequency planning, It has the advantage of being suitable for large cities because it is excellent for data communication.

On the other hand, PN code is a kind of cyclic code (Cyclic Code) is defined as a series of coded 1 and 0 having a certain autocorrelation characteristics and a period artificially generated by binary code. The PN code can be easily configured using multiple flip-flop shift registers and a mod-2 adder. The PN code is generated in the PN code generator, and signals are distinguished by different offsets.

Such a PN generator is essential in the CDMA scheme for spread spectrum. In addition, the offset is essential for identifying the base station and finding the rake receiver when configuring the rake receiver, and also needs to change the offset from time to time to acquire and maintain synchronization.

1 is a block diagram of a conventional PN generator.

The PN generator shown in FIG. 1 includes a long code generator 10, a short code I generator 2, a short code Q generator 14, and first and second EXORs 16 and 18.

That is, the conventional PN generator is largely composed of the long code generator 10 and the short code generators 12 and 14.

Long code generation polynomial P (X) is

P (X) = X ⁴² + X ³⁵ + X ³³ + X ³¹ + X ²⁷ + X ²⁶ + X ²⁵ + X ²² + X ²¹ + X ¹⁹ + X ¹⁸ + X ¹⁷ + X ¹⁶ + X ¹⁰ + X ⁷ + X ⁵ + X ³ + X ² + X + 1

The occurrence period of the long code is 2 ^42-1 . Thus, ^242-1 within the bit has the value one random meeting of ²⁴² of such a random value - By one unit is cyclic.

Short code generation polynomials Pi (X) (Short code I generation polynomial) and Pq (X) (Short code Q generation polynomial) are as follows.

Pi (X) = X ¹⁵ + X ¹³ + X ⁹ + X ⁸ + X ⁷ + X ⁵ + 1

Pq (X) = X ¹⁵ + X ¹² + X ¹¹ + X ¹⁰ + X ⁶ + X ⁵ + X ⁴ + X ³ + 1

The occurrence period of the short code is 2 ¹⁵ . Therefore, although 2 ¹⁵ has a random bit value, it is periodic for every 2 ¹⁵ units that are a collection of such random values.

The long code generated by the long code generator 10 and the short code I generated by the short code generator 12 are exclusively ORed in the first EXOR 16 to generate an I PN code.

The long code generated by the long code generator 10 and the short code Q generated by the short code Q generator 14 are exclusively ORed in the second EXOR 18 to generate a Q PN code.

The long code generator 10 and the short code generators 12 and 14 generate PN codes having respective periods in bit sequences each time a chip clock is generated.

The conventional PN code generator shown in FIG. 1 is configured to be initialized every two seconds. To obtain a PN code having an offset, the PN generator is initialized at a predetermined time (target offset) by an additional reference timer to obtain a PN code. .

Therefore, the PN code cannot be obtained immediately according to the offset, and the offset adjustment by the initialization value in the polynomial has to store the state value for every period, which causes a problem in that the burden of hardware or software is very large. In this case, the performance of the searcher (the highest power signal stage detecting means among the transmitted signals) and the finger (mechanism for modulating each of the signal stages detected by the searcher) are also degraded.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved PN code generator for improving the performance of a searcher and a finger by varying an offset of a PN code within a plurality of symbol intervals to solve the above problems. It is.

In order to achieve the above object,

A PN generator for generating an I PN code and a Q PN code from a long channel, an I channel short code, and a Q channel short code of a plurality of channels, wherein the long code and the short code are converted into parallel codes by predetermined bits, respectively, A plurality of serial-to-parallel converters for outputting the conversion results in parallel; A plurality of memories for storing the parallel codes converted by the plurality of serial-to-parallel converters; A write address generator for generating a code corresponding to a current symbol time as a write address; A read address generator configured to generate a value corresponding to a difference between a current symbol time and a symbol offset as a read address; A memory selector for selecting a memory to be written and a memory to be read according to the decoded value of the write address, the write address and the read address; An improved PN code generator is provided that includes a PN code selector for generating an I PN code and a Q PN code by combining parallel codes read from the plurality of memories by a channel selection signal.

The PN code selector may include: a selector configured to select and output one channel code from a plurality of long codes read from the memory by a channel select signal; A first logic gate for performing a logic operation on the long code of any one channel selected by the selector and the I channel short code read from the memory; And a second logic gate for performing a logic operation on the long code of any one channel selected by the selector and the Q channel short code read from the memory.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of one embodiment of an improved PN code generator in accordance with the present invention.

The PN code generator shown in FIG. 2 includes the Long Code 0-3 generator 202-208, the Short Code I and Q generators 210 and 212, the first through sixth serial-to-parallel converters 214-224, and the first through The sixth memory 226-236, the GPS timer 238, the write address generator 240, the read address generator 242, the decoder 243, the memory selector 244, and the PN code selector 246. Include.

The PN code generator shown in FIG. 2 is an example of four channels.

The Long Code 0-3 generators 202-208 generate the long codes of the 0-3 channels in sequential bits (in series). The short code I generator 210 generates the short codes of the I channel in sequential bits (serially). The short code Q generator 212 generates the short codes of the Q channel in sequential bits (in series).

The first to sixth serial-to-parallel converters 214 to 224 convert the code of each channel into four bits in parallel to generate and output 24-bit parallel code data.

The GPS timer 238 operates as a timer indicating a time up to two seconds by the chip clock and the synchronous reference time signal to generate a reference value for the generation of write and read addressers. The chip clock is, for example, 39.3216MHZ, which is 32 times 1.21.2MHZ.

The write address generator 240 and the read address generator 242 generate an address according to the current time value from the GPS timer 238. That is, the write address generator 240 generates the time value (current symbol time) of the GPS timer 238 as the write address. The read address generator 242 generates a value obtained by subtracting the symbol offset from the time value of the GPS timer 238 as the read address.

The decoder 243 decodes the most significant 3 bits of the addresses generated by the write address generator 240 to generate a memory selection signal (first memory selection signal-sixth memory selection signal).

The memory selector 244 selects one of six memories in the write mode based on the memory select signal generated by the decoder and the write and read addresses generated by the write address generator 240 and the read address generator 242. And set one of the remaining five memories to read mode.

The memory set in the write mode by the memory selector 244 among the first through sixth memories 226 through 236 corresponds to the current time of the parallel code data converted by the first through sixth parallel converters 214 through 224. Writes parallel code data.

Meanwhile, the memory set in the read mode by the memory selector 244 reads and outputs parallel code data corresponding to an address according to an offset among the parallel code data converted by the first through sixth parallel converters 214-224. Done. The memory that is not set to the write mode or the read mode does not operate at all, but may be set to the write mode or the read mode next time according to the GPS timer 238 and the offset.

3 is a diagram illustrating a memory format of each of the first to sixth memories 226 to 236.

In the memory format shown in Fig. 3, the I and Q codes and four long codes of four channels each have 24 bits for writing or reading a total of 24 bits. 0-1 in the vertical direction indicates a part of the memory address (less than 2 is omitted for convenience), and 0-7 in the horizontal direction indicates some of the writing order from the oldest (0) to the most recent (7) order (8). The following is omitted for convenience).

The PN code selector 246 combines the four channels long code, the I channel and the Q channel short code from the values read from the first to sixth memories 226 to 236 to generate an I PN code and a Q PN code.

4 is a detailed block diagram of the PN code selector 246.

The PN code selector shown in FIG. 4 represents MUX 246a, first EXOR 246b, and second EXOR 246c.

The long code 16 bits of four channels among the 24 bits read from the first to sixth memories 226 to 236 are inputted to the MUX 246a, and are inputted by the channel selection signal (the channel selection signal assigned to the current rake time). Four bits of either channel are output.

Four bits of the I channel and Q channel short code are input to the first EXOR 246b and the second EXOR 246c, respectively.

The first EXOR 246b outputs an I PN code by performing an exclusive OR on the I channel short code 4 bits and any one channel code 4 bits output from the MUX 246a.

The second EXOR 246c outputs the Q PN code by performing exclusive OR on the Q channel short code 4 bits and any one channel code 4 bits output from the MUX 246a.

The present invention is not limited to the above-described embodiment, and of course, modifications may be made by those skilled in the art within the spirit of the present invention. For example, in the exemplary embodiment of the present invention, the case of the long code of the four channels has been described as an example, but the case of the long code of the other channel is naturally applied. In the case where six memories are used, the number of memories can be added or subtracted. In addition, although the EXOR gate is used to generate the PN code in the PN code selector, other logic gates may be used.

According to the present invention, since the setting of the PN offset is easy, not only the performance of the searcher is improved but also the coupling operation of the fingers is easy. In addition, it is easy to process a large number of rakes to maximize the efficiency of the parallel structure in a modem that accommodates multiple channels.

1 is a block diagram of a conventional PN generator.

2 is a block diagram of one embodiment of an improved PN code generator in accordance with the present invention.

3 is a diagram illustrating a memory format of each of the first to sixth memories 226 to 236.

4 is a detailed block diagram of the PN code selector 246.

Claims (3)

In the PN generator for generating the I PN code and the Q PN code from the multi-channel long code, I channel short code and Q channel short code, A plurality of serial-to-parallel converters for converting each of the long code and the short code into predetermined parallel bits and outputting the conversion result in parallel; A plurality of memories for storing the parallel codes converted by the plurality of serial-to-parallel converters; A write address generator for generating a code corresponding to a current symbol time as a write address; A read address generator configured to generate a value corresponding to a difference between a current symbol time and a symbol offset as a read address; A memory selector for selecting a memory to be written and a memory to be read according to the decoded value of the write address, the write address and the read address; And And a PN code selector for generating an I PN code and a Q PN code by combining the parallel codes read out from the plurality of memories by a channel selection signal. The method of claim 1, wherein the PN code selector A selector for selecting and outputting any one channel code from a plurality of long codes read from the memory by a channel selection signal; A first logic gate for performing a logic operation on the long code of any one channel selected by the selector and the I channel short code read from the memory; And And a second logic gate for logically outputting the long code of any one channel selected by the selector and the Q channel short code read out from the memory. The method of claim 2, wherein the first and second logic gates are An improved PN code generator characterized by each being an EXOR gate.