KR100505446B1 - Ferroelectric random access memory and method for fabricating the same - Google Patents

Abstract

The present invention relates to a capacitor of a ferroelectric memory device and a method of manufacturing the same. According to the present invention, the cell-to-cell spacing is minimized and can be adjusted as necessary. The cell area can be reduced while ensuring reliability, contributing to the development of highly integrated ferroelectric memory.

Description

Ferroelectric memory device and method for manufacturing the same {Ferroelectric random access memory and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric random access memory (FeRAM) and a method of manufacturing the same, and more particularly, to minimize integration of capacitor lower electrodes between adjacent cells so as to have a minimum spacing while maintaining high integration and process stability. The present invention relates to a ferroelectric memory device and a method of manufacturing the same.

In semiconductor memory devices, FeRAM uses a ferroelectric as a capacitor to overcome the limitations of refreshing in DRAM (Dynamic Random Access Memory), and to store information even when the power is cut off as a nonvolatile memory. Its applications range from smart cards for information storage to memory in mobile devices.

A structure of a memory capacitor according to the related art will be described with reference to FIGS. 1A and 1B as follows.

In general, the ferroelectric capacitor is formed on the insulating film 11 and the contact plug 12 as illustrated in FIG. 1A and has a lower electrode 13 having a trapezoidal cross-sectional shape and a ferroelectric formed on the lower electrode 1 ( 1) and the upper electrode 16 formed on the ferroelectric.

In addition, the ferroelectric capacitor is provided in each memory cell of the ferroelectric memory device, and the lower electrodes 13 of the first and second cells adjacent to each other should be electrically separated from each other. To this end, a separation insulating layer 14 is formed between each lower electrode 13 of the first cell and the second cell.

Meanwhile, in order to develop a highly integrated ferroelectric memory, the integration of a front end of process (FEOL) as well as the development of a high density memory such as DRAM has already been developed to a sufficient degree, but a post process including a ferroelectric capacitor manufacturing process (Back Integration in the End of Process (BEOL) holds the key to high integration of ferroelectric memory. Since the chemical vapor deposition of ferroelectric films has not been fully developed, it is difficult to apply three-dimensional capacitors for at least a while. It is a trend.

In this case, the area of the capacitor is determined by the size of the upper and lower electrodes, and in the case of the upper electrode, since two adjacent cells may share one upper electrode (Share Cell Plate), the cell area of the ferroelectric capacitor, and thus the ferroelectric memory. The size of the bottom electrode of the ferroelectric capacitor and the distance between each bottom electrode are determined.

However, in a conventional ferroelectric memory device, a noble metal is generally used as a lower electrode, and when etching a noble metal, the noble metal is etched by physical collision because the noble metal does not react chemically with the etching gases and must be etched by physical collision. In consideration of being sloped etched, a gap C is provided between the lower electrodes as shown in FIG. In FIG. 1B, the size of the lower electrode actually serving as a capacitor in contact with the ferroelectric is a reference numeral 'A', and is an actual layout of a mask (reticle) to be used for etching the lower electrode. Reference numeral 'B' is the area increased by the inclined etching.

As a result, the prior art has to consider a separate interval (reference number 'C') between the lower electrodes of adjacent cells in consideration of the area that is increased by the inclined etching, the degree of integration is reduced.

At present, in consideration of this problem, that is, an inclination etching, a method of reducing the size of the lower electrode or reducing the thickness of the lower electrode is attempted to reduce the cell area. This is because reducing the thickness of the lower electrode minimizes the area enlarged by the inclined etching.

However, the method of reducing the size of the lower electrode is limited because the amount of charge that can be stored in the capacitor decreases accordingly, and the method of reducing the thickness of the lower electrode has a limitation because the characteristics of the lower electrode are degraded.

The present invention has been proposed to solve the problems of the prior art as described above, by minimizing the gap between the lower electrodes while stably forming the lower electrode without short circuit between the lower electrodes without considering the size of the lower electrode is inclined etching. An object of the present invention is to provide a ferroelectric memory device capable of achieving high integration and a method of manufacturing the same.

A ferroelectric memory device manufacturing method of the present invention for achieving the above technical problem, in the ferroelectric memory device manufacturing method for forming a plurality of island-shaped bottom electrode arranged in a matrix in the row and column direction, the first on the substrate Depositing a conductive layer; Forming a first sub-electrode corresponding to a portion of the lower electrodes of the plurality of lower electrodes by using a photomask having a plurality of light blocking patterns arranged in a mosaic shape; Depositing an insulating film on an entire substrate including the patterned first conductive layer; Dry etching the insulating film without a mask to form insulating film spacers on sidewalls of the patterned first conductive layer; Forming a second conductive layer over the entire substrate including the patterned first conductive layer and the insulating layer spacer; And chemically polishing the second conductive layer to form a second lower electrode corresponding to a portion of the lower electrodes of the plurality of lower electrodes.

In addition, the ferroelectric memory device of the present invention comprises: a lower electrode of a first cell patterned in an island shape on a substrate and having a shape in which a side of a circumferential edge gradually widens from a lower side thereof; A second lower electrode of the second cell which is separated from the lower electrode of the first cell in a lateral direction and formed in an island shape on the substrate and whose cross section around the edge is gradually narrowed from the lower side; A separation insulating layer formed in a separation region between the lower electrode of the first cell and the lower electrode of the second cell; Ferroelectrics formed on each of the lower electrodes of the first and second cells and the isolation insulating film; It characterized in that it comprises an upper electrode formed on the ferroelectric.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 2a is a view showing the structure of the ferroelectric capacitor according to the present invention, Figure 2b is a view showing the layout of the lower electrode according to the present invention.

2A shows each ferroelectric capacitor for four cells, and FIG. 2B shows only the bottom electrode corresponding to the three cells.

2A and 2B, the lower electrodes 23a and 23c of the first and third cells are patterned in an island shape on the substrate, and the sides around the edges are gradually widened from the lower side.

The lower electrode 23b of the second cell between the first cell and the third cell is separated from the lower electrode of the adjacent cell in the lateral direction and formed in an island shape, and the cross-section around the edge is gradually narrowed from the lower side. The same applies to the lower electrode 23d of the fourth cell.

In addition, the lower electrodes of the adjacent cells are separated in the lateral direction by the isolation insulating layer 24.

A ferroelectric 25 is formed on the lower electrode and the isolation insulating film of each cell, and an upper electrode 26 which is a plate electrode is formed thereon.

The lower electrodes are formed on the contact plug 22 penetrating the insulating film 21 and the junction of the transistor to serve as a charge storage electrode.

The lower electrode and / or the upper electrode is formed using Pt, Ir, IrOx, Ru, Re, Rh, or one of these complex structures, and these precious metal-based electrodes do not chemically react with the etching gas and are physically etched. Because it must be etched (sloped etch), the etch slope angle (etch slope angle) of the lower electrode is greater than 45 ° and less than 90 °.

As the ferroelectric, one of SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT), (Bi, La) 4 Ti 3 O 12 (hereinafter referred to as BLT) and (Pb, Zr) TiO 3 (hereinafter referred to as PZT) can be used. Dielectric has the characteristic that charge is induced by applied voltage, and especially ferroelectric material using dipole polarization. Ferroelectric materials use polarization to distinguish between '0' and '1' based on the amount of charge written, and use them in memory. Preferably, the SBT, BLT, PZT is used by changing the composition or by adding impurities. In addition, the ferroelectric material has a perovskite structure or a layered perovskite structure.

The isolation insulating film 24 is formed of a low-k dielectric in order to prevent disturbance between cells, and preferably has a thickness of 3 to 1000 인접 between adjacent lower electrodes.

Referring to FIG. 2B, the size of the lower electrode serving as a capacitor in contact with the ferroelectric is a portion 'A', which is an actual layout of a mask (reticle) to be used for etching the lower electrode. The structure of the present invention does not have to consider the area increase due to the inclined etching unlike the conventional art, and only needs to consider the interval of the reference numeral 'D'. As will be described later in the manufacturing process, the interval between the reference numeral 'D' becomes the deposition thickness of the isolation insulating film 24.

As a result, the prior art has to consider a separate spacing between the lower electrodes of adjacent cells in consideration of the area increased by the inclined etching (reference numeral 'C' in FIG. 1B), so that the degree of integration decreases, but the present invention is adjacent to each other. Since the cross-sections of the lower electrodes have different point symmetric shapes, it is not necessary to consider the area increase due to the inclined etching.

Therefore, it is not necessary to worry about the short circuit of adjacent lower electrodes, and forming lower electrodes of the same size can lay out a plurality of lower electrodes in a relatively small area.

Next, a preferred embodiment of the method of manufacturing the ferroelectric memory device having the above-described structure will be described with reference to FIGS. 3A to 3D and FIGS. 4A and 4B.

The lower electrodes of the above structure are formed in plural as island shapes arranged in a matrix in rows and columns in plan view.

First, as shown in FIG. 3A, a first conductive layer is deposited on a substrate (a state in which an insulating film and a plug are formed), and a photomask having a plurality of light blocking patterns arranged in a mosaic shape (see FIG. 4A) is used. Lower electrodes 23a and 23c of the third cell are formed. The first conductive layer is inclined during etching with the noble metal.

Next, an insulating film 24 is deposited on the entire substrate including the patterned lower electrodes 23a and 23c.

Subsequently, referring to FIG. 3B, the insulating film 24 is completely dry-etched without a mask to form a spacer on the sidewalls of the patterned lower electrodes 23a and 23c, and the insulating film spacer becomes a separation insulating film 24. .

Subsequently, a second conductive layer 230 is formed on the entire substrate including the patterned lower electrode and the insulating layer spacer as shown in FIG. 3C.

Subsequently, as illustrated in FIG. 3D, the second conductive layer 230 is chemical mechanical polished (CMP) to form lower electrodes 23b and 23d of the second and fourth cells.

When the manufacturing method is applied, even when the lower electrode is inclinedly etched during the lower electrode etching process, the isolation insulating layer is deposited, the entire surface is etched to form a spacer, and then the lower electrode of the adjacent cell is formed by chemical mechanical polishing. There is no need to worry about the short circuit of the lower electrode since the isolation insulating film is always present between the lower electrodes of. In addition, high integration is possible without reducing the area and thickness of the lower electrode.

On the other hand, the isolation insulating film 24 is preferably deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to sufficiently follow the topology of the lower electrode.

Further, the second conductive layer is deposited thick enough to cover the lower electrodes 23a and 23c of the first conductive layer, and then chemical mechanical polishing (CMP) until the lower electrode of the second conductive layer is exposed. Form.

FIG. 4B is a plan view of another mask (reticle) used to etch the first conductive layer. When etching the first conductive layer, the rounding phenomenon is a phenomenon in which corners are etched when the size of the pattern decreases. This is to overcome the problem that the area acting as a capacitor is smaller than the area drawn as a result of the rounding.

Referring again to FIG. 4A, a photomask (reticle) for forming a lower electrode may include a plurality of light blocking patterns arranged in a mosaic shape as a pattern corresponding to a portion of the conductive patterns among a plurality of conductive patterns arranged in a matrix in a row column direction. 42) and a plurality of transmission patterns 46 arranged in a mosaic shape as a pattern corresponding to the conductive patterns of the remaining portions of the plurality of conductive patterns.

Referring to the mask illustrated in FIG. 4B, in addition to the light shielding pattern 42 and the transmission pattern 46, the plurality of light shielding patterns may be adjacent to each other at edges to compensate for the area reduced by the rounding effect during the etching of the conductive pattern. The pattern portion 44 further extended to the corner portion of the conductive pattern to be further included.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those of ordinary knowledge.

According to the present invention as described above, even when the lower electrode is etched inclined during the etching of the lower electrode, the isolation insulating film is present as the thickness deposited between the adjacent lower electrodes and has an inclination opposite to the point symmetry with each other, thereby increasing the cell area. It becomes insignificant.

In addition, the cell-to-cell spacing ensures a minimum cell-to-cell spacing, and can be adjusted as necessary, so that the cell area can be reduced while securing process stability and device reliability in manufacturing memory devices. Will be.

The present invention can contribute to the development of highly integrated ferroelectric memory devices of more than 128M.

1A is a view showing the structure of a ferroelectric capacitor manufactured according to the prior art.

1B is a view showing a layout of a lower electrode having a space between the lower electrodes in consideration of an inclined etching.

2A is a view showing the structure of a ferroelectric capacitor according to the present invention.

Figure 2b is a view showing the layout of the lower electrode according to the present invention.

3A to 3D are diagrams illustrating each step of a method of forming a lower electrode according to an embodiment of the present invention.

4A illustrates a mosaic-shaped lower electrode mask (reticle) for forming the lower electrode according to the present invention.

4B is a layout of a lower electrode mask according to another embodiment of the present invention.

Claims (8)

A lower electrode of the first cell patterned in an island shape on a substrate and having a shape in which a side of the edge is gradually widened from a lower side thereof; A second lower electrode of the second cell which is separated from the lower electrode of the first cell in a lateral direction and formed in an island shape on the substrate and whose cross section around the edge is gradually narrowed from the lower side; A separation insulating layer formed in a separation region between the lower electrode of the first cell and the lower electrode of the second cell; Ferroelectrics formed on each of the lower electrodes of the first and second cells and the isolation insulating film; A ferroelectric memory device comprising an upper electrode formed on the ferroelectric. The method of claim 1, The upper and lower electrodes of the ferroelectric film is any one selected from the group of Pt, Ir, IrOx, Ru, Re, Rh or a composite structure thereof. The method of claim 1, The lower electrode of the first cell is a ferroelectric memory device, characterized in that the inclination of the side around the edge gradually widens from the lower side is greater than 45 ° and less than 90 °. . The method of claim 1, The isolation insulating film includes a low-k dielectric. The method of claim 1, And the isolation insulating layer has a thickness of 3 to 1000 Å between each lower electrode of the first and second cells. delete A mask for forming a plurality of island-shaped capacitor lower electrodes arranged in a matrix in rows and columns, A plurality of light blocking patterns arranged in a mosaic shape as a pattern corresponding to a portion of the lower electrodes of the plurality of lower electrodes; And A plurality of transmission patterns arranged in a mosaic shape as a pattern corresponding to the lower electrodes of the remaining portions of the plurality of lower electrodes, The plurality of light blocking patterns have a quadrangular shape in plan view, and the plurality of light blocking patterns extend from corners to corners of neighboring light blocking patterns in order to compensate for the area reduced by the rounding effect during the lower electrode etching. The mask further comprises a wealth. A method of manufacturing a ferroelectric memory device for forming a plurality of island-shaped lower electrodes arranged in rows and columns in matrix, Depositing a first conductive layer on the substrate; Forming a first lower electrode corresponding to a part of the lower electrodes of the plurality of lower electrodes by using a photomask having a plurality of light blocking patterns arranged in a mosaic shape; Depositing an insulating film on an entire substrate including the patterned first conductive layer; Dry etching the insulating film without a mask to form insulating film spacers on sidewalls of the patterned first conductive layer; Forming a second conductive layer over the entire substrate including the patterned first conductive layer and the insulating layer spacer; Chemical mechanical polishing the second conductive layer to form a second lower electrode corresponding to a portion of the lower electrodes of the plurality of lower electrodes Ferroelectric memory device manufacturing method comprising a.