KR100474605B1 - Via first dual damascene process for copper metallization - Google Patents

Abstract

The interconnect pattern is formed on the top surface of the silicon wafer where both the vias and trenches of the pattern are filled with copper. The process of filling vias and trenches includes using a silicon nitride film for etching prevention and filling the vias with an antireflective coating.

Description

Via first dual damascene process for copper metal wiring {VIA FIRST DUAL DAMASCENE PROCESS FOR COPPER METALLIZATION}

FIELD OF THE INVENTION The present invention relates to integrated circuits using copper to interconnect discrete circuit components as part of the back-end-of-the line of a semiconductor silicon wafer, particularly prior to trenching in dual damascene processes. When the vias are etched, it relates to the modification of wafer processing needed to protect copper during chemical etching.

Due to the demand for faster integrated circuits, technicians are trying to increase the packing density by miniaturizing the solid state components on the chip. Due to this demand, interconnect metallurgy is moving from aluminum based metals to copper with lower resistivity. High conductivity and low cost copper are well suited for interconnecting circuit components. In addition, copper has relatively improved reliability to electromigration failure than Al or Al-Cu.

Copper has desirable electrical properties, but it tends to oxidize or corrode when contacted with commonly used processing chemicals. Therefore, if copper is exposed during the process, ie not covered, the process associated with copper metal wiring should not be affected by these environments. Back-end-of-the line metallization of Al and Al-Cu does not tend to corrode due to the protective oxides covering the metal faces in these materials.

Copper is a very promising material as a line back end metal when single or dual damascene processes are used. The damascene process utilizes a series of trenches formed in the insulating layer. After overfilling the trench with copper, the overfill is removed by a chemical mechanical polishing (CMP) process. The trench is separated from the via. That is, the trench is an extended groove, which generally extends parallel to the top surface of the silicon chip, and is patterned to interconnect circuits on the same level of the line back end process, while vias generally extend perpendicular to the face. Holes, which are patterned to connect metal lines from layer to layer.

The technique uses a "trench first" approach. Initially, a "via first" approach was used because of the need for a relatively thick multilayer silicon nitride film. Silicon nitride, which protects copper during the process, must subsequently remain in many active regions. However, these silicon nitride layers significantly increased the dielectric properties of the stack, worsening the performance of the circuit. If the silicon nitride film is thin, the film is weakened during the via etching. Via etch is also etched into the oxide defining the trench. If a ground rule of 0.25 [mu] m is adequate, even a small change in the line definition can cause fatal reliability problems.

Since copper is known to be quite sensitive to its environment, photoresist and oxidizing chemicals, including sulfur in general, should not be in contact with the copper face during the process. In the present invention, silicon nitride is used as a protective layer for protecting copper and for etching prevention.

However, the "trench first" approach is also limited. These limitations are related to the photolithographic process of the wafer. Problems arise when the trench shape causes a difference in photoresist thickness. The change in thickness occurs, for example, in the wide trenches (wide lines) or very dense trenches (narrow lines) required in DRAM, resulting in print distortion of the via image.

The present invention provides a protective layer of silicon nitride on copper, using a novel approach that does not damage silicon nitride during etching vias and trenches simultaneously.

1 through 6 illustrate a portion of a semiconductor wafer in successive steps of a process in accordance with an exemplary embodiment of the present invention to provide vias and trenches filled with metal as part of an interconnection pattern of conductors of integrated circuits formed in the semiconductor wafer. Figure is a diagram.

The drawings are not necessarily to scale.

The present invention relates to the use of a preferred "via first" approach for forming vias (openings, holes) and trenches (grooves) of a passivation layer by using a dual damascene process.

In one embodiment, contact metallurry is deposited on a patterned glass layer (eg, boron phospho silicate galss (BPSG)) and the glass is planarized. Then, another insulating material, such as silicon oxide, is deposited on the glass layer and patterned to form a shallow via opening aligned with the contact. This via is filled with copper and the face is planarized by chemical and physical polishing. A thin silicon nitride layer is deposited on the planarized insulator face to serve as a barrier layer / etch prevention.

The SiO ₂ layer is deposited on the silicon nitride layer and patterned using conventional photolithographic techniques to form a via hole therein aligned with the previous via.

In the present invention, unlike the prior art, it is an anti-reflective coating material (ARC) that spins on a wafer. The coating of ARC fills the vias and covers the rest of the face with a thin layer of ARC. The ARC material is placed in place and the photoresist is spun and patterned onto the wafer to form the shape of the trench. The SiO ₂ layer with vias is etched again to form trenches. During the trench etch, the ARC material is etched etched but at a different rate than SiO ₂ . As a result of the different etch rates, a plug of ARC material remains at the bottom of the via after the trench opening process is complete. This ARC plug prevents silicon nitride from deteriorating and protects the underlying copper since the etchant does not come into contact with copper.

To this end, one feature of the present invention is to protect the copper during the etching of the insulator layer using a silicon nitride film. In particular, this silicon nitride layer is thin so that the dielectric constant of the stack is kept to a minimum.

Another feature of the present invention is the use of an antireflective coating (ARC) to protect the silicon nitride layer. In general, in the manufacture of semiconductor chips, the phosphorous material is used not only as a protective layer but also provides photolithographic media in component definitions of silicon, insulators and metals.

A related feature of the invention includes the etching of an ARC layer that is not completely removed from the vias. After etching of the vias and trenches is complete, the ARC coating is removed as part of the photoresist strip process.

According to a first process aspect of the present invention, the present invention relates to copper on at least some vias and some trenches that penetrate an insulating layer arranged on a top surface of a semiconductor wafer on a semiconductor wafer comprising a device having a conductive contact region. It relates to a method of forming an interconnection pattern using. The method includes forming a first insulating layer on the device, forming a via penetrating from the top surface of the first insulating layer to communicate with the contact area of the device, filling the via with a conductor, first insulating Forming a second insulating layer on the layer, forming a via penetrating the second insulating layer to communicate with the via filled with the conductor of the first insulating layer, and filling the via passing through the second insulating layer with copper Forming a third insulating layer on the upper surface of the second insulating layer, forming a fourth insulating layer on the upper surface of the third insulating layer, the fourth insulating layer having an etching characteristic different from that of the third insulating layer, and the fourth Patterning / etching the insulating layer to form vias separated from the copper-filled vias passing through the second insulating layer by the third insulating layer but aligned with the vias passing through the second insulating layer, a fourth Antireflection on the top surface of the insulating layer Forming a layer and filling vias through the fourth insulating layer with an antireflective material, patterning the antireflective layer and the antireflective material to define a trench in the fourth insulating layer, removing the antireflective layer and a portion of the fourth insulating layer To form a trench in the fourth insulating layer, the trench communicating with the top surface of the via penetrating the fourth insulating layer, wherein the third insulating layer is formed between the antireflective material of the via penetrating through the fourth insulating layer and the second and fourth insulating layers. Removing a portion of the layer, filling the trench and via of the fourth insulating layer and the removed third insulating layer portion with copper.

According to a second process aspect of the invention, the invention relates to a copper fill in a trench on a semiconductor wafer, positioned in an insulating layer provided thereon and extending parallel to the top surface of the wafer, and a copper fill in a via extending the insulating layer vertically. It relates to a method of forming an interconnection pattern having a. The method includes forming a first insulating layer on the top surface of the semiconductor wafer, forming a trench on the top surface of the first insulating layer, and trenching from the bottom of the trench through the first insulating layer to communicate with the contact area of the device. Forming vias in communication with the substrate, overfilling the vias and trenches of the first insulating layer with a contact metal, and planarizing to form a first flat surface on the semiconductor wafer, on the first insulating layer filled with metal Forming a second insulating layer, forming vias and trenches in the second insulating layer and overfilling the vias and trenches with copper, forming a second flat surface on the second insulating layer filled with copper, Forming a silicon nitride layer on the planarized surface, forming a third insulating layer on the silicon nitride layer having an etching rate different from that of the silicon nitride layer, the silicon nitride film being etched Acting as a paper, patterning the third insulating layer to form vias aligned with the underlying copper, thereby forming a layer of antireflective material on the top surface of the third insulating layer filling the vias, the photo on the antireflective layer Depositing a resist layer to fill the via with an antireflective material, patterning the photoresist, etching the exposed portion of the via and the antireflective material and a portion of the third insulating layer to form a trench in the third insulating layer Removing the portion of the silicon nitride layer between the second and third insulating layers, the patterned photoresist, the antireflective material from the vias, and the respective trenches and vias below the third insulating layer In communication with one of the vias and trenches of the third insulating layer, overfilling the opening of the silicon nitride layer with copper, and patterning the face to off of the silicon nitride layer. The second step includes leaving the contact of the copper vias and trenches with the second insulating layer filled with the second insulating layer 3 of copper vias extending through.

These objects, features, and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

In the present specification, the back-end-of-the line process of the dual damascene process requires vias and trenches to be etched into a silica glass insulating layer or silicon oxide between different levels of the conductive interconnect pattern. do. For the "via first" approach, vias and trenches need to be present in place before copper is deposited. Filling vias and trenches in one deposition process can reduce the complexity of the process. The silicon nitride film for protecting the metal of the first level must be removed continuously so that metal to metal contact is made between the first level of the copper line and the first via.

As mentioned above, it is common practice to use a "trench first" approach. The adoption of a "via first" approach offers many advantages as long as copper remains protected during the process and its conductivity does not deteriorate.

FIG. 1 illustrates a portion of a silicon wafer 100 having an insulating (dielectric) layer 10 made of boron phospho silicate glass (BPSG). As shown, the wafer 100 has an insulated gate field effect transistor formed on its top surface 100a. The field effect transistor (device) includes diffusion regions 12a and 12c, a drain region, a source region, and a gate region 12b, and the gate region 12b is arranged on the upper surface 100a of the wafer 100 and the dielectric gate It is located centrally between the regions 12a and 12b on the layer 13. In general, dielectric layer 13 and gate region 12b are preferentially formed, and region 12b serves as a mask to allow regions 12a and 12c to self align with gate region 12b. Do it. A conventional photoprocess is performed to pattern the layer 10 and an etching process is performed to form vias (openings) through the layer 10 to expose the diffusion regions 12a, 12c and the gate region 12b. . In general, the trenches are etched into the top surface 10a of the layer 10. The vias and trenches of layer 10 are then overfilled with metals 16a, 16b, 16c, typically tungsten (W), to form flat surface 10a by chemical-physical polishing. In general, an insulating layer 18 made of SiO ₂ is deposited on the flat surface 10a. Using photoresist and etching on layer 18 to form vias and trenches overfilled with copper 22a, 22b, 22c to provide metal-to-metal contact with tungsten 16a, 16b, 16c, respectively. . The first damascene process is completed by planarizing the top surface 18a of layer 18 by chemical and physical polishing.

In Fig. 2, an insulating layer 24 made of 50 nm silicon nitride, which is usually formed by PECVD, is deposited on the surface 18a so as to serve as an etching barrier / cap layer, and an insulating layer usually made of SiO ₂ ( Shown is wafer 100 after 26 has been deposited on top 24a of silicon nitride layer 24, respectively. Thereafter, a photoresist (not shown) is spun into layer 26. After the photoresist is patterned, layer 26 is reactive ion etched to open vias 28a, 28b, 28c. Post etch treatment employed to remove the photoresist and a portion of the exposed layer 26 is stopped at the silicon nitride barrier layer 24. This process gives high precision selectivity to completely open vias 28a, 28b, 28c without generating a reactive ion etch (RIE) lag at the tip.

3, a relatively thin anti-reflexive coating 30 is spun onto the wafer 100 to cover the surface and fill the vias 28a, 28b, 28c of the layer 26. Is shown. It is important that vias 28a, 28b, 28c are filled to ensure no voids are present. In practice, however, the cross-section of the processed wafer shows that the ARC material fills the trenches 28a, 28b, 28c to approximately three quarters of their height.

For example, an ARC material of grade 1100A (first at 95 ° C. and then at 180 ° C.) is heated and non-selectively reactive ion etched from the surface of SiO ₂ 26 for 40 seconds with C ₄ F ₈ + O ₂ . The photoresist layer 32, typically of DUV 30 MCSIII / JSR 130/6250, is then spun and patterned on the wafer 100 to form openings 31a, 31b, 31c exposing a portion of the layer 30. An opening 31a wider than via 28a is positioned to communicate with it on via 28a. An opening 31b wider than via 28b is positioned to communicate with it on via 28b. An opening 31c wider than via 28c is positioned to communicate with it on via 28c.

Low selective reactive ion etch, which typically lasts for 40 seconds, is used to etch exposed portions of ARC layer 30 using a combination of C ₄ F ₈ , Ar and O ₂ , and then Expose a portion of layer 26 to be etched. As a result, trenches 36a, 36b, 36c in communication with the vias 28a, 28b, 28c are formed. 4 shows ARC plugs 30a, 30b, 30c remaining at the bottom of vias 28a, 28b, 28c after such etching. This is because ARC material is removed at a slower rate than SiO ₂ of layer 26. This prevents the environment of surrounding SiO ₂ etching from affecting the silicon nitride layer 24. 4 also shows that oxide layer 26 is etched to integrate trenches 36a, 36b, 36c and vias 28a, 28b, 28c, respectively.

When the ARC material 30 is in the vias, the etching of the oxide layer 26 is “fence” by adjusting the etching process to be compatible with the etching of SiO ₂ and ARC materials as well as SiO _2. Is achieved without the formation of. A fence is formed when the etchant removes material from the via at a different etch rate depending on its location. For example, it can be seen that when compared to ARC material at the ARC / oxide interface, it exhibits different etch rates for the ARC material in the center of the via.

The post etching process for 20-40 seconds removes remaining ARC material 30a, 30b, 30c from the vias 28a, 28b, 28c, respectively. The silicon nitride layer 24 is then selectively etched away using CHF ₃ + O ₂ for approximately 35 seconds. All trenches are wider than vias in communication with them, but need not extend beyond one side of a via.

Once the normal cleaning process is complete, the structure of FIG. 4 is already metal filled with copper.

5 shows the wafer 100 after via / trench openings 28a / 36a, 28b / 36b are overfilled with electroplated copper 40.

FIG. 6 shows the wafer 100 after the resulting top surface 42 is planarized by chemical-physical polishing to remove excess copper leaving the conductors 40a, 40b, 40c. 6 also shows the results of the final dual damascene process for this level of metallization.

The above-described embodiments are merely illustrative of the general principles of the invention, and of course, there can be various other embodiments without departing from the principles known to those skilled in the art. For example, the insulating layer may be a material other than silicon dioxide, and the metal for contacting the semiconductor device may be aluminum. Also, in some applications, some or all of the trenches do not need to be used with vias that fully extend the insulating layer. And the novel process of the present invention may begin in the trench portion of the first level of the conductor, and the metals 16a, 16b, 16c may be tungsten in the vias and copper in the trenches.

Claims (17)

Forming an interconnection pattern using copper on at least some vias and some trenches that penetrate an insulating layer arranged on the top surface of the semiconductor wafer, the semiconductor wafer 100 comprising a device having a conductive contact region In the method, Forming a first insulating layer 10 on the device, Forming vias 16a, 16b, 16c penetrating from the top surface 10a of the first insulating layer 10 to communicate with the contact region of the device, Filling the vias 16a, 16b, 16c with a conductor, Forming a second insulating layer 18 on the first insulating layer 10, Forming vias (22a, 22b, 22c) passing through the second insulating layer (18) to communicate with vias (16a, 16b, 16c) filled with a conductor of the first insulating layer (10); Filling the vias 22a, 22b, 22c penetrating the second insulating layer 18 with copper; Forming a third insulating layer 24 on the upper surface 18a of the second insulating layer 18, Forming a fourth insulating layer 26 having an etching characteristic different from that of the third insulating layer 24 on the upper surface 24a of the third insulating layer 24, The fourth insulating layer 26 is patterned / etched to separate the copper-filled vias 22a, 22b, 22c penetrating the second insulating layer 18 by the third insulating layer 24. Forming vias 28a, 28b, 28c but aligned with one another, Forming an antireflective layer 30 on the upper surface of the fourth insulating layer 26 and filling vias 28a, 28b, and 28c penetrating the fourth insulating layer 26 with an antireflective material, Patterning the antireflective layer 30 and the antireflective material to define a trench in the fourth insulating layer 26, A portion of the vias 28a, 28b and 28c penetrating the fourth insulating layer 26 through the fourth insulating layer 26 by removing a portion of the antireflective layer 30 and the fourth insulating layer 26. The trenches 31a, 31b, and 31c communicating with the upper surface are formed, and the antireflective layer 30 and a part of the fourth insulating layer 26 are removed by a first etching means to remove the fourth insulating layer 26. Leaving the plugs 30a, 30b, 30c of the antireflective layer 30 remaining at the bottom of the vias 28a, 28b, 28c, The second etching means uses a portion of the third insulating layer 24 between the plug of the fourth insulating layer 26 and the via of the second insulating layer 18 and the via of the fourth insulating layer 26. Removing by Filling trenches and vias of said fourth insulating layer and portions of said third insulating layer removed with copper. How to form an interconnect pattern. The method of claim 1, Vias 28a, 28b and 28c and trenches 30a, 30b and 30c of the fourth insulating layer 26 are overfilled with copper and chemical and physical polishing are employed to planarize the formed structure. How to form an interconnect pattern. The method according to claim 1 or 2, The first insulating layer 10 is made of BPSG, the second and fourth insulating layers 18 and 26 are made of silicon oxide, and the third insulating layer 24 is made of silicon nitride. How to form an interconnect pattern. The method according to claim 1 or 2, The conductor is tungsten How to form an interconnect pattern. The method according to claim 1 or 2, The conductor is aluminum How to form an interconnect pattern. The method according to claim 1 or 2, On the upper surface 10a of the first insulating layer 10, respectively communicating with vias 16a, 16b, 16c penetrating through the first insulating layer 10, forming a separate trench each filled with a conductor step, Overfilling the vias 16a, 16b, 16c and trenches of the first insulating layer 10 with conductors and planarizing them using chemical and physical polishing, Forming a separate trench on the top surface 18a of the second insulating layer 18, communicating with the vias 22a, 22b, 22c of the second insulating layer 18, respectively, filled with copper; Overfilling the vias 22a, 22b, 22c and trenches of the second insulating layer 18 with copper and planarizing them using chemical and physical polishing. How to form an interconnect pattern. The method according to claim 1 or 2, The antireflective layer 30 and the antireflective material have an etching rate different from that of the third insulating layer 24. How to form an interconnect pattern. The method of claim 3, wherein Silicon nitride of the third insulating layer 24 is deposited by plasma excited chemical vapor deposition How to form an interconnect pattern. delete delete delete delete delete delete delete delete delete