KR100451041B1 - Method for forming metal interconnection of semiconductor device to solve problems arising from step between cell area and peripheral circuit area of semiconductor device - Google Patents
Method for forming metal interconnection of semiconductor device to solve problems arising from step between cell area and peripheral circuit area of semiconductor device Download PDFInfo
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- KR100451041B1 KR100451041B1 KR1019970028509A KR19970028509A KR100451041B1 KR 100451041 B1 KR100451041 B1 KR 100451041B1 KR 1019970028509 A KR1019970028509 A KR 1019970028509A KR 19970028509 A KR19970028509 A KR 19970028509A KR 100451041 B1 KR100451041 B1 KR 100451041B1
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- semiconductor device
- peripheral circuit
- film
- exposure process
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000002184 metal Substances 0.000 title claims abstract description 22
- 230000002093 peripheral effect Effects 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로 특히, 주변 회로 영역과 셀 영역 간의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE
일반적으로 반도체 소자의 금속 배선은 소자간의 조합에 자유도를 주어, 고밀도의 디바이스를 형성 시키기 위한 중요한 방법이다. 소자의 금속 배선이 복잡해 지면서 새로운 불량 모드가 발생할 가능성이 크다. 특히, 소자의 수율이나 신뢰성에 문제가 되는 것이 단차에 의한 단선 및 단락이다.In general, metal wiring of a semiconductor device is an important method for forming a high-density device by giving freedom to the combination between the devices. As the metal wiring in the device becomes more complex, new failure modes are more likely to occur. In particular, disconnection and short circuit due to a step are problematic for yield and reliability of the device.
도 1은 종래 반도체 소자의 금속 배선 형성방법을 설명하기 위한 마스크의 평면도 및 소자의 단면도의 단면도이다. 도 1을 참조하면, 종래 반도체 소자의 셀영역(2)과 주변 회로영역(1) 간의 단차(3)로 인하여 노광시 최적의 초점을 얻기 어렵고, 또한 단차에 형성된 금속 배선의 난반사로 불량한 패턴이 발생된다. 참고적으로 반도체 소자의 금속배선은 노광 공정시 금속배선의 표면 반사율이 매우 높기 때문에 정재파나 산란파의 영향을 받기 쉽다. 이때 난반사 되는 산란광은 감광막에 침투되어 패턴의 불량을 발생시킨다.1 is a plan view of a mask and a cross-sectional view of a device for explaining a method of forming a metal wiring of a conventional semiconductor device. Referring to FIG. 1, due to the
따라서, 본 발명은 반도체 소자의 셀 영역과 주변 회로 영역 간의 단차로 인한 문제점을 해소하여 소자의 신뢰성 및 수율을 향상 시킬 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which can improve the reliability and yield of the device by solving the problem caused by the step between the cell region and the peripheral circuit region of the semiconductor device.
상기한 목적을 달성하기위한 본 발명은 셀 영역 및 주변회로 영역 간에 단차가 형성된 실리콘 기판상에 절연막 및 금속 배선을 순차적으로 형성하는 단계와, 반사방지막인 Ti/TiN 막 및 SeGe 막을 순차적으로 형성한 후 전체 상부면에 감광막을 형성하는 단계와, 제 1 마스크를 이용하여 상기 셀영역에 1 차 노광 공정을 실시한 후 제 2 마스크를 이용하여 상기 주변 회로 영역에 2 차 노광공정을 실시하는 것을 특징으로 한다.According to an aspect of the present invention, an insulating film and a metal wiring are sequentially formed on a silicon substrate on which a step is formed between a cell region and a peripheral circuit region, and a Ti / TiN film and a SeGe film, which are antireflection films, are sequentially formed. Thereafter, forming a photoresist film on the entire upper surface, and performing a first exposure process on the cell region using a first mask, and then performing a second exposure process on the peripheral circuit region using a second mask. do.
도 1은 종래 반도체 소자의 금속 배선 형성방법을 설명하기 위한 마스크의 평면도 및 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a mask and a cross-sectional view of a device for explaining a method of forming a metal wiring of a conventional semiconductor device.
도 2는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도.2 is a cross-sectional view of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
도 3a 및 도 3b는 본 발명에 따른 마스크의 평면도.3a and 3b are plan views of masks according to the invention;
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 및 17 : 주변 회로영역 2 및 16 : 셀 영역1 and 17: peripheral circuit area 2 and 16: cell area
11 : 실리콘 기판 12 : 절연막11 silicon substrate 12 insulating film
13 : 금속층 14 : Ti/TiN막13
15 : SeGe막15 SeGe film
이하, 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.
도 2를 참조하면, 셀 영역(16)과 주변 회로 영역(17)이 형성되어 있는 실리콘 기판(11)상에 절연막(12) 및 금속층(12)을 순차적으로 형성한 후 반사방지막인 Ti/TiN막(14) 및 SeGe막(15)을 순차적으로 형성한다. 이때 Ti/TiN막(14)의 두께는 200 내지 1000Å이며 SeGe막(15)의 두께는 100 내지 1500Å으로 한다. 이와같이 상기 반사 방지막(14 및 15)은 노광공정시 난반사를 제어하게 되어 패턴의 불량을 최소화 하는 역할을 한다.Referring to FIG. 2, after the insulating film 12 and the metal layer 12 are sequentially formed on the
상기 반사 방지막(14 및 15)을 형성한 후 전체 상부면에 감광막(도시않됨)을 형성한다. 이 후 노광 공정을 도 3a 및 도 3b를 참조하여 설명하면, 도 3a는 제 1 마스크의 평면도로서, 상기 제 1 마스크를 이용하여 셀영역(16)을 1 차 노광한 후 제 2 마스크(도 3b)를 이용하여 주변회로 영역(17) 2 차 노광한다.After the
이때, 청구항 제4항에서는 1차 및 2차 노광 공정 시 노광 영역이 9 내지 11um 중첩되도록 한다고 기재되어 있습니다.At this time, it is stated in claim 4 that the exposure area overlaps 9 to 11 μm during the first and second exposure processes.
이는, 1차 노광 공정 후 2차 노광 공정 시 정렬 오차가 발생되면 셀 영역(16)과 주변 회로 영역(17)이 접한 영역에서 1차 노광 공정이나 2차 노광 공정에 의해서도 노광 공정이 이루어지지 않아 패턴 형성이 이루어지지 않을 수 있다. 이러한 문제점이 발생되는 것을 방지하기 위하여 1차 노광 공정과 2차 노광 공정의 노광 영역을 중첩시킨다. 즉, 1차 및 2차 노광 공정 시 셀 영역과 주변 회로 영역에서 노광 영역이 9 내지 11㎛ 정도 겹치도록 한다.If an alignment error occurs in the secondary exposure process after the primary exposure process, the exposure process is not performed even by the primary exposure process or the secondary exposure process in the region where the
이로써, 공정 마진이 증가하여 정렬 오차에도 패턴이 형성되지 않는 문제점을 해결할 수 있다.As a result, it is possible to solve the problem that a process margin is increased and a pattern is not formed even in alignment error.
상술한 바와같이 단차가 형성된 주변 회로 영역과 셀 영역간에 노광시 발생하는 난반사를 방지하고, 노광시 가장 알맞은 초점이 형성되도록 하기 위하여 반사 방지막을 금속층상에 형성한다. 그리고 주변회로 영역과 셀 영역을 1차 및 2 차로 나누어서 노광공정을 실시한다. 그 결과 금속 배선의 패턴이 안정화 되어 소자의 신뢰성이 향상되는 효과가 있다.As described above, an antireflection film is formed on the metal layer in order to prevent diffuse reflection occurring during exposure between the peripheral circuit region where the step is formed and the cell region, and to achieve the most suitable focus during exposure. The exposure process is performed by dividing the peripheral circuit region and the cell region into primary and secondary. As a result, the pattern of the metal wiring is stabilized, thereby improving the reliability of the device.
Claims (4)
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KR1019970028509A KR100451041B1 (en) | 1997-06-27 | 1997-06-27 | Method for forming metal interconnection of semiconductor device to solve problems arising from step between cell area and peripheral circuit area of semiconductor device |
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KR1019970028509A KR100451041B1 (en) | 1997-06-27 | 1997-06-27 | Method for forming metal interconnection of semiconductor device to solve problems arising from step between cell area and peripheral circuit area of semiconductor device |
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KR100451041B1 true KR100451041B1 (en) | 2004-12-04 |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5933827A (en) * | 1982-08-19 | 1984-02-23 | Toshiba Corp | Manufacture of semiconductor device |
US5545588A (en) * | 1995-05-05 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of using disposable hard mask for gate critical dimension control |
JPH08274325A (en) * | 1995-04-03 | 1996-10-18 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH08330249A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Manufacture of semiconductor device |
KR970003473A (en) * | 1995-06-20 | 1997-01-28 | 김광호 | Fine metal wiring formation method of semiconductor device |
KR100191708B1 (en) * | 1995-06-09 | 1999-06-15 | 김영환 | Forming method for metal wiring in semiconductor device |
KR100219550B1 (en) * | 1996-08-21 | 1999-09-01 | 윤종용 | Anti-reflective coating layer and pattern forming method using the same |
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1997
- 1997-06-27 KR KR1019970028509A patent/KR100451041B1/en not_active IP Right Cessation
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5933827A (en) * | 1982-08-19 | 1984-02-23 | Toshiba Corp | Manufacture of semiconductor device |
JPH08274325A (en) * | 1995-04-03 | 1996-10-18 | Fujitsu Ltd | Manufacture of semiconductor device |
US5545588A (en) * | 1995-05-05 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of using disposable hard mask for gate critical dimension control |
JPH08330249A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Manufacture of semiconductor device |
KR100191708B1 (en) * | 1995-06-09 | 1999-06-15 | 김영환 | Forming method for metal wiring in semiconductor device |
KR970003473A (en) * | 1995-06-20 | 1997-01-28 | 김광호 | Fine metal wiring formation method of semiconductor device |
KR0155959B1 (en) * | 1995-06-20 | 1998-12-01 | 김광호 | Formation method of metal wiring in semiconductor device |
KR100219550B1 (en) * | 1996-08-21 | 1999-09-01 | 윤종용 | Anti-reflective coating layer and pattern forming method using the same |
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