KR100450238B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR100450238B1 KR100450238B1 KR10-2001-0079098A KR20010079098A KR100450238B1 KR 100450238 B1 KR100450238 B1 KR 100450238B1 KR 20010079098 A KR20010079098 A KR 20010079098A KR 100450238 B1 KR100450238 B1 KR 100450238B1
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- protective
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 87
- 230000001681 protective effect Effects 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910019001 CoSi Inorganic materials 0.000 claims description 4
- 229910004541 SiN Inorganic materials 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910003465 moissanite Inorganic materials 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000013508 migration Methods 0.000 abstract description 4
- 230000005012 migration Effects 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 28
- 230000004888 barrier function Effects 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- -1 or the like Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체 소자 제조 방법에 관한 것으로, 그 목적은 금속 배선의 일렉트로마이그레이션 및 스트레스마이그레이션 문제를 해결하는 데 있다. 이를 위해 본 발명에서는 보호금속막 또는 보호산화막으로 금속 배선을 감싸는 것을 특징으로 한다. 즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 금속 배선막을 형성하고 패터닝하여 금속 배선층을 형성하는 단계, 금속 배선층을 포함한 상부 전면에 고저항물질로 이루어진 보호금속막을 형성하고, 보호금속막 상에 보호산화막을 형성하는 단계, 및 통상적인 사진식각공정으로 금속 배선층의 상면 및 측면을 제외한 나머지 영역의 보호금속막 및 보호산화막을 식각하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and an object thereof is to solve the electromigration and stress migration problems of metal wiring. To this end, the present invention is characterized by surrounding the metal wiring with a protective metal film or a protective oxide film. That is, in the semiconductor device manufacturing method according to the present invention, forming a metal wiring layer on the structure of the semiconductor substrate to form a metal wiring layer, forming a protective metal film made of a high resistance material on the entire upper surface including the metal wiring layer, Forming a protective oxide film on the protective metal film, and etching the protective metal film and the protective oxide film in the remaining areas except the upper and side surfaces of the metal wiring layer by a conventional photolithography process.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 금속배선을 형성하는 방법에 관한 것이다.The present invention relates to a semiconductor manufacturing method, and more particularly to a method for forming a metal wiring.
반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring technology has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the interconnected metal wiring layers through vias.
그리고, 반도체 소자에서 다층 배선 기술을 적용함으로써, 교차 배선이 가능하게 되어 반도체 소자의 회로 설계에 있어서의 자유도와 집적도를 향상시킬 수 있으며, 또한 배선 길이를 단축할 수 있어 배선이 수반하는 속도의 지연 시간을 짧게 함으로써 반도체 소자의 동작 속도를 향상시킬 수 있다.By applying the multilayer wiring technology in the semiconductor device, cross wiring is possible, which improves the degree of freedom and integration degree in the circuit design of the semiconductor device, and also reduces the length of the wiring, thereby delaying the speed accompanying the wiring. By shortening time, the operation speed of a semiconductor element can be improved.
이러한 다층 배선 기술을 실현하기 위한 종래 방법에서는, 층간절연막을 선택적으로 식각하여 비아홀을 형성하고, 텅스텐이나 알루미늄의 확산으로부터 산화막을 보호하기 위하여 비아홀의 내벽에 얇은 Ti 또는 TiN 베리어 메탈을 증착한 다음, 베리어 메탈 상에 텅스텐을 형성하여 비아홀을 충진시키고, 웨이퍼 표면으로부터 텅스텐을 제거할 목적의 화학기계적 연마공정을 수행한 다음, 알루미늄 증착을 통해 블랭킷층을 형성한 후 에칭공정을 거쳐 금속 배선층을 형성하며, 이와 같은 금속 배선층 형성공정을 반복하여 다층 배선을 형성한다.In the conventional method for realizing such a multi-layered wiring technique, a via hole is formed by selectively etching the interlayer insulating film, and a thin Ti or TiN barrier metal is deposited on the inner wall of the via hole to protect the oxide film from diffusion of tungsten or aluminum, Tungsten is formed on the barrier metal to fill the via holes, and a chemical mechanical polishing process for removing tungsten from the wafer surface is performed. Then, a blanket layer is formed through aluminum deposition, followed by etching to form a metal wiring layer. Such a metal wiring layer forming step is repeated to form a multilayer wiring.
그러나, 이와 같은 종래 방법에서는 일반적으로 알루미늄 또는 알루미늄 합금 등을 금속 배선으로 사용하는데, 후속 공정을 진행하면서 열과 스트레스 등에 기인하여 배선의 저항이 증가하고 이로 인해 소자의 동작 속도가 느리게 되며 심지어는 금속 배선이 단락되기도 하는 스트레스마이그레이션이 발생하는 문제점이 있었다.However, in the conventional method, aluminum or aluminum alloy is generally used as metal wiring. Due to heat and stress, the resistance of the wiring increases due to heat and stress, which causes the operation speed of the device to be slow and even the metal wiring. This short-circuit stress migration had a problem.
또한, 반도체 소자의 사용시 전류 흐름에 기인하여 배선을 따라 알루미늄이 자체확산(self-diffusion)되는 일렉트로마이그레이션(electromigration)이 발생하는 문제점이 있었다.In addition, there is a problem in that the electromigration of the aluminum self-diffusion along the wiring due to the current flow when using the semiconductor device occurs.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 금속 배선의 일렉트로마이그레이션 및 스트레스마이그레이션 문제를 해결하는 데 있다.The present invention is to solve the problems as described above, the object is to solve the electromigration and stress migration problems of the metal wiring.
도 1a 내지 도 1c는 본 발명의 제1실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 2a 내지 도 2c는 본 발명의 제2실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 보호금속막 또는 보호산화막으로 금속 배선을 감싸는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that the metal wiring is wrapped with a protective metal film or a protective oxide film.
즉, 본 발명에 따른 반도체 소자 제조 방법은, 반도체 기판의 구조물 상에 금속 배선막을 형성하고 패터닝하여 금속 배선층을 형성하는 단계, 금속 배선층을 포함한 상부 전면에 고저항물질로 이루어진 보호금속막을 형성하고, 보호금속막 상에 보호산화막을 형성하는 단계, 및 통상적인 사진식각공정으로 금속 배선층의 상면 및 측면을 제외한 나머지 영역의 보호금속막 및 보호산화막을 식각하는 단계를 포함하여 이루어진다.That is, in the semiconductor device manufacturing method according to the present invention, forming a metal wiring layer on the structure of the semiconductor substrate to form a metal wiring layer, forming a protective metal film made of a high resistance material on the entire upper surface including the metal wiring layer, Forming a protective oxide film on the protective metal film, and etching the protective metal film and the protective oxide film in the remaining areas except the upper and side surfaces of the metal wiring layer by a conventional photolithography process.
이 때, 통상적인 사진식각공정 대신에 아르곤 가스 또는 헬륨 가스를 사용하는 스퍼터링 방법을 이용하여 금속 배선층의 상면 및 측면에 형성된 보호금속막만을 남기고 보호산화막을 전부 제거할 수도 있다.In this case, a sputtering method using argon gas or helium gas may be used instead of the conventional photolithography process, and all of the protective oxide film may be removed, leaving only the protective metal film formed on the upper and side surfaces of the metal wiring layer.
보호금속막은 Ti, Ta, Co, Si, TiN, TaN, 또는 CoSi을 700Å 이하의 두께로 형성하고, 보호산화막은 SiN, SiO2, SiON, SiC, 또는 SiOC을 1000Å 이하의 두께로 형성하는 것이 바람직하다.The protective metal film preferably forms Ti, Ta, Co, Si, TiN, TaN, or CoSi in a thickness of 700 GPa or less, and the protective oxide film forms SiN, SiO 2 , SiON, SiC, or SiOC in a thickness of 1000 GPa or less. Do.
이하, 본 발명의 제1실시예에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다. 도 1a 내지 도 1c는 본 발명의 제1실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described in detail. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판의 구조물(1), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(2)을 형성하고, 하부절연막(2) 상에 베리어 메탈(3), 금속막(4), 및 반사방지막(5)을 순차적으로 형성한다.First, as shown in FIG. 1A, a lower insulating film 2 made of an oxide film or the like is formed on a structure 1 of a semiconductor substrate, that is, on a semiconductor substrate or a lower metal wiring layer on which individual elements are formed, and then on the lower insulating film 2. The barrier metal 3, the metal film 4, and the antireflection film 5 are sequentially formed.
이어서, 반사방지막(5) 상에 감광막을 도포하고 노광 현상하여 감광막 패턴(6)을 형성한다.Subsequently, a photoresist film is applied and exposed to light on the antireflection film 5 to form a photoresist pattern 6.
다음, 감광막 패턴(6)을 마스크로 하여 반사방지막(5), 금속막(4), 및 베리어메탈(3)을 선택적으로 식각하여 도 1b에 도시된 바와 같이 금속배선층을 형성한 다음, 감광막 패턴(6)을 제거하고 세정공정을 수행한다.Next, the antireflection film 5, the metal film 4, and the barrier metal 3 are selectively etched using the photoresist pattern 6 as a mask to form a metal wiring layer as shown in FIG. 1B. (6) is removed and cleaning process is performed.
이어서, 패터닝된 금속배선층을 포함한 상부 전면에 Ti, Ta, Co, Si, TiN, TaN 또는 CoSi 등으로 보호금속막(7)을 증착하고, 보호금속막(7) 상에 SiN, SiO2, SiON, SiC, 또는 SiOC 등으로 보호산화막(8)을 증착한다. 이 때 보호금속막(7)은 약 700Å 이하의 두께로 형성하고 보호산화막(8)은 약 1000Å 이하의 두께로 형성한다.Subsequently, the protective metal film 7 is deposited on the upper surface including the patterned metal wiring layer by Ti, Ta, Co, Si, TiN, TaN, CoSi, or the like, and SiN, SiO 2 , SiON is formed on the protective metal film 7. The protective oxide film 8 is deposited by, SiC, SiOC or the like. At this time, the protective metal film 7 is formed to a thickness of about 700 kPa or less, and the protective oxide film 8 is formed to a thickness of about 1000 kPa or less.
여기서, 보호금속막의 형성 전에 금속배선층 표면의 자연산화막을 제거할 수도 있다.Here, the natural oxide film on the surface of the metal wiring layer may be removed before the protective metal film is formed.
또한, 보호금속막(7)과 보호산화막(8)의 순서를 서로 바꾸어 형성할 수도 있으며, 보호금속막(7)과 보호산화막(8)을 교대로 2회 이상 증착하여 적층구조로 형성할 수도 있다.In addition, the protective metal film 7 and the protective oxide film 8 may be formed in a reverse order. Alternatively, the protective metal film 7 and the protective oxide film 8 may be alternately deposited two or more times to form a stacked structure. have.
다음, 보호산화막(8) 상에 감광막을 도포하고 노광 현상하여 금속배선층의 상면 및 측면을 덮으면서 금속배선층 사이의 보호산화막을 노출시키는 감광막 패턴(9)을 형성한다.Next, a photosensitive film is coated on the protective oxide film 8 and exposed to light to form a photosensitive film pattern 9 exposing the protective oxide film between the metal wiring layers while covering the top and side surfaces of the metal wiring layer.
다음, 도 1c에 도시된 바와 같이, 감광막 패턴(9)을 마스크로 하여 금속 배선층의 상면 및 측면을 제외한 나머지 영역의 보호산화막(8) 및 보호금속막(7)을 식각한 후, 제2감광막 패턴(9)을 제거하고 세정공정을 수행함으로써, 보호금속막(7) 및 보호산화막(8)으로 둘러싸인 금속배선층 형성을 완료한다.Next, as shown in FIG. 1C, after etching the protective oxide film 8 and the protective metal film 7 in the remaining areas except the upper and side surfaces of the metal wiring layer using the photosensitive film pattern 9 as a mask, the second photosensitive film is etched. By removing the pattern 9 and performing a cleaning process, the formation of the metal wiring layer surrounded by the protective metal film 7 and the protective oxide film 8 is completed.
또다른 실시예로서, 보호산화막 없이 보호금속막만으로 둘러싸인 금속배선층을 형성할 수도 있는데, 이는 제2실시예로서, 본 발명의 제2실시예에 따른 반도체 소자 제조 방법에 대한 상세히 설명은 다음과 같다. 도 2a 내지 도 2c는 본 발명의 제2실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.As another embodiment, a metal wiring layer surrounded by only a protective metal film may be formed without a protective oxide film. As a second embodiment, a detailed description of a method of manufacturing a semiconductor device according to a second embodiment of the present invention is as follows. . 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판의 구조물(1), 즉 개별 소자가 형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(2)을 형성하고, 하부절연막(2) 상에 베리어 메탈(3), 금속막(4), 및 반사방지막(5)을 순차적으로 형성한다.First, as shown in FIG. 2A, a lower insulating film 2 made of an oxide film or the like is formed on a structure 1 of a semiconductor substrate, that is, on a semiconductor substrate or a lower metal wiring layer on which individual elements are formed, and then on the lower insulating film 2. The barrier metal 3, the metal film 4, and the antireflection film 5 are sequentially formed.
이어서, 반사방지막(5) 상에 감광막을 도포하고 노광 현상하여 감광막 패턴(6)을 형성한다.Subsequently, a photoresist film is applied and exposed to light on the antireflection film 5 to form a photoresist pattern 6.
다음, 감광막 패턴(6)을 마스크로 하여 반사방지막(5), 금속막(4), 및 베리어메탈(3)을 선택적으로 식각하여 도 2b에 도시된 바와 같이 금속배선층을 형성한 다음, 감광막 패턴(6)을 제거하고 세정공정을 수행한다.Next, the antireflection film 5, the metal film 4, and the barrier metal 3 are selectively etched using the photoresist pattern 6 as a mask to form a metal wiring layer as shown in FIG. 2B. (6) is removed and cleaning process is performed.
이어서, 패터닝된 금속배선층을 포함한 상부 전면에 Ti, Ta, Co, Si, TiN, TaN 또는 CoSi 등으로 보호금속막(7)을 증착하고, 보호금속막(7) 상에 SiN, SiO2, SiON, SiC, 또는 SiOC 등으로 보호산화막(8)을 증착한다. 이 때 보호금속막(7)은 약 700Å 이하의 두께로 형성하고 보호산화막(8)은 약 1000Å 이하의 두께로 형성한다.Subsequently, the protective metal film 7 is deposited on the upper surface including the patterned metal wiring layer by Ti, Ta, Co, Si, TiN, TaN, CoSi, or the like, and SiN, SiO 2 , SiON is formed on the protective metal film 7. The protective oxide film 8 is deposited by, SiC, SiOC or the like. At this time, the protective metal film 7 is formed to a thickness of about 700 kPa or less, and the protective oxide film 8 is formed to a thickness of about 1000 kPa or less.
또한, 보호금속막(7)의 형성 전에 금속배선층 표면의 자연산화막을 제거할 수도 있다.In addition, the native oxide film on the surface of the metal wiring layer may be removed before the protective metal film 7 is formed.
다음, 아르곤 가스 또는 헬륨 가스를 사용한 스퍼터링 또는 플라즈마 식각 방법으로 금속 배선층의 상면 및 측면에 형성된 보호금속막(7)만을 남기고 보호산화막을 전부 제거함으로써, 도2c 에 도시된 바와 같이, 보호금속막(7)으로 둘러싸인 금속배선층 형성을 완료한다.Next, by removing all of the protective oxide film leaving only the protective metal film 7 formed on the upper and side surfaces of the metal wiring layer by a sputtering or plasma etching method using argon gas or helium gas, as shown in FIG. 2C, the protective metal film ( 7) Complete the formation of the metal wiring layer surrounded by.
상술한 바와 같이, 본 발명에서는 금속배선층의 상면 및 측면에 보호금속막 및 보호산화막을 형성하여 금속배선층을 둘러싸기 때문에, 금속 배선의 일렉트로마이그레이션 및 스트레스마이그레이션이 억제되는 효과가 있으며, 또한 금속 배선의 변형이 억제되는 효과가 있다.As described above, in the present invention, since the protective metal film and the protective oxide film are formed on the upper and side surfaces of the metal wiring layer to surround the metal wiring layer, the electromigration and the stress migration of the metal wiring are suppressed, and the metal wiring can be suppressed. Deformation is suppressed.
Claims (8)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6266628A (en) * | 1985-09-19 | 1987-03-26 | Oki Electric Ind Co Ltd | Forming method for interconnection of semiconductor element |
| JPH1056022A (en) * | 1996-08-12 | 1998-02-24 | Nec Corp | Semiconductor device and manufacture thereof |
| KR19990086608A (en) * | 1998-05-29 | 1999-12-15 | 김규현 | Method for manufacturing metal wiring layer of semiconductor device |
| KR20000002928A (en) * | 1998-06-24 | 2000-01-15 | 윤종용 | Metal wiring structure of semiconductor device and production method thereof |
| KR20000027159A (en) * | 1998-10-27 | 2000-05-15 | 김영환 | Method for forming metal line of semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6266628A (en) * | 1985-09-19 | 1987-03-26 | Oki Electric Ind Co Ltd | Forming method for interconnection of semiconductor element |
| JPH1056022A (en) * | 1996-08-12 | 1998-02-24 | Nec Corp | Semiconductor device and manufacture thereof |
| KR19990086608A (en) * | 1998-05-29 | 1999-12-15 | 김규현 | Method for manufacturing metal wiring layer of semiconductor device |
| KR20000002928A (en) * | 1998-06-24 | 2000-01-15 | 윤종용 | Metal wiring structure of semiconductor device and production method thereof |
| KR20000027159A (en) * | 1998-10-27 | 2000-05-15 | 김영환 | Method for forming metal line of semiconductor device |
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