KR100459683B1 - Manufacturing method of polysilicon pattern for semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a polysilicon pattern of a semiconductor device is provided to easily eliminate residue like a stringer remaining when a material layer pattern is formed by forming a polysilicon pattern having a sidewall of a positive slant. CONSTITUTION: A polysilicon layer is formed on a semiconductor substrate(100). An etch stop layer pattern is formed on the polysilicon layer. The polysilicon layer is tilt-etched by using reaction gas including He gas, SF6 gas and Cl2 gas while using the etch stop layer pattern as a mask. An over-etching process is performed on the resultant structure by using reaction gas including Cl2 gas and HBr gas. The polysilicon stringer remaining on the tilt-etched structure is etched by using reaction gas including the reaction gas of the tilt-etch process, He gas and SF6 gas.

Description

Manufacturing method of polysilicon pattern for semiconductor device

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of forming a polysilicon pattern of a semiconductor device using a gradient etching method.

As the integration of semiconductor devices is rapidly increased, the area in which a pattern is formed on a semiconductor substrate is reduced, and the distance between patterns becomes smaller. Thus, the step height of the structures on the semiconductor substrate is relatively high. When a pattern of materials is applied and patterned on a structure having a narrow gap between such patterns and a high step, residues, eg, stringers, remain in the corners of the stepped portions. In particular, if the sidewall of the structure is vertical or negative slope, i.e., the lower gap of the step is greater than the upper gap, the stringer has a positive slope, i.e., the lower gap of the step is less than the upper gap. More remaining When the material layer is conductive, for example, a polysilicon layer or a metal layer, the remaining stringer acts as an electrical resistor to increase the electrical failure rate of the semiconductor device.

Referring to Fig. 1, the problem of the conventional method is shown. The conventional method forms a polysilicon pattern in the following manner. First, an insulating layer such as a first lower material layer 20, for example, a silicon nitride (SiN) layer, is formed on the semiconductor substrate 10. An insulating layer, such as a first conductive layer pattern 30 and a second lower material layer pattern 40, for example, a silicon nitride layer, is formed on the first lower material layer 20. Thereafter, a second conductive layer, for example, a polysilicon layer, is formed on the second lower material layer pattern 40. Thereafter, a photoresist pattern (not shown) is formed on the second conductive layer. A portion of the second conductive layer is dry-etched using the photoresist pattern as a mask to form a second conductive layer pattern 50, that is, a polysilicon pattern. Thereafter, over etching is performed for a predetermined time.

In such a conventional method, when etching the second conductive layer, an unetched protrusion such as A may be formed. In addition, the stringer 60 remains in the stepped portion when the second conductive layer is etched. Excessive excessive etching is required to remove the stringer 60. This excess over-etching further reduces process margins. In addition, the first and second lower material layer patterns 20 and 40 formed with a thin thickness may be severely impaired, such that a defect B may occur. The defect may cause an electrical defect such as an electrical short in a subsequent metal wiring process.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for preventing severe invasion of a lower material layer, removing remaining stringers, and forming a material layer pattern, particularly a polysilicon pattern.

1 is a cross-sectional view for explaining the problem of the conventional polysilicon pattern forming method.

2 to 6 are cross-sectional views for explaining the polysilicon pattern forming method of the present invention.

In order to achieve the above technical problem, the present invention forms a polysilicon layer on a semiconductor substrate including a lower structure. After the etching, an etch stop layer pattern is formed on the polysilicon layer. In this case, a photoresist pattern is used as the etch stop layer pattern. Subsequently, the polysilicon layer is inclinedly etched to have a positive inclination with a reaction gas including helium (He) gas, sulfur hexafluoride (SF6) gas, and chlorine (Cl2) gas using the etch stop layer pattern as a mask. . At this time, the flow rate of the chlorine (Cl2) gas is 30% or less of the flow rate of the helium (He) gas or sulfur hexafluoride (SF6) gas. In addition, the surface of the substructure is used as the reaction endpoint of etching. After the removal, the polysilicon stringer is etched and removed with a reaction gas including helium (He) gas and sulfur hexafluoride (SF6) gas.

In addition, the present invention further includes the step of over-etching the resultant of the inclined etching after a predetermined time. At this time, transient etching is performed with a reaction gas including chlorine (Cl 2) gas and hydrogen bromide (HBr) gas. Subsequently, the excess etched resultant is etched with a reaction gas including helium (He) gas and sulfur hexafluoride (SF6) gas to remove the remaining polysilicon stringer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 6 are cross-sectional views for explaining the polysilicon pattern forming method of the present invention.

2 illustrates a step of forming a lower structure on the semiconductor substrate 100.

First, a silicon nitride layer (SiN) is coated on the semiconductor substrate 100 to a thickness of approximately 300 kPa to form the first insulating layer 200. Thereafter, a conductive layer, such as a polysilicon layer, is formed on the first insulating layer 200 to a thickness of approximately 4000 kPa. Subsequently, a first etch stop layer pattern (not shown) is formed on the conductive layer, for example, a photoresist pattern. A portion of the conductive layer is etched using the first etch stop layer pattern as a mask to form a conductive layer pattern 300. In this case, a dry etching method or a wet etching method is used. Preferably, a dry etching method using a plasma generator is used.

Sidewalls of the conductive layer pattern 300 may have any inclination. For example, in the case of a charge coupled device (CCD), the sidewall of the conductive layer pattern 300 has a vertical slope or a negative slope as necessary, that is, an upper portion of the conductive layer pattern 300. It may have the same slope as when the width is greater than the bottom width. In addition, as shown in FIG. 1, a positive inclination, that is, the inclination of the upper portion of the first conductive layer pattern 300 may be smaller than the lower width.

After that, an insulating layer covering the conductive layer pattern 300 is formed. For example, a silicon nitride layer is formed. A second etch stop layer pattern (not shown) is formed on the silicon nitride layer, for example, a photoresist pattern. The silicon nitride layer is etched using the photoresist pattern as a mask. For example, the silicon nitride layer is etched by a dry etching method using a plasma generator. In this way, the second insulating layer pattern 400 covering the conductive layer pattern 300 is formed. In this case, the second insulating layer pattern 400 is formed to have a thickness of approximately 300 kPa to 400 kPa. As described above, a lower structure is formed on the semiconductor substrate 100.

3 illustrates a step of sequentially forming the polysilicon layer 500 and the third etch stop layer pattern 600 on the semiconductor substrate 100.

First, a polysilicon layer 500 covering the second insulating layer pattern 400 is formed on the semiconductor substrate 100 to have a thickness of about 4000 GPa. At this time, a method such as chemical vapor deposition (CVD) is used. Thereafter, a photoresist layer is coated on the polysilicon layer 500. Thereafter, the photoresist layer is exposed and developed to form a photoresist pattern to form a third etch stop layer pattern 600.

4 illustrates the step of patterning the polysilicon layer 500 to form the polysilicon pattern 550.

The polysilicon layer 500 is etched by a dry etching method such as a method of using a plasma generating apparatus using the third etch stop layer pattern 600, for example, a photoresist pattern as a mask. In this case, a reaction gas including sulfur hexafluoride (SF6) gas, chlorine (Cl2) gas, and helium (He) gas is used as an etching gas. The reaction gas is a condition for isotropic etching the polysilicon layer 500. That is, as the etching reaction proceeds, the exposed region of the polysilicon layer 500 is etched, and at the same time, the polysilicon at the interface 700 shielded by the third etch stop layer pattern 600. A portion of layer 500 is also etched. As the etching reaction proceeds from the surface portion of the exposed region of the polysilicon layer 500 to the lower portion, the portion is continuously etched by the etch stop layer pattern 600. The sidewalls thus formed have a positive slope. As such, the polysilicon pattern 550 is formed.

The degree of inclination of the side wall is controlled by an etching condition, for example, the flow rate of the reactant gas supplied and the flow rate of the component gas therein, the etching reaction time, and the power applied to the plasma generator during the etching reaction. In the present embodiment, a reaction gas including a chlorine gas having a flow rate of 20 sccm (Standard Cubic CentiMeter) to 300 sccm, a sulfur hexafluoride gas having a flow rate of 100 sccm to 1000 sccm, and a helium gas having a flow rate of 100 sccm to 1000 sccm is used. At this time, the flow rate of the chlorine gas in each component gas of the reaction gas is supplied to be at most 30% or less than the flow rate of the sulfur hexafluoride gas. Under such etching conditions, a polysilicon pattern 550 having a positively inclined profile may be formed. Therefore, the remaining residue and the polysilicon stringer can be more easily removed than in the case of the polysilicon pattern having a negative slope or a vertical slope. In addition, the etching conditions may prevent defects such as the conventional protrusion A, which is caused by not etching the polysilicon at the interface portion 700 of the etch stop layer pattern 600 and the polysilicon pattern 550. Can be.

The upper surface 400 of the lower structures 200, 300, 400 of the polysilicon pattern 550 is used as an end point of the inclined etching. That is, the surface of the second insulating layer pattern 400 is used as an end point of the inclined etching. For example, when the second insulating layer pattern 400 is a silicon nitride layer, when the nitride is detected during the inclined etching, the inclined etching is stopped. In this way, the residue of the gradient etching reaction is left in the form of polysilicon stringer 800 on the side of the substructure. In addition, a residue 900 remaining without being etched remains on the lower sidewall portion of the polysilicon pattern 550. Thereafter, the stringer 800 and the residue 900 are removed.

5 illustrates removing the stringer 800 and residue 900 on the semiconductor substrate 100.

After the gradient etching step, the reaction gas including the helium gas and the sulfur hexafluoride gas is isotropically etched by adjusting the etching time so that the profile of the polysilicon pattern 550 is not impaired. The reaction gas containing the helium gas and the sulfur hexafluoride gas has a higher reactivity with polysilicon than the reaction gas used in the gradient etching step. Therefore, the residue 900 and the stringer 800 may be removed in a shorter time, thereby preventing invasion of the lower first and second insulating layers 200 and 400. In addition, since the isotropic etching is performed, the polysilicon stringer 800 may be easily removed even when the sidewall of the substructure has a vertical or negative slope. In addition, since the polysilicon pattern 550 has a positive slope, the residue 900 may be more easily removed. In addition, when subsequently applying and patterning an insulating layer (not shown) and a conductive layer (not shown) on the polysilicon pattern 550, it is easy to remove an etching residue such as the polysilicon stringer 800. Become. As such, the polysilicon stringer 800 and the residue 900 are removed.

Alternatively, over etching may be further performed as a step before performing the isotropic etching step. For example, even after the etching end point is detected by the reactive gas of the gradient etching process described with reference to FIG. 4, that is, a reactive gas including sulfur hexafluoride (SF6) gas, chlorine (Cl2) gas, and helium (He) gas. Time proceeds the etching reaction further.

Alternatively, after the etching end point of the oblique etching process is detected to terminate the etching reaction, transient etching is performed with another reaction gas replacing the reaction gas. For example, the etching selectivity of the second insulating layer pattern 400 or the first insulating layer pattern 200 and the second insulating layer pattern 400 is excessively etched with an etching condition higher than that of the etching condition used in the inclined etching. Proceed. For example, the hydrogen bromide (HBr) gas and the chlorine gas having the silicon nitride layer and the etching selectivity, which are the first insulating layer pattern 200 and the second insulating layer pattern 400, are higher than the reactive gas used in the gradient etching. Proceed with excessive etching with a reaction gas comprising a. In this way, the first and second insulating layer patterns 200 and 400 may be prevented from invading and the residue 900 and the polysilicon stringer 800 of the inclined etching process may be removed. At this time, the progress time of the excessive etching is adjusted so that the profile of the polysilicon pattern 550 is not violated.

Thereafter, the resultant of the excessive etching isotropically etched with a reaction gas containing the helium gas and sulfur hexafluoride gas. By performing this isotropic etching, the polysilicon stringer 800 and the residue 900 remaining in the result of the transient etching are removed. In this case, the isotropic etching time is adjusted so that the profile of the polysilicon pattern 550 is not infringed. In this way, after the end of the inclined etching, the excess etching is further added to the step of removing the residue 900 and the stringer 800 to prevent the intrusion of the first and second insulating layer patterns 200 and 400. To further prevent and remove residue 900 and stringer 800.

5 illustrates removing the etch stop layer pattern 600 from the semiconductor substrate 100.

After removing the residue 900 and the polysilicon stringer 800, the third etch stop layer pattern 600 is removed. For example, when the third etch stop layer pattern 600 is a photoresist pattern, it is removed by ashing. The ashed result is then washed by a wet cleaning method.

In the above, the present invention has been described in detail with reference to specific embodiments, but the present invention is not limited to the above-described embodiments, and modifications and improvements of the present invention are made by those skilled in the art within the scope of the technical idea of the present invention. It is obvious that this is possible.

The above-described method can form a polysilicon pattern having positively sloped sidewalls. Therefore, it is easy to remove residues such as stringers remaining when forming the material layer pattern thereafter. In addition, it is possible to prevent the defective profile of the polysilicon pattern generated at the interface between the unexposed region of the polysilicon layer and the etch stop layer pattern used as the mask. Thus, a polysilicon pattern having a good sidewall profile can be formed.

In addition, the reaction gas containing a polysilicon pattern having positively inclined sidewalls and helium gas and sulfur hexafluoride gas is used to prevent intrusion into the first and second insulating layers, which are lower material layers, and to prevent residues and polysilicon. The stringer can be removed more easily. In addition, the step of over-etching with a reaction gas containing hydrogen bromide gas and chlorine gas can be added to further prevent intrusion into the underlying material layer, the first and second insulating layers, and remove residues and polysilicon stringers. have.

Claims (2)

Forming a polysilicon layer on the semiconductor substrate; Forming an etch stop layer pattern on the polysilicon layer; Obliquely etching the polysilicon layer with a reaction gas including a helium (He) gas, a sulfur hexafluoride (SF6) gas, and a chlorine (Cl 2) gas using the etch stop layer pattern as a mask; Over etching the gradient-etched result with a reaction gas including chlorine (Cl 2) gas and hydrogen bromide (HBr) gas; And Etching away the polysilicon stringer remaining on the gradient etched product with a reaction gas including the reaction gas, helium (He) gas, and sulfur hexafluoride (SF6) gas in the gradient etching. A polysilicon pattern forming method of a semiconductor device. The polysilicon pattern of claim 1, wherein the flow rate of the chlorine (Cl 2) gas is in a range of 1% to 30% of the flow rate of the helium (He) gas or the sulfur hexafluoride (SF6) gas. Way.

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