KR100457739B1 - High frequency test device - Google Patents

Abstract

The present invention relates to a high frequency test apparatus, and more particularly, to a high frequency test apparatus for overcoming the speed limit of an off-chip test equipment by controlling a clock period inside the chip. This enables high frequency testing at the wafer level, increasing the upgrade cycle of the test equipment, and reducing the cost by selecting fail chips at high speed before packaging the chips.

Description

High frequency test device

The present invention relates to a high frequency test apparatus, and in particular, by reducing the period of the internal master clock by using the frequency divider in the memory chip, it is possible to remove the constraints of the speed due to the speed of external equipment or the interface loading and to perform the high frequency test. To a high frequency test apparatus.

The test frequency used in a conventional test device depends on the clock generation capability of the device and the LRC level of the device and the chip-to-chip interface.

Therefore, in the functional test at the wafer level, the LRC increases due to the wires necessary for the probe card and bonding between the device and the chip, and the clock generation capability of the device itself is more than 50 MHz. In functional testing was almost impossible.

This forced the memory chip to be packaged in a state where the drive capability of the device was not verified during the high frequency test.

When the high frequency function test is performed in the packaged chip state, the difference between the wafer yield and the package yield is inevitably increased. In this case, the production cost of the chip increases.

In addition, the operation speed of the semiconductor chip is rapidly improving, while the clock generation speed of the equipment used for the test is less than the operation speed of the semiconductor chip, thereby increasing test difficulties.

Therefore, the only solution to the problem of the existing test apparatus is to upgrade the test equipment, which is also a major cause of increasing the production cost of the semiconductor chip.

The present invention was created to solve the above problems, and has a first object of generating a high frequency internal clock and using the same when performing a high frequency test.

In addition, the present invention has a second object of generating an internal clock in a frequency division scheme, selecting an external clock or an internal clock, and using the same for a high frequency test.

In addition, the present invention has a third purpose to increase the frequency of the chip internal clock and control the pattern of the internal data using a PLL, DLL or clock period divider.

1 is a block diagram of a high frequency test apparatus according to the present invention,

2 is a timing diagram related to the high frequency test apparatus of FIG. 1;

3 is a view of a clock selector of the high frequency test apparatus according to the present invention;

4 is a view of an input data control unit of the high frequency test apparatus according to the present invention;

5 is a circuit diagram of a clock frequency division unit of the high frequency test apparatus according to the present invention;

6 is an operation timing diagram of a high frequency test apparatus according to the present invention.

<Description of Symbols for Main Parts of Drawings>

70: PLL 80: clock selector

100: clock frequency division unit 120: input data control unit

In order to achieve the above object, the high frequency test apparatus of the present invention includes a clock buffer for receiving and buffering an external clock, and a frequency adjusting means for increasing the frequency of the internal clock by receiving a buffered external clock output from the clock buffer. Clock selection means for selecting the buffered external clock or the internal clock output from the frequency adjusting means and outputting the internal clock as an internal master clock according to a state of a high frequency test mode entry signal, and the internal master clock applied from the clock selection means And clock frequency dividing means for outputting a data clock signal for controlling data at one cycle of the clock according to a logical combination of a power-up signal and a data combination according to the logical combination of the data clock signal and the data pattern selection signal. Input to output to the input line Another control means is provided. Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a high frequency test mode of a high frequency test apparatus according to a first embodiment of the present invention. Is a block diagram of a PLL for increasing the frequency of a clock internal master clock above the frequency of an external clock.

The configuration of FIG. 1 includes a clock buffer 10 that receives an external clock, buffers the output, and a PLL 70.

The PLL 70 charge pumps a phase frequency detector 20 for detecting and outputting a phase frequency of an external clock output from the clock buffer 10 and a signal input from the phase frequency detector 20. A charge pump unit 30, a loop filter 40 for filtering a signal applied from the charge pump unit 30, and a frequency of a signal applied from the loop filter 40. The frequency divider 60 outputs the frequency controlled oscillator 50 that outputs the clock Imclk and the internal clock Imclk that is output from the voltage controlled oscillator 50, and divides the frequency into the phase frequency detector 20. )

Here, a phase-locked loop (PLL) 70 is used to increase the frequency of an internal clock by receiving an external clock frequency, and frequency the internal clock Imclk fed back to the phase frequency detector 20. The division unit 60 divides the signal by using the division unit 60, and increases the internal clock frequency Imclk, which is the output of the voltage controlled oscillator 50.

That is, the output ratio of the PLL 70 for the external clock period, that is, the decrease ratio of the internal master clock is determined according to the number of the frequency divider 60 used.

If the duty cycle of the external clock is correctly input at 50%, the phase is compared at the rising edge and the falling edge of this clock.If the duty cycle of the external clock is not exactly 50%, the rising edge of the external clock and the external clock are Compare the rising edges of the divided internal clocks that occur first among the clocks generated during one period.

Therefore, in the embodiment of the present invention, although the PLL 70 is used to increase the frequency of the internal clock, a clock cycle divider that does not compare the phase with the DLL or the external clock may be used instead of the PLL 70. .

2 is an operation timing diagram of the high frequency test apparatus of FIG. 1, and it can be seen that the frequency of the high frequency test clock is increased compared to the external clock.

On the other hand, Figure 3 is another embodiment of a high frequency test apparatus according to the present invention.

Referring to FIG. 3, an embodiment of the present invention increases an internal clock (Imclk) by increasing a frequency of a clock buffer 10 that receives an external clock and buffers and outputs an external clock applied from the clock buffer 10. And a clock selector 80 for selecting a normal internal master clock and an internal master clock int_mclk in the high frequency test mode.

Here, the clock selector 80 receives the high frequency test mode entry signal st_hfreq through the PMOS transistor and the high frequency test mode entrance signal st_hfreq inverted by the inverter IV1 through the NMOS transistor. According to the state, the transmission gate PG0 for outputting the external clock applied from the clock buffer 10 as the internal master clock signal int_mclk and the high frequency test mode entry signal st_hfreq through the NMOS transistor are input to receive the PMOS transistor. Receives the high frequency test mode entry signal st_hfreq inverted by the inverter IV1 and transmits the internal clock Imclk applied from the PLL 70 as the internal master clock signal int_mclk according to the state of the signal. The gate PG1 is formed.

Accordingly, the clock selector 80 selectively controls the transmission gates PG0 and PG1 according to the state of the high frequency test mode entry signal st_hfreq, and outputs the external clock as the internal master clock int_mclk during the normal test. In the high frequency test mode, the frequency increased internal clock (Imclk) applied from the PLL 70 is output to the internal master clock.

That is, the external clock applied from the clock buffer 10 is used in normal operation, and the output of the multiple PLL 70, DLL, or clock period divider for dividing the frequency of the internal clock in the high frequency test mode. Is used as the internal master clock (int_mclk).

The operation of the clock selector of the present invention having such a configuration will be described below.

First, when the high frequency test mode entry signal st_hfreq indicating high frequency test mode entry is enabled, the transmission gate PG1 is turned on to output the output of the internal clock Imclk applied from the PLL 70 to the internal master clock int_mclk. Will be printed).

In addition, when the high frequency test mode entry signal st_hfreq is disabled, the transmission gate PG0 is turned on so that the output of the external clock applied from the clock buffer 10 becomes the internal master clock signal int_mclk.

On the other hand, in the normal high frequency test, the extraction of read data is possible about two in one clock.

Accordingly, two data strobe signals are displayed within one clock period to extract data input from the chip, and compare the data input to the chip upon writing to determine the pass / fail.

In this high frequency test, n data can be exported during one external clock cycle. If the number of data strobes of the equipment is not n, the number of tests is increased and the data strobe enable time is changed each time.

Therefore, the read operation during the high frequency test can be implemented by changing the test method without changing or adding a circuit inside the chip.

On the other hand, in the case of writing during a high frequency test, it is not easy to send two or more pieces of data during one cycle of the clock in the test equipment, and thus a method of controlling data at the time of writing should be considered.

As mentioned above, the situation to be considered when writing a high frequency test can be divided into two.

One must output two or more data (indicated by n for convenience) to the write divider during an external clock cycle, and one must support both solid write and check boarder methods.

Here, when data is written to a memory cell every clock through the DQ pin during burst writing, the same data every clock, for example, 1 is continuously 1, 0 is continuously 0, is input to the DQ pin. This is called solid light.

In addition, when data is toggled every clock, that is, once the data of 0 is input and 1 is input, it is called a check border recording method.

From the point of view of the external test equipment, only one data can be supplied to the chip for one clock, so it is only possible to supply the same data regardless of whether the data is written to the cell in a solid or check border manner.

Therefore, in the present invention, the pattern of write data is determined inside the chip regardless of external test equipment.

FIG. 4 is an embodiment of a high frequency test apparatus for determining the internal pattern of data in the chip when writing the memory data as described above.

Referring to FIG. 4, the high frequency test apparatus of the present invention includes an internal clock having a frequency increased by increasing the frequency of the clock buffer 10 that receives the external clock and buffers the output and the external clock applied from the clock buffer 10. PLL 70 for outputting Imclk, a clock selector 80 for selecting a normal internal master clock and an internal master clock int_mclk in the high frequency test mode, and an internal applied from the clock selector 80 A clock frequency divider 100 that receives the master clock signal int_mclk and a power-up signal pwrup and outputs a data clock signal data_clk, and a data clock applied from the input data data and the clock frequency divider 100. The input data control unit 120 controls the input data data according to the signal data_clk.

Here, the input data controller 120 includes a data input buffer 110 for receiving and buffering input data data, an inverter IV10 for inverting and outputting a signal output from the data input buffer 110, and a clock frequency division unit. A NAND gate 120 for receiving a data clock signal data_clk and a test mode entry signal st_hfreq_ckbd for selecting a data pattern from the 100 and performing an NAND operation, and outputs the NAND gate 120 through a PMOS transistor. The received signal, the output signal of the NAND gate 120 inverted from the inverter IV11 through the NMOS transistor, and the signal applied from the inverter IV10 according to the input of the signal to the global input line din_line. Receives the output signal from the NAND gate 120 through the transmission gate (PG6) and the NMOS transistor to output, and inverted from the inverter (IV11) through the PMOS transistor It receives the output signal of the NAND gate 120 comprises a transfer gate (PG7) to output as the input to the global line (din_line) the signal applied from the data input buffer 110 in accordance with input of the signal.

The signal that is enabled when entering the test mode for data pattern selection after entering the high frequency test mode is the test mode entry signal (st_hfre_ckbd) for data pattern selection.

First, when this signal is activated high, the transmission gate PG7 is turned on, and the data output from the data input buffer 110 is converted into the internal master clock signal according to the data clock data_clk which is the output of the clock frequency divider 100. Toggles every one period of (int_mclk) and outputs it to the global input line (din_line).

In addition, when the test mode entry signal st_hfre_ckbd for data pattern selection becomes low, the data inverted by the turn-on of the transmission gate PG6 is output to the global input line din_line.

Therefore, the external clock stores the data of the n high frequency test internal clocks in the cell during one clock cycle.

5 is a detailed circuit diagram of the clock frequency division unit 100 described above.

Referring to FIG. 5, a circuit diagram of a clock frequency divider 100 for dividing a frequency in order to control data of an internal master clock used in a high frequency test every cycle is shown.

That is, the clock frequency dividing unit 100 controls to become low in the next cycle when the clock frequency divider 100 becomes high for one cycle of the clock so as to perform data control for each cycle of the clock.

The clock frequency divider 100 receives an inverted internal master clock signal int_mclk and a power-up signal Pwrup through the inverter IV2 and NAND to output an output signal inc. And an inverter IV3 for inverting the output signal inc of the NAND gate 90 and outputting the incb signal.

Then, the inverter IV4 for inverting and outputting the output signal of the PMOS transistor P1, the PMOS transistor P1 receiving the power-up signal Pwrup to its gate terminal, and the output of the inverter Inverter IV5 outputs to PG2) and incb signal through PMOS transistor, inc signal through NMOS transistor, and is turned on according to the input of this transmission gate to output the signal from inverter IV4. (PG2) and the transmission gate (PG3) for receiving the incb signal through the PMOS transistor, the inc signal through the NMOS transistor, and turns on according to the input of this signal to output the signal applied from the inverter IV4, and the transmission. Inverter IV6 that inverts the output of gate PG3, Inverter IV7 that inverts the output of inverter IV6 and outputs to transfer gate PG4, and an inc signal through an PMOS transistor and receives an NMOS transistor. The incb signal is input through the jitter, and is turned on in response to the input of the incb signal to output the signal applied from the transmission gate PG3 and the output of the inverter IV6 by inverting the output of the data clock signal data_clk. The inverter IV9 is output.

Accordingly, the clock frequency divider 100 transmits PG2, PG3, PG4, and PG5 according to a logical combination of an internal master clock int_mclk and a power up signal applied from the clock selector 80 of FIG. ) Is sequentially turned on and outputs a data clock signal data_clk for controlling data at one cycle of the clock.

6 is a timing diagram of check border recording in the high frequency test mode according to the present invention.

6, it can be seen that two data can be output to the global input line during one period of the external clock.

Here, the hatched portions represent data opposite to the external input data.

In FIG. 6, the write-border operation timing diagram of the check border method is shown. However, in the solid write method, when the access operation is performed immediately after entering the high frequency test mode, the test mode entry signal (st_hfreq_ckbd) for data pattern selection is disabled to low. It only splits the data, so there is no change in the polarity of the data.

As described above, the high frequency test apparatus of the present invention automatically divides the frequency supplied from an external device in the chip, thereby enabling high frequency testing even in low frequency test equipment, thereby reducing both test time and cost. to provide.

Claims (20)

delete delete delete delete A clock buffer which receives an external clock and buffers and outputs the buffer; Frequency adjusting means for receiving a buffered external clock output from the clock buffer and increasing a frequency of the internal clock; Clock selection means for selecting the buffered external clock or the internal clock output from the frequency adjusting means and outputting the internal clock according to a state of a high frequency test mode entry signal; Clock frequency dividing means for outputting a data clock signal for controlling data at one cycle of the clock according to a logical combination of the internal master clock and a power-up signal applied from the clock selecting means; And And input data control means for controlling the data according to a logical combination of the data clock signal and the data pattern selection signal and outputting the data to a global input line. The method of claim 5, wherein the clock selection means, A first switching unit which is turned on when the high frequency test mode entry signal is enabled and outputs the internal clock applied from the clock period divider as the internal master clock signal; And a second switching unit which is turned on when the high frequency test mode entry signal is disabled and outputs the buffered external clock applied from the clock buffer as the internal master clock signal. The method of claim 6, wherein the first switching unit, Receiving the high frequency test mode entry signal through a PMOS transistor and the inverted high frequency test mode entry signal through an NMOS transistor, and outputs the buffered external clock as the internal master clock signal as it is. High frequency test device, characterized in that the transmission gate The method of claim 6, wherein the second switching unit, Receives the high frequency test mode entry signal through an NMOS transistor and the inverted high frequency test mode entry signal through a PMOS transistor, and transmits the buffered internal clock as the internal master clock signal according to the state of the signal. High frequency test device, characterized in that the gate. delete The method of claim 5, wherein the clock frequency dividing means, A logic operation unit for performing a logic operation on the internal master clock and the power-up signal applied from the clock selecting means, and outputting a control signal; A pull-up unit selectively turned on according to the power-up signal; And switching means for selectively outputting an output signal applied from the pull-up unit according to the control signal. The method of claim 10, The logic unit is a high frequency test device, characterized in that the NAND gate. The method of claim 10, The pull-up unit is a high frequency test device, characterized in that the PMOS transistor. The method of claim 10, wherein the switching means, A first switching unit turned on by the control signal applied from the logic operation unit and inverting and outputting the power up signal; A second switching unit outputting the power-up signal turned on and inverted by the control signal; A third switching unit outputting a signal applied from the second transmission gate when the control signal inverted from the logic operation unit is input; And And a fourth switching unit which receives a feedback input to the third switching unit when the inverted control signal is input from the logic operation unit, and inverts and outputs the first switching unit. The method of claim 13, The switching means is a high frequency test device, characterized in that the transmission gate. The method of claim 5, wherein the input data control means A data input buffer for receiving the data and buffering the data; A logic operation unit configured to logically operate the data clock signal and the data pattern selection signal applied from the clock frequency dividing unit and output a control signal; And And a control means for inverting the data applied from the data input buffer and outputting the data applied from the data input buffer to the global input line as it is, according to a control signal applied from the logic operation unit. The method of claim 15, The logic unit is a high frequency test device, characterized in that the NAND gate. The method of claim 15, wherein the control means, A first transfer gate turned on when the control signal applied from the logic operation unit is high to output a data inversion signal applied from the data input buffer to the global input line; And And a second transmission gate which is turned on when the control signal applied from the logic operation unit is low and outputs data applied from the data input buffer to the global input line as it is. The method of claim 5, wherein The frequency control means is a high frequency test device, characterized in that the phase-locked loop (phase-locked loop). The method of claim 5, wherein The frequency control means is a high frequency test device, characterized in that the delay-locked loop (delay-locked loop). The method of claim 5, wherein And the frequency adjusting means is a clock period divider.