KR100370168B1 - Circuit for Precharging Bit Line - Google Patents

Abstract

The present invention relates to a bit line precharge circuit having improved response characteristics and a stable output voltage. The present invention provides a first voltage divider for dividing VDL by half and an output signal of the first voltage divider for input. A second voltage divider for dividing and outputting by 1/2, a comparison voltage generator for generating and outputting a comparison voltage, and an output signal of the second voltage divider as an input and comparing the bit line precharge voltage to a comparison voltage. An output driver using a differential amplifier for controlling a voltage, a precharge controller for controlling a precharge operation of the output driver to be quickly responded, a current supply compensating a level of the bitline precharge voltage, and the bitline precharge voltage Characterized in that it comprises a leakage circuit for shorting the rise of.

Description

Bit Line Precharge Circuitry {Circuit for Precharging Bit Line}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuits, and more particularly to bit line precharge circuits having improved response characteristics and stable output voltages.

Hereinafter, a bit line precharge circuit according to the prior art will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a conventional bit line precharge circuit.

As shown in FIG. 1, the bit line precharge circuit includes a voltage divider 11 including a plurality of PMOSs, resistors, and capacitors, a current mirror 12, a first PMOS driver PM1, It consists of a response section composed of the first NMOS driver NM1.

First, in the voltage divider 11, four PMOSs are connected in series between the VDL voltage unit VDL and the ground terminal VSS, and two resistors are connected between the PMOSs.

The response unit may include a first PMOS driver PM1 connected in series between a VDL voltage unit VDL and a ground terminal VSS, and having a first node N1 and a second node N2 connected to each other as a gate. One NMOS driver NM1 and a current mirror 12 composed of two PMOS and NMOS, respectively.

Here, when the bit line precharge voltage VBLR is lower than the half VDL voltage of the voltage divider, Vgsn2 of the current mirror 12 is increased to increase the current to the second NMOS NM2 so that the first node is increased. The voltage at (N2) is lowered.

Accordingly, since the first PMOS driver PM1 is turned on to inject current, the bit line precharge voltage VBLR of the output terminal is increased.

On the contrary, when the bit line precharge voltage VBLR is higher than the half VDL voltage of the voltage divider 11, the current increases to the second PMOS PM2 of the current mirror 12, so that the second node N2 is increased. Increases the voltage.

Therefore, since the first NMOS driver NM1 is turned on to draw current to the ground terminal, the bit line precharge voltage VBLR is lowered.

However, the conventional bit line precharge circuit as described above has the following problems.

If a large current draw occurs during bit line precharging, the response characteristic of the current mirror is slowed down.

In addition, a change in the bit line precharge voltage level occurs according to the voltage change of the PMOS and the NMOS of the current mirror.

Disclosure of Invention The present invention has been made to solve the above-described problems, and an object thereof is to provide a bit line precharge circuit having an improved response characteristic and a stable output voltage by using an output driver having a differential amplifier.

1 is a circuit diagram illustrating a conventional bit line precharge circuit.

2 is a circuit diagram illustrating a bit line precharge circuit according to the present invention.

Explanation of symbols for the main parts of drawings

21: first voltage divider 22: second voltage divider

23: output driver 24: precharge control unit

25: comparison voltage generator 26: current supply unit

27: leakage circuit

In order to achieve the above object, the bit line precharge circuit according to the present invention receives a first voltage divider for dividing VDL by half and an output signal of the first voltage divider as an input and divides it back to half. And a second voltage divider for outputting the signal, a comparison voltage generator for generating and outputting a comparison voltage, and a differential amplifier receiving the output signal of the second voltage divider as an input and comparing the comparison voltage to a bit line precharge voltage. An output driver using a second power source, a precharge control unit controlling the precharge operation of the output driver to respond quickly, a current supply unit compensating the level of the bit line precharge voltage, and a rise of the bit line precharge voltage. Characterized in that it comprises a ground fault.

Hereinafter, a bit line precharge circuit of the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating a bit line precharge circuit according to the present invention.

As shown in FIG. 2, the bit line precharge circuit includes a first voltage divider 21 for dividing VDL, which is a high level bit line precharge voltage, by half, and the first voltage divider 21. A second voltage divider 22 which receives the output signal BLR of the input signal and divides it into 1/2 again and outputs it, a comparison voltage generator 25 which generates and outputs a comparison voltage, and the second voltage share An output driver 23 using a differential amplifier that receives the output signal HBLR of the allocation unit 22 as an input and outputs the bit line precharge voltage VBLR in comparison with the comparison voltage, and the precharge of the output driver 23. A precharge control unit 24 for controlling the operation to respond quickly; a current supply unit 26 for compensating the level of the bit line precharge voltage VBLR; and a rise of the bit line precharge voltage VBLR. The earth leakage part 27 is comprised.

First, the first voltage divider 21 includes tenth and eleventh PMOS PM10 and PM11, two resistors, and a twelfth and thirteenth PMOS PM12 between the VDL voltage unit VDL and the ground terminal VSS. (PM13) is connected in series and outputs a BLR that divides the bitline precharge voltage by half between two resistors.

The gates of the tenth and thirteenth PMOS PM10 and PM13 are connected to an inverted VDL, and the gates of the eleventh and twelfth PMOS PM11 and PM12 are connected to a resistor and a ground terminal VSS, respectively. .

The second voltage divider 22 includes a third PMOS PM3 and a fourth PMOS PM4 connected in series, and the third PMOS PM3 is disposed between the resistors of the first voltage divider 21. The gate is connected between the fourth PMOS PM4.

The fourth PMOS PM4 is connected to the ground terminal VSS, and the ground terminal VSS is connected to the gate.

Here, the third and fourth PMOS PM3 and PM4 use a diode-type PMOS.

The output driver 23 has a differential amplifier form consisting of fifth and sixth PMOS PM5 and PM6 and third and fourth NMOS NM3 and NM4.

Here, the fifth PMOS PM5 is connected to the external power supply VDD and the third NMOS NM3, and the gate is connected to the gate of the sixth PMOS PM6.

The sixth PMOS PM6 is connected to an external power supply VDD and a fourth NMOS NM4.

The third NMOS NM3 is connected to the fourth NMOS NM4, and a gate thereof is connected between the third and fourth PMOS PM3 PM4 of the second voltage divider 22.

The precharge control unit 24 is connected to the third NMOS NM3 and has a fifth NMOS NM5 to which a precharge operation signal PRE is applied as a gate, the fifth NMOS NM5 and the ground terminal VSS. The sixth NMOS NM6 connected to the gate of the seventh NMOS NM7 and the seventh NMOS NM7 connected to the fourth NMOS NM4 and the ground terminal VSS.

The current supply unit 26 and the comparison voltage generator 25 are configured by connecting the seventh, eighth, and ninth PMOS PM7, PM8, and PM9 in series between the external power supply VDD and the ground terminal VSS. .

The seventh PMOS PM7 of the current supply unit 26 is connected to an external voltage VDD and a gate is connected between the fifth PMOS PM5 and the third NMOS NM3.

The eighth PMOS PM8 of the comparison voltage generator 25 is connected to a seventh PMOS PM7 and a ninth PMOS PM9 and a gate thereof is connected to a gate of the fourth NMOS NM4.

In addition, a ninth PMOS PM9 is connected to a ground terminal VSS, and the ground terminal VSS is connected to a gate.

The earth leakage part 27 has eighth and ninth NMOS NM8 and NM9 connected in series between a precharge voltage output terminal connected to a seventh PMOS PM7 and an eighth PMOS PM8 and a ground terminal VSS. An external power supply VDD and a precharge signal PRE are connected to each gate.

The operation of the bit line precharge circuit according to the present invention configured as described above is as follows.

The BLR divided in half by the first voltage divider 21 is further divided in half through the second voltage divider 22 to obtain HBLR.

The output driver 23 outputs the bit line precharge voltage VBLR by comparing the HBLR as an input voltage with a comparison voltage which is an output signal of the comparison voltage generator 25.

Here, when the bit line precharge voltage VBLR is lower than the level of the comparison voltage, the current increases to the third NMOS NM3 of the output driver 23, so that the level of the node N3 falls.

Therefore, the seventh PMOS PM7 of the current supply unit 26 is operated to compensate for the bit line precharge voltage VBLR.

At this time, the precharge control unit 24 turns on the fifth and sixth NMOS (NM5) and NM6 to respond quickly in the precharge operation to improve the response characteristics, and to reduce the current consumption during other operations. Only 7 NMOS (NM7) is turned on.

On the contrary, when the bit line precharge voltage VBLR is higher than the level of the comparison voltage, the eighth and ninth NMOS NM8 and NM9 of the ground fault unit 27 may be configured to have the bit line precharge voltage VBLR. Short the rise.

The bit line precharge circuit of the present invention as described above has the following effects.

In other words, by using an output driver with a differential amplifier, it is possible to minimize the variation of the half VDL level and provide a fast response to the variation of the level of the bit line precharge voltage.

Claims (3)

A first voltage divider for dividing the VDL by one half; A second voltage divider which receives the output signal of the first voltage divider as an input and divides the output signal into 1/2 again; A comparison voltage generator for generating and outputting a comparison voltage; An output driver using a differential amplifier that receives the output signal of the second voltage divider as an input and compares the comparison voltage with a comparison voltage to control a bit line precharge voltage; A precharge controller for controlling a precharge operation of the output driver to be quickly responded; A current supply compensating the level of the bit line precharge voltage; And an earth leakage part for leakage of a rise of the bit line precharge voltage. 4. The output driver of claim 1, wherein the output driver comprises: a fifth PMOS connected to an external power source and a third NMOS, the gate of which is connected to a gate of a sixth PMOS, a sixth PMOS connected to an external power source and a fourth NMOS, and a fourth A third NMOS connected to an NMOS and a fifth PMOS, and a gate connected between the third and fourth PMOSs of the second voltage divider; and an eighth PMOS connected to the sixth and third NMOSs; And a fourth NMOS connected to the bit line precharge circuit. The bit line free circuit according to claim 1, wherein the ground fault unit is configured in series between the precharge voltage output terminal and the ground terminal, and includes eighth and ninth NMOS connected to an external power supply and a precharge signal to each gate. Charge circuit.