KR100358007B1 - Synchronization acquisiting apparatus for use in a cdma system - Google Patents

Abstract

The present invention relates to a synchronization acquisition apparatus for a wideband code division multiple access system, and an object of the present invention is to shorten the synchronization acquisition time by minimizing one integration time as much as possible. To this end, the present invention uses the parallel buffer module 30 to shift and store the serial PN code sequence generated by the PN code generator 20, and then output in parallel, and parallel matching type correlator 50 The PN code sequence is matched with the spread spectrum data received in step C).

Therefore, since the total integration section output of the spread spectrum data and the PN code is generated every chip time, the time for detecting the position of the spread spectrum data whose phase of the spread spectrum data and the PN code coincide can be significantly shortened.

Description

SYNCHRONIZATION ACQUISITING APPARATUS FOR USE IN A CDMA SYSTEM}

According to the present invention, a mobile station or base station receives a spread spectrum signal transmitted through a pilot channel from a base station or a terminal of a broadband code division multiple access (CDMA) mobile communication system. The present invention relates to a synchronization acquisition device for finding synchronization, and more particularly, to a synchronization acquisition device capable of shortening the overall synchronization acquisition time by reducing one integration time.

In general, finding the correct synchronization in a wideband CDMA mobile communication system is an important factor in determining the performance of the system. Therefore, the communication method in the wideband CDMA mobile communication system has many differences from the general communication method. Among them, the method of spreading the signal is spread much wider than the frequency band of the original signal during modulation.

Accordingly, if the spreading signal at the receiving end is not despread to the original narrow band, since the information to be transmitted at the transmitting end is not properly transmitted, it does not have any meaning, so the receiving end must despread the spreading signal at the time of transmission. do. To this end, the following two prerequisites must first be established, firstly the pattern of the PN code used to spread the signal during transmission must match the code used at the receiving end, and secondly, The PN code is to be synchronized with the PN code included in the received signal. That is, the receiver can recover data by synchronizing the PN code only when the PN code patterns generated by the transceiver are identical.

In addition, the synchronization process is basically divided into two parts, the initial synchronization acquisition process and the synchronization tracking process, and the method of selection is different depending on the required characteristics. That is, a method of preventing the PN synchronization from deviating by more than one chip when despreading the band by using the same code used to spread the band at the reception side is an initial synchronization acquisition process. After the process, the synchronization tracking process is to adjust the reference signal of the receiver so that the PN code pattern used by the transmitter does not differ by more than one chip.

Herein, a detailed description of the conventional initial synchronization acquisition process is as follows. That is, the transmitting end of the wideband CDMA mobile communication system transmits the first PN code string through a pilot channel, and the receiving end of the wideband CDMA mobile communication system generates a second PN code string identical to the PN code string generated from the transmitting end, and then sets Phase is compared with the first PN code sequence received through the PN code sequence. At this time, the phase comparison method detects a correlation value of the first PN code string and the second PN code string in each phase while comparing the phase of the second PN code string generated at the receiving end by one chip unit, and compares the received values from the pilot channel. The first PN code sequence and the second PN code sequence are searched for the phase where the correlation value is highest. Here, the position where the correlation value between the first PN code string and the second PN code string is highest is the phase synchronization.

Subsequently, when the search process for the phase in which the correlation value between the first PN code string and the second PN code string received from the pilot channel is the highest is completed, the second PN code string is maintained.

However, in the above-described synchronous acquisition method of the prior art, the largest part of the search time for synchronous acquisition is the integral time of the correlator, and this integral time is required by the chip times the chip clock T _c in calculation. Do. If the size of the search window is assumed to be N, at least N × T _c is required even if ideally, P _d (detection probability) is 1 and P _fa (false alarm probability) is 0. In other words, this time is a decisive factor in the acquisition time. Therefore, it is desirable to reduce the integration time for faster synchronization acquisition.

Therefore, an object of the present invention is to provide a synchronization acquisition apparatus capable of shortening the overall synchronization acquisition time by reducing an integration time for synchronization acquisition of a received signal of a CDMA system. .

In the wideband code division multiple access system according to the present invention for achieving the above object, an apparatus for synchronizing a received signal includes: a PN code generator for generating a serial PN code sequence having PN_I and PN_Q codes; A PN buffer module for shifting and storing PN code sequences of PN_I and PN_Q generated from the PN code generator and outputting PN codes of PN_I and PN_Q stored in parallel, respectively; Correlation of the spread spectrum I and Q data input through the pilot channel and the PN code sequences of PN_I and PN_Q in parallel output from the PN buffer are performed one to one for each Tc clock to generate a correlation result of the I and Q components. A parallel matching filter correlator; A sum of squares circuit for obtaining a sum of squares of the correlation result of the I and Q components generated by the parallel matching filter correlator; And a maximum value / position detector for detecting a position of the spread spectrum data that best matches the phase of the PN code sequence using the maximum value in the output of the sum-of-square circuit.

1 is a schematic block diagram of an apparatus for synchronous acquisition of a received signal of a code division multiple access system constructed in accordance with the present invention;

FIG. 2 is a diagram showing a detailed configuration of the PN buffer module shown in FIG. 1;

3 is a diagram showing a detailed configuration of the parallel matching correlator shown in FIG. 1;

4 is a diagram showing a detailed configuration of the parallel adder shown in FIG. 3;

5 is a diagram showing a detailed configuration of the sum-square circuit shown in FIG. 1;

FIG. 6 is a diagram showing a detailed configuration of the parallel matching correlator shown in FIG. 1;

<Description of the symbols for the main parts of the drawings>

10: receiver 20: PN code generator

30: PN buffer module 50: parallel matching correlator

70: sum of squares circuit 80: position detector

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, to aid understanding of the present invention, assuming that the PN code length is N, the probability of first finding a position where the phase coincides between the PN code sequence and the received spread spectrum data is 1 / N, and the second time. The probability of getting one will be 1 / N, and likewise, the last chance to find it will be 1 / N. In other words, the search time for acquisition can be thought of as follows.

In Equation 1, T_acq represents a synchronization acquisition time, Represents one integration time for the acquisition.

As can be seen from Equation 1, since N is a fixed value as the detection probability, It can be seen that reducing the time can be a way to reduce the search time for synchronization acquisition.

Conventionally, in the prior art, the received signal is correlated with the PN code sequence by one chip and then integrated. However, the present invention is configured to generate the entire output of the integral section at the time of one chip by using the buffer sufficiently. A matching filter with parallelism as much as the integration period is used.

The present invention is a device for the synchronization acquisition of the received signal of the CDMA system applying the above concept is implemented as shown in FIG. The synchronization acquisition device of FIG. 1 includes a receiver 10, a PN code generator 20, a PN buffer module 30, a parallel matched correlator 50, a square sum circuit 70, and a position detector 80. ).

The spread spectrum signal transmitted over the pilot channel is provided to the receiver 10 via an antenna. Receiver 10 frequency downconverts the spread spectrum signal and provides the downconverted I and Q spread spectrum data to parallel matching correlator 50.

The PN code generator 20 has a linear feedback shift register composed of M stage registers and logic gates, and according to an initial value provided from the illustrated control means, a PN code sequence of PN_I and PN_Q consisting of M bits, e.g., 256 bits. Create The PN code sequence is a recursive code signal having the same code as the code used to spread the information signal in the transmitter, and is repeatedly generated randomly in group units. The serial code sequence of the PN_I and PN_Q codes generated by the PN code generator 20 is provided to the PN buffer module 30.

The PN buffer module 30 is composed of a pair of shift registers 32 and 34 having M buffers, i.e., 256 buffer cells equal to the number of chips of a PN code sequence, as shown in detail in FIG. The first and second shift registers 32 and 34 sequentially shift and store PN_I and PN_Q of the PN code sequence provided in series from the PN code generator 20 to the right in every Tc clock. PN codes of PN_I and PN_Q are output to the next parallel matching correlator 50 in parallel.

The parallel matching correlator 50 matches spread spectrum data of the same length with 256 chips of PN code sequence output in parallel from the PN buffer module 30 every Tc clock, thereby spreading the spectrum having the same phase as the PN code sequence. Perform an operation to find the location of data. As shown in detail in FIG. 3, the parallel matching correlator 50 includes a first correlator unit 55, a second correlator unit 65, and first and second correlator units 55 and 65. It consists of a multiplexer 58 for selectively outputting the output of and a parallel adder module 60 for adding the output of the multiplexer.

The first and second correlator sections 55 and 65 are composed of shift registers 52 and 62, latch sections 54 and 64 and multipliers 56 and 66, respectively. The shift register 52 of the first correlator section 55 sequentially shifts and stores I data of spread spectrum data provided from the receiver 10 at every Tc clock, and the latch section 54 stores the PN buffer module 30. Latch and store the parallel 256 chips PN_I code provided from &quot; The multiplier 56 multiplies the I data stored in the shift register 52 and the latch unit 54 with the PN_I code by chip every Tc clock, and outputs the multiplied result to the multiplexer 58. Similarly, the shift register 62 of the second component correlator section 65 sequentially shifts and stores the Q data of the spread spectrum data provided from the receiver 10 every Tc clock, and the latch section 64 stores the shift register. The PN_Q code of 256 chips in parallel provided from the 62 and the PN buffer module 30 is latched and stored. The Q data and the PN_Q code stored in the shift register 62 and the latch unit 64 are multiplied by the multiplier 66 in units of chips every Tc clock and output to the multiplexer 58 of the next stage.

The multiplexer 58 divides the result value multiplied by the chip unit in each of the multipliers 56 and 66 into I and Q components for each Tc clock and selectively provides the result with a parallel adder. In other words, the multiplexer 58 alternately outputs the I component value and Q component value multiplied every Tc clock to the parallel adder module 60.

The parallel adder module 60 adds 256 I and Q component values multiplied by the multipliers 56 and 66 in the parallel matching correlator 50 and outputs the summed result at every Tc clock. Do this. Parallel adder 60 is a multi-stage group of adders comprised of a pair of two-input adders and one two-input adder that receives the output of these two-input adders as input, as shown in detail in FIG. 1, 60-2, 60-3, 60-4). More specifically, the result values multiplied by the respective multipliers 56 and 66 of the PN_I and PN_Q correlator sections 55 and 65 are applied to the two-input adders in pairs, respectively, and the outputs of these two-input adders It is again applied to the input of the two-input adder, and the output of these two-input adders is again provided to the input of the two-input adder, and finally through the adder stages 60-1 to 60-4, respectively. The multiplication result of the I component and the Q component of the multipliers 56 and 66 generates a summed value. Therefore, the final adder stage 60-4 of the parallel adder module 60 alternately outputs the sum of the correlated I component and Q component of the spread spectrum data and the PN code sequence every Tc clock. The I component and Q component outputs summed by the parallel adder module 60 are provided to the next sum square square circuit 70.

The square sum circuit 70 squares the I component sum values and the Q component sum values provided from the parallel adder module 60 to obtain the magnitude values by integrating the I component sum values and the Q component sum values. Perform the function to find the sum. This square sum circuit 70 is comprised of a squarer 74 and a summer 76 that sums the outputs of the squarer, as shown in more detail in FIG.

If the squarer 74 squares each of the I component sum values and the Q component sum values as they are, the number of output bits is twice the number of bits of the input I component sum value and the Q component sum value. The size of summer 76 is increased. To prevent this, the present invention further includes an absolute value circuit 72 disposed in front of the squarer 74 to reduce the size of the input bit. The absolute value circuit 72 checks the sign of the sign bit in the input bit and, if there is a sign, performs a two's complement operation on the input bit to reduce the input bit by one bit. Therefore, the squarer 74 alternately squares the data of each of the I component sum values and the Q component sum values, which are two's complement calculations by the absolute value circuit 72. The squared I and Q squared results at squarer 74 are provided to summer 76.

Summer 76 first stores the squared value for the I component squared result, and then, when the squared value for the Q component signal is provided in accordance with the selection operation of multiplexer 78 according to the selection signal " 0 " The squared values of these I and Q components are summed to provide the summed result to the position detector 80 of the next stage.

The position detector 80 detects the largest value among the outputs of the sum-square circuit 70 provided every Tc clock and the position of the spread spectrum signal accompanying the value. The detected position is a position at which the received spread spectrum signal is synchronized with the PN code generated by the PN code generator 20. As shown in more detail in FIG. 6, the position detector 80 for detecting the synchronous position includes a sum of squares / position updater 90 and a maximum value / position latch 96 connected to the counter 88 and the output of the counter. ), A comparator 84 and a counter 88.

The sum of squares / position updater 90 stores the position of storing the current position of the spread spectrum data corresponding to the sum of squares of the sum of squares storage 82 and the sum of squares circuit 70 temporarily storing the sum of squares output from the sum of squares circuit 70. It is comprised by the part 92. The maximum value / position latch section 96 stores a maximum value storage section 86 for storing the maximum value of the output of the square sum circuit 70 and a spread spectrum data corresponding to the maximum value stored in the maximum value storage section 86. It consists of a maximum position storage 94 for storing the position.

On the other hand, the counter 88 has a bit length corresponding to the length of the PN code sequence generated by the PN code generator 20, and a parallel matching type correlator at that time as a count value that is incremented by one according to every Tc clock. Generate a position of spread spectrum data that matches with the PN code sequence at 50. The value counted by the counter 88, that is, the current position of the spread spectrum data, is temporarily stored in the position storage 92 of the sum of squares / position updater 90.

The comparator 86 compares whether the current sum of squares input from the sum-square circuit 70 is greater than or less than the maximum value stored in the maximum value storage section 84 of the maximum value / position latch section 96, and the current input value is If larger than the stored maximum value, the update enable signal 85 is provided to the sum of squares / position updater 90 via line 85. In response to the update enable signal, the square sum storage unit 82 provides the maximum sum stored in the maximum value / position latch unit 96 as the maximum value to the maximum value storage unit 84 of the maximum value / position latch unit 96 as a new maximum value. It will be updated and stored as the maximum value. Correspondingly, the sum of squares / position update unit 90 uses the current position value of the spread spectrum data stored in the position storage unit 92 as the updated position value and the maximum position storage unit 94 of the maximum value / position latch unit 96. ) To be stored.

However, as a result of the comparison in the comparator 86, if the current input value is smaller than the stored maximum value, the sum of squares / position update unit 90 will not perform any update operation, and therefore, the maximum value / position latch unit 96 The maximum value and position stored in) will be used as the reference value when the next sum of squares value is entered.

The above-described process is repeated until the Tc clock of the period corresponding to the number of 256 chips is finished. Finally, the maximum value storage unit 84 and the maximum position storage unit 94 of the maximum value / position latch unit 96 are stored. The maximum value and the corresponding position are those at which the phase of the received spread spectrum signal and the PN code sequence match best.

Therefore, according to the present invention, the output of the entire integrated section of the spread spectrum data and the PN code is generated every chip time, so that the time for detecting the position of the spread spectrum data whose phase between the spread spectrum data and the PN code is substantially shortened is significantly shortened. Can be.

Claims (5)

A synchronization acquisition device for finding synchronization of a received signal in a wideband code division multiple access system, A PN code generator for generating a serial PN code sequence having PN_I and PN_Q codes; A PN buffer module for shifting and storing PN code sequences of PN_I and PN_Q generated from the PN code generator and outputting PN codes of PN_I and PN_Q stored in parallel, respectively; Correlation of the spread spectrum I and Q data input through the pilot channel and the PN code sequences of PN_I and PN_Q in parallel output from the PN buffer are performed one to one for each Tc clock to generate a correlation result of the I and Q components. A parallel matching filter correlator; A sum of squares circuit for obtaining a sum of squares of the correlation result of the I and Q components generated by the parallel matching filter correlator; And a maximum value / position detector for detecting a position of the spread spectrum data that best matches a phase of the PN code sequence using the maximum value of the output of the sum-square circuit. Acquisition device for synchronization of received signal. The method of claim 1, wherein the parallel matched correlator is: A first shift register for sequentially shifting and storing the I data of the spread spectrum data every Tc clock; a first latch unit for latching and storing parallel PN_I codes provided from the PN buffer module; and the first shift register; And a first correlator unit configured to multiply the I data stored in the first latch unit and the PN_I code by chips every Tc clock. A second shift register for sequentially shifting and storing the Q data of the spread spectrum data every Tc clock, a second latch unit for latching and storing parallel PN_Q codes provided from the PN buffer module, and the second shift register; And a second correlator unit configured to multiply the Q data stored in the second latch unit and the PN_Q code by chip every Tc clock. A multiplexer configured to alternately output the result values multiplied by the chip unit in each of the first and second multipliers by I and Q components every Tc clock; And a parallel adder for summing the alternating I and Q component outputs of the multiplexer for each Tc clock and outputting the summed result, wherein the received signal is synchronized in a wideband code division multiple access system. The circuit of claim 2 wherein the sum of squares circuit is: A squared step of squaring each of the I and Q component sum outputs summed from the parallel adder module; And a summation unit for generating summed outputs by summing respective I and Q squared results generated by the squarer. 4. The circuit of claim 3, wherein the sum of squares circuit is: Further comprising an absolute value circuit performing a two's complement operation on each of the I and Q component sum outputs added from the parallel adder module to reduce the number of bits of each of the I and Q component sum outputs to provide the squarer. A synchronization acquisition device for a received signal in a wideband code division multiple access system, characterized in that. The apparatus of claim 2, wherein the position detector comprises: The diffusion having a bit length corresponding to the length of the PN code sequence generated by the PN code generator and being incremented by one according to every Tc clock and matching with the PN code sequence in a parallel matching correlator at that time. A counter for generating a location of spectral data; A comparator for comparing the magnitude of the sum of squares provided from the sum of square circuits with a reference sum of squares; A spread spectrum including a maximum sum value of a square sum storage unit for updating and storing a maximum value of the sum of squares and a reference square sum as the reference sum of squares according to a comparison result of the comparator, and the current position of the spread spectrum data counted by the counter And a maximum value / position updater configured as a position storage unit for updating and storing the position of data.