KR100355875B1 - Method for forming shallow trench isolation by silicon nitride wet etching - Google Patents
Method for forming shallow trench isolation by silicon nitride wet etching Download PDFInfo
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- KR100355875B1 KR100355875B1 KR1019990068478A KR19990068478A KR100355875B1 KR 100355875 B1 KR100355875 B1 KR 100355875B1 KR 1019990068478 A KR1019990068478 A KR 1019990068478A KR 19990068478 A KR19990068478 A KR 19990068478A KR 100355875 B1 KR100355875 B1 KR 100355875B1
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- 238000001039 wet etching Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 16
- 238000002955 isolation Methods 0.000 title description 15
- 229910052581 Si3N4 Inorganic materials 0.000 title 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title 1
- 150000004767 nitrides Chemical class 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 238000000926 separation method Methods 0.000 claims abstract description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 238000009413 insulation Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 210000002268 wool Anatomy 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
본 발명의 반도체 소자 분리 방법은 반도체 기판(11) 상에 완충 산화막(12) 및 질화막(13)을 연속하여 적층하는 단계, 질화막(13) 상부에 형성된 감광막 패턴(14)을 마스크로 하여 질화막(13), 완충 산화막(12) 및 반도체 기판(11)을 식각하여 트렌치(T)를 형성하는 트렌치 형성단계, 감광막 패턴(14)을 제거하고, 질화막을 식각용액에 의해 습식 식각하여 완충 산화막(12)과 접해있는 질화막의 양모서리(EG)를 둥굴게 형성하는 질화막 식각 단계, 트렌치(T) 내부에 라이너 산화막(15)을 형성하는 단계, 트렌치(T)가 형성된 반도체 기판(11) 및 습식 식각하여 양모서리가 둥굴게 형성된 질화막(13a) 상부에 절연막(16)을 증착하고 식각하여 트렌치(T) 내부를 절연막(16)으로 채우는 트렌치 절연막 패턴(16a)을 형성하는 단계, 질화막(13a)이 노출될 때까지 트렌치 절연막 패턴(16a)을 연마하는 단계 및 질화막(13a)을 식각하여 제거하는 단계로 구성된다.In the semiconductor device separation method of the present invention, the buffer oxide film 12 and the nitride film 13 are sequentially stacked on the semiconductor substrate 11, and the nitride film (14) is formed using the photosensitive film pattern 14 formed on the nitride film 13 as a mask. 13), the trench forming step of etching the buffer oxide film 12 and the semiconductor substrate 11 to form the trench T, removing the photoresist pattern 14, and wet etching the nitride film with an etching solution to buffer the oxide film 12. ), The nitride film etching step of forming the both edges (EG) of the nitride film in contact with each other, the step of forming a liner oxide film 15 in the trench (T), the semiconductor substrate 11 having the trench (T) and wet etching To form a trench insulating pattern 16a filling the trench T with the insulating film 16 by depositing and etching the insulating film 16 on the nitride film 13a having both edges rounded. The trench insulating film pattern 16a is exposed until exposed. Polishing and removing the nitride film 13a by etching.
본 발명은 트렌치의 가장자리에 형성된 라이너 산화막의 두께가 얇아지는 것을 방지할 수 있고, 가장자리의 형상을 개선하여 게이트 산화막 집적도의 특성 향상 및 누설전류의 발생을 방지할 수 있다.The present invention can prevent the thickness of the liner oxide film formed at the edge of the trench from thinning, and improve the shape of the edge to prevent the improvement of the characteristics of the gate oxide film density and generation of leakage current.
Description
본 발명은 반도체 소자 분리 방법에 관한 것으로, 특히 반도체 기판 표면에 트렌치를 형성하여 반도체 소자를 분리하는 반도체 소자 분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for separating semiconductor devices, and more particularly, to a method for separating semiconductor devices by forming trenches on a semiconductor substrate surface.
일반적으로 반도체 소자 분리 방법은 질화막을 이용하여 국부 산화막 형성(Local Oxidation of Silicon:LOCOS) 방법과 반도체 기판 표면에 트렌치(Trench)를 형성하여 소자를 분리하는 트렌치 소자 분리 방법이 있다.In general, a semiconductor device isolation method includes a local oxide formation (LOCOS) method using a nitride film and a trench device isolation method for forming a trench on a surface of a semiconductor substrate to separate devices.
국부 산화막 형성 방법은 질화막을 마스크로 해서 반도체 기판 자체를 열산화시키기 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 우수한 장점이 있으나 소자 분리 영역이 차지하는 면적이 크므로 미세화에 한계가 있다. 이에 반해 트렌치 소자 분리 방법은 반도체 기판 표면에 트렌치를 형성하여 절연막을 채운 후 평탄화하는 방법으로 소자 분리 영역이 차지하는 면적을 작게 형성할 수 있어 미세화에 유리하다.The method of forming a local oxide film has the advantage that the process of thermally oxidizing the semiconductor substrate itself using a nitride film as a mask has a small element stress problem, and the resulting oxide film quality is excellent. There is. On the other hand, in the trench isolation method, a trench is formed on the surface of the semiconductor substrate to fill the insulating layer and then planarize to form an area occupied by the isolation region, which is advantageous for miniaturization.
도 1a 내지 도 1g는 종래의 반도체 기판 표면에 트렌치를 형성하여 반도체 소자 분리 방법을 위한 공정 순서를 도시한 단면도이다.1A to 1G are cross-sectional views illustrating a process sequence for a method of separating a semiconductor device by forming a trench on a surface of a conventional semiconductor substrate.
도 1a에 도시된 바와 같이 반도체 기판(1) 상에 100∼300Å 두께를 갖는 완충 산화막(PAD Oxide)(2)을 성장시키고, 완충 산화막(2) 상부에 1000∼3000Å 두께를 갖는 질화막(3)을 형성하고, 질화막(3) 상부에 감광막(4)을 도포하고, 마스크를 사용하여 반도체 기판(1) 표면에 소자 분리 영역인 트렌치를 형성하기 위해 감광막(4)을 노광 현상한다. 도 1b에 도시된 바와 같이 감광막(4)의 노광 현상에 의해 드러난 질화막(3) 및 완충 산화막(2)을 식각하여 제거하고, 다시 드러난 반도체 기판(1)을 3000∼7000Å의 깊이로 300∼500Å의 폭을 갖도록 식각하여 반도체 소자 분리 영역인 트렌치(T)를 형성한다. 도 1c에 도시된 바와 같이 트렌치(T)의 가장자리를 둥글리기(rounding) 위하여 트렌치(T) 내부에 라이너 산화막(5)을 형성한다. 라이너 산화막(5) 형성시 반도체 기판(1)의 표면의 결정방향은 <100>인데 반해 트렌치(T)의 식각 단면의 결정방향은 <110> 이므로 트렌치(T)의 가장자리의 라이너 산화막의 두께는 얇다. 도 1d에 도시된 바와 같이 트렌치(T)를 포함한 반도체 기판(1) 상부면에 화학 기상 증착법(Chemical Vapor Deposition:CVD)에 의해 산화막인 절연막(6)을 두껍게 증착하여 트렌치(T) 내부를 채운다. 도 1e에 도시된 바와 같이 절연막(6)이 형성된 반도체 기판(1) 상에 감광막을 도포한 후, 마스크를 사용하여 감광막을 노광 현상하여 트렌치(T) 상부의 절연막(6) 위에만 감광막 패턴(7)이 남도록 한다. 감광막 패턴(7)을 마스크로 하여 절연막(6)을 식각하여 트렌치 절연막 패턴(6a)을 형성한다. 도 1f에 도시된 바와 같이 감광막 패턴(7)을 제거하고, 기계 화학적 연마(Chemical Mechanical Polishing:CMP) 공정을 이용하여 질화막(3)이 있는데 까지 트렌치 절연막 패턴(6a)을 깍아내 평탄화하여 평탄화된 절연막 패턴(6b)을 형성한다. 도 1g에 도시된 바와 같이 노출된 질화막(3)을 습식 식각하여 제거한다.As shown in FIG. 1A, a buffer oxide film (PAD Oxide) 2 having a thickness of 100 to 300 GPa is grown on the semiconductor substrate 1, and a nitride film 3 having a thickness of 1000 to 3000 GPa is formed on the buffer oxide film 2. The photosensitive film 4 is formed on the nitride film 3, and the photosensitive film 4 is exposed and developed to form a trench, which is an isolation region, on the surface of the semiconductor substrate 1 using a mask. As illustrated in FIG. 1B, the nitride film 3 and the buffer oxide film 2 exposed by the exposure phenomenon of the photosensitive film 4 are etched and removed, and the exposed semiconductor substrate 1 is 300 to 500 kV at a depth of 3000 to 7000 Å. The trench T is etched to have a width of to form a semiconductor device isolation region. As shown in FIG. 1C, a liner oxide layer 5 is formed in the trench T to round the edge of the trench T. As shown in FIG. When the liner oxide film 5 is formed, the crystal direction of the surface of the semiconductor substrate 1 is <100>, whereas the crystal direction of the etching cross section of the trench T is <110>. Therefore, the thickness of the liner oxide film at the edge of the trench T is thin. As shown in FIG. 1D, an insulating film 6, which is an oxide film, is thickly deposited on the upper surface of the semiconductor substrate 1 including the trench T by chemical vapor deposition (CVD) to fill the inside of the trench (T). . As shown in FIG. 1E, after the photoresist film is applied onto the semiconductor substrate 1 on which the insulation film 6 is formed, the photoresist film is exposed and developed by using a mask to form the photoresist pattern only on the insulation film 6 above the trench T. 7) is left. Using the photosensitive film pattern 7 as a mask, the insulating film 6 is etched to form a trench insulating film pattern 6a. As shown in FIG. 1F, the photoresist layer pattern 7 is removed, and the trench insulation layer pattern 6a is scraped and planarized until there is a nitride layer 3 using a chemical mechanical polishing (CMP) process. The insulating film pattern 6b is formed. As shown in FIG. 1G, the exposed nitride layer 3 is removed by wet etching.
도 2는 종래의 반도체 소자 분리 방법에 따라 트렌치 형성 후 라이너 산화막의 취약한 부분을 나타낸 확대도이다. 도 2에 도시된 바와 같이 라이너 산화막(5) 형성시 반도체 기판(1)의 표면의 결정방향과 트렌치(T)의 식각 단면의 결정방향은 상이하므로 트렌치(T)의 가장자리(a)의 라이너 산화막의 두께는 얇다.2 is an enlarged view illustrating a weak portion of a liner oxide film after trench formation according to a conventional method of separating semiconductor devices. As shown in FIG. 2, when the liner oxide film 5 is formed, the crystal direction of the surface of the semiconductor substrate 1 and the crystal direction of the etched cross section of the trench T are different, so the liner oxide film of the edge a of the trench T is different. The thickness of is thin.
따라서 종래의 반도체 소자 분리 방법은 트렌치의 가장자리의 라이너 산화막의 두께는 얇게 형성되므로 트렌치 가장자리에서 누설전류(Leakage Current)가 발생될 수 있고, 후공정인 게이트 산화막 형성시 게이트 산화막의 두께는 얇게 형성되므로 트렌치의 가장자리에 얇은 두께를 갖는 라이너 산화막에 의해 게이트 산화막 집적도(Gate Oxide Integrity:GOI)의 특성의 저하를 가져오고, 이로 인해 반도체 소자의 신뢰성 및 특성이 열악해지는 문제점을 가지고 있다.Therefore, in the conventional semiconductor device isolation method, since the thickness of the liner oxide film at the edge of the trench is thin, leakage current may be generated at the edge of the trench, and the thickness of the gate oxide film is thin when the gate oxide film is formed later. Due to a thin liner oxide film on the edge of the trench, the gate oxide density (GOI) may be degraded, resulting in poor reliability and characteristics of the semiconductor device.
본 발명의 목적은 트렌치 가장자리의 라이너 산화막의 두께가 얇아지는 것을 방지하여 트렌치 가장자리의 둥글리기 형상을 개선하여 게이트 산화막 집적도의 특성 향상 및 누설전류의 발생을 방지할 수 있는 반도체 소자 분리 방법을 제공하는 데 있다.Disclosure of Invention An object of the present invention is to provide a semiconductor device isolation method capable of preventing the thickness of the liner oxide film at the trench edge from being thin and improving the roundness of the trench edge to improve the characteristics of gate oxide density and to prevent leakage current. There is.
도 1a 내지 도 1g는 종래의 반도체 소자 분리 방법을 위한 공정 순서를 도시한 단면도,1A to 1G are cross-sectional views illustrating a process sequence for a conventional semiconductor device isolation method;
도 2는 종래의 트렌치 형성 후 라이너 산화막의 취약한 부분을 나타낸 확대도,2 is an enlarged view showing a weak portion of a liner oxide film after forming a conventional trench;
도 3a 내지 도 3h는 본 발명의 반도체 소자 분리 방법을 위한 공정 순서를 도시한 단면도이다.3A to 3H are cross-sectional views illustrating a process sequence for a semiconductor device isolation method of the present invention.
상기의 목적을 달성하기 위하여 본 발명의 반도체 소자 분리 방법은 반도체 기판 상에 완충 산화막 및 질화막을 연속하여 적층하는 단계; 질화막 상부에 감광막을 도포하고, 마스크를 사용하여 트렌치를 형성하기 위해 감광막을 노광 현상하여 감광막 패턴을 형성하고, 감광막 패턴을 마스크로 하여 질화막, 완충 산화막 및 반도체 기판을 식각하여 트렌치를 형성하는 트렌치 형성단계; 감광막 패턴을 제거하고, 질화막을 식각용액에 의해 습식 식각하여 완충 산화막과 접해 있는 질화막의 양모서리를 둥굴게 형성하는 질화막 식각 단계; 트렌치 내부에 라이너 산화막을 형성하는 단계; 트렌치가 형성된 반도체 기판 및 습식 식각하여 양모서리가 둥굴게 형성된 질화막 상부에 절연막을 증착하고, 절연막을 식각하여 트렌치 내부를 절연막으로 채우는 트렌치 절연막 패턴을 형성하는 단계; 습식 식각하여 양모서리가 둥굴게 형성된 질화막이 노출될때 까지 트렌치 절연막 패턴을 연마하는 단계; 및 질화막을 식각하여 제거하는 단계를 구비한 것을 특징으로 한다.In order to achieve the above object, the semiconductor device isolation method of the present invention comprises the steps of: sequentially depositing a buffer oxide film and a nitride film on a semiconductor substrate; A trench is formed by applying a photoresist film over the nitride film and exposing and developing the photoresist film to form a trench using a mask, and etching the nitride film, the buffer oxide film, and the semiconductor substrate using the photoresist pattern as a mask to form a trench. step; A nitride film etching step of removing the photoresist pattern and wet etching the nitride film with an etching solution to form rounded corners of the nitride film in contact with the buffer oxide film; Forming a liner oxide film inside the trench; Depositing an insulating film on the trench-formed semiconductor substrate and a wet etching-etched nitride film having rounded both edges, and etching the insulating film to form a trench insulating film pattern filling the inside of the trench with the insulating film; Polishing the trench insulating pattern until the nitride film having the rounded corners is exposed by wet etching; And etching to remove the nitride film.
질화막 식각 단계에서 식각용액은 인산 용액이고, 식각용액의 온도는 120℃ 내지 180℃의 범위인 것을 특징으로 한다.The etching solution in the nitride film etching step is a phosphoric acid solution, the temperature of the etching solution is characterized in that the range of 120 ℃ to 180 ℃.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자 분리 방법을 상세히설명하고자 한다.Hereinafter, a semiconductor device isolation method of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3h는 본 발명의 반도체 소자 분리 방법을 위한 공정 순서를 도시한 단면도 이다.3A to 3H are cross-sectional views illustrating a process sequence for a semiconductor device isolation method of the present invention.
도 3a 내지 도 3h에 도시된 바와 같이 본 발명의 반도체 소자 분리 방법은 반도체 기판(11) 상에 완충 산화막(12) 및 질화막(13)을 연속하여 적층하는 단계,질화막(13) 상부에 감광막을 도포하고, 마스크를 사용하여 트렌치(T)를 형성하기 위해 감광막을 노광 현상하여 감광막 패턴(14)을 형성하고, 감광막 패턴(14)을 마스크로 하여 질화막(13), 완충 산화막(12) 및 반도체 기판(11)을 식각하여 트렌치(T)를 형성하는 트렌치 형성단계, 감광막 패턴(14)을 제거하고, 질화막을 식각용액에 의해 습식 식각하여 완충 산화막(12)과 접해 있는 질화막의 양모서리(EG)를 둥굴게 형성하는 질화막 식각 단계, 트렌치(T) 내부에 라이너 산화막(15)을 형성하는 단계, 트렌치(T)가 형성된 반도체 기판(11) 및 습식 식각하여 양모서리가 둥굴게 형성된 질화막(13a) 상부에 절연막(16)을 증착하고, 절연막(16)을 식각하여 트렌치(T) 내부를 절연막(16)으로 채우는 트렌치 절연막 패턴(16a)을 형성하는 단계, 습식 식각하여 양모서리가 둥굴게 형성된 질화막(13a)이 노출될 때까지 트렌치 절연막 패턴(16a)을 연마하는 단계 및 질화막(13a)을 식각하여 제거하는 단계로 구성된다.3A to 3H, a method of separating a semiconductor device according to an embodiment of the present invention comprises sequentially depositing a buffer oxide film 12 and a nitride film 13 on a semiconductor substrate 11, and forming a photoresist film on the nitride film 13. The photoresist film is exposed and developed to form a trench T using a mask to form a photoresist pattern 14, and the nitride film 13, the buffer oxide film 12, and the semiconductor are formed using the photoresist pattern 14 as a mask. The trench forming step of etching the substrate 11 to form the trench T, removing the photoresist pattern 14, and wet etching the nitride film with an etching solution to wet both edges of the nitride film contacting the buffer oxide film 12 (EG) ) Is formed by etching the nitride film, forming the liner oxide film 15 inside the trench T, the semiconductor substrate 11 having the trench T formed therein, and the nitride film 13a having the both edges formed by wet etching. The insulating film 16 on the And etching the insulating film 16 to form a trench insulating pattern 16a filling the inside of the trench T with the insulating film 16. The trench is wet-etched until the nitride film 13a having rounded corners is exposed. The insulating film pattern 16a is polished and the nitride film 13a is etched and removed.
질화막 식각 단계에서 식각용액은 인산 용액이고, 식각용액의 온도는 120℃ 내지 180℃의 범위인 것을 특징으로 한다.The etching solution in the nitride film etching step is a phosphoric acid solution, the temperature of the etching solution is characterized in that the range of 120 ℃ to 180 ℃.
상기의 구성에 따른 본 발명인 반도체 소자 분리 방법의 동작은 다음과 같다.Operation of the semiconductor device separation method of the present invention according to the above configuration is as follows.
도 3a에 도시된 바와 같이 반도체 기판(11) 상에 100∼300Å 두께를 갖는 완충 산화막(12)을 성장시키고, 완충 산화막(12) 상부에 1000∼3000Å 두께를 갖는 질화막(13)을 형성한다. 질화막(13) 상부에 감광막을 도포하고, 마스크를 사용하여 트렌치(T)를 형성하기 위해 감광막을 노광 현상하여 감광막 패턴(14)을 형성한다. 도 3b에 도시된 바와 같이 감광막 패턴(14)을 마스크로 하여 질화막(13), 완충 산화막(12) 및 반도체 기판(11)을 식각하여 트렌치(T)를 형성한다. 도 3c에 도시된 바와 같이 감광막 패턴(14)을 제거하고, 질화막을 120℃ 내지 180℃의 온도 범위의 식각용액인 인산 용액을 사용하여 습식 식각하여 완충 산화막(12)과 접해있는 질화막의 양모서리(EG)를 둥굴게 형성한다. 질화막의 습식 식각시 질화막의 식각 두께는 100Å 이하가 되도록 제어한다. 도 3d에 도시된 바와 같이 트렌치(T) 내부에 라이너 산화막(15)을 형성한다. 라이너 산화막(15) 형성시 트렌치(T)의 가장자리에 형성되는 라이너 산화막(TEG)은 종래에 비해 둥근 형상을 갖게 되어 가장자리 둥굴리기(Corner Rounding)를 향상시키 수 있다. 도 3e에 도시된 바와 같이 트렌치(T)가 형성된 반도체 기판(11) 및 습식 식각하여 양모서리가 둥굴게 형성된 질화막(13a) 상부에 산화막인 절연막(16)을 증착한다. 도 3f에 도시된 바와 같이 절연막(16)이 형성된 반도체 기판(11) 상에 감광막을 도포한 후, 마스크를 사용하여 감광막을 노광 현상하여 트렌치(T) 상부의 절연막(16) 위에만 감광막 패턴(17)이 남도록 하고, 감광막 패턴(17)을 마스크로 하여 절연막(16)을 식각하여 트렌치(T) 내부를 절연막(16)으로 채우는 트렌치 절연막 패턴(16a)을 형성한다. 도3g에 도시된 바와 같이 감광막 패턴(17)을 제거하고, 기계 화학적 연마(CMP) 공정을 이용하여 습식 식각하여 양모서리가 둥굴게 형성된 질화막(13a)이 노출될 때까지 트렌치 절연막 패턴(16a)을 평탄하게 연마하여 평탄화된 절연막 패턴(16b)을 형성한다. 도 3h에 도시된 바와 같이 노출된 질화막(13a)을 습식 식각하여 제거한다.As shown in FIG. 3A, a buffer oxide film 12 having a thickness of 100 to 300 GPa is grown on the semiconductor substrate 11, and a nitride film 13 having a thickness of 1000 to 3000 GPa is formed on the buffer oxide film 12. A photosensitive film is coated on the nitride film 13, and the photosensitive film is exposed and developed to form a trench T using a mask to form the photosensitive film pattern 14. As illustrated in FIG. 3B, the trench T is formed by etching the nitride film 13, the buffer oxide film 12, and the semiconductor substrate 11 using the photoresist pattern 14 as a mask. 3C, the photoresist pattern 14 is removed, and the nitride layer is wet-etched using a phosphoric acid solution, which is an etching solution in a temperature range of 120 ° C. to 180 ° C., so that the edges of the nitride layer in contact with the buffer oxide layer 12 are etched. (EG) is rounded off. During wet etching of the nitride film, the etching thickness of the nitride film is controlled to be 100 kPa or less. As shown in FIG. 3D, a liner oxide layer 15 is formed in the trench T. Referring to FIG. When the liner oxide layer 15 is formed, the liner oxide layer TEG formed at the edge of the trench T may have a rounded shape as compared with the conventional art, thereby improving edge rounding. As illustrated in FIG. 3E, an oxide insulating layer 16, which is an oxide film, is deposited on the semiconductor substrate 11 having the trench T formed thereon and wet etching to form a nitride film 13a having rounded corners. As shown in FIG. 3F, after the photoresist film is coated on the semiconductor substrate 11 on which the insulation film 16 is formed, the photoresist film is exposed and developed by using a mask to expose the photoresist pattern only on the insulation film 16 on the upper portion of the trench T. 17 is left, and the insulating film 16 is etched using the photoresist pattern 17 as a mask to form a trench insulating film pattern 16a that fills the trench T with the insulating film 16. As shown in FIG. 3G, the trench insulation layer pattern 16a is removed until the photoresist pattern 17 is removed and wet etched using a mechanical chemical polishing (CMP) process to expose the nitride film 13a having rounded wool edges. Is polished to form a flattened insulating film pattern 16b. As shown in FIG. 3H, the exposed nitride layer 13a is removed by wet etching.
본 발명의 반도체 소자 분리 방법은 트렌치의 가장자리에 형성된 라이너 산화막의 두께가 얇아지는 것을 방지할 수 있고, 가장자리의 형상을 개선하여 게이트 산화막 집적도의 특성 향상 및 누설전류의 발생을 방지하여 반도체 소자의 신뢰성 및 특성을 향상시킬 수 있다.The semiconductor device isolation method of the present invention can prevent the thickness of the liner oxide film formed on the edge of the trench from being thin, and improve the shape of the edge to prevent the improvement of the characteristics of the gate oxide density and the generation of leakage current, thereby improving the reliability of the semiconductor device. And properties can be improved.
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| JPH10223747A (en) * | 1997-02-06 | 1998-08-21 | Nec Corp | Manufacture of semiconductor device |
| KR19980084107A (en) * | 1997-05-21 | 1998-12-05 | 문정환 | Device isolation method of semiconductor device |
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| KR19990066178A (en) * | 1998-01-22 | 1999-08-16 | 구본준 | Device isolation method of semiconductor device |
| JPH11284064A (en) * | 1998-01-13 | 1999-10-15 | Texas Instr Inc <Ti> | Method of forming trench isolators of transistor, without using chemical-mechanical polishing method |
| US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH10223747A (en) * | 1997-02-06 | 1998-08-21 | Nec Corp | Manufacture of semiconductor device |
| KR19980084107A (en) * | 1997-05-21 | 1998-12-05 | 문정환 | Device isolation method of semiconductor device |
| US5930620A (en) * | 1997-09-12 | 1999-07-27 | Advanced Micro Devices | Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures |
| US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
| JPH11186378A (en) * | 1997-12-24 | 1999-07-09 | Mitsubishi Electric Corp | Semiconductor integrated circuit, manufacture thereof, semiconductor device and manufacture thereof |
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