KR100332414B1 - Apparatus for virtual container mapper in synchronous digital hierarchy - Google Patents

Abstract

The present invention provides a virtual container mapper device on a synchronous digital hierarchy. The present invention includes: an STM-1 address generator for generating an address of STM-1; A mapper address generator for generating an address of the mapper; An STM-1 formatter configured to receive an address signal from the STM-1 address generator and to receive VC3 and VC3 / 4 signals from the mapper address generator to form an STM-1 format; A plurality of controllers which receive a control signal from the mapper address generator and output control signals for DS3, DS3E, AU3, and TUG-3 options; A plurality of VC11 / 12/3/4 processing units respectively receiving control signals from the plurality of controllers and processing VC11 / 12/3/4 and VC11 / 12/3, respectively, provide fewer gates when performing VCx mapping. You can implement a virtual container mapper with a number.

Description

Apparatus for virtual container mapper in synchronous digital hierarchy

The present invention relates to a Virtual Container (VC) Mapper device on a Synchronous Digital Hierarchy (SDH), and is particularly suitable for implementing a virtual container mapper with a low gate count when performing VCx mapping. A virtual container mapper device on a synchronous digital hierarchy.

In general, digital signal levels available in public telecommunication networks include PDH (Pleisynchronous Digital Hierarchy) of ITU-T Recommendation G.720 and SDH of G.707. There are many differences in the transmission of network maintenance signals. Therefore, in the synchronous network, the basic signal considering the stuffing of the byte unit for multiplexing is defined as STM-1 / STM-0, and the signal is crossed by the unit of byte to the STM-n (Synchronous Transport Module level n) signal. Multiplex. The speed of the multiplexed signal is an integer multiple of STM-1 / STM-0, and low-speed signal access is possible by one-step demultiplexing. These synchronous networks define sufficient overhead allocation and maintenance signals for network operation maintenance and are globally standardized. In addition, the virtual container (VC) is a unidirectional logical ATM channel between two or more ATM (Asynchronous Transfer Mode) end systems.

1 is a block diagram of a virtual container mapper device on a conventional synchronous digital hierarchy, assuming that DS1 is input.

As shown in the drawing, a plurality of VC11 / 12 processing units for receiving a DS1 (Digital Signal Level 1) or a DS1E signal and processing a VC (Virtual Container) 11/12 to output a Tributary Unit Group (TUG) 1 to 3); A plurality of VC3 / 4 and VC3 processing units 4 to 6 which receive the TUGs output from the plurality of VC11 / 12 processing units 1 to 3 and receive a DS3E / DS4 signal to process VC3; AU3 / 4 and AU3 pointer generation units for receiving VC3 / 4 and VC3 output from the plurality of VC3 / 4 and VC3 processing units 4 to 6 and generating AU (Administrative Unit) 3/4 and AU3 pointers (7); The AUG forming unit 8 generates an AUG (Administrative Unit Group) by receiving the AU3 / 4 and AU3 pointers output from the AU3 / 4 and AU3 pointer generators 7 and outputs an STM-1 signal.

The DS-1 signal is mapped to 28 internal VC11 channels according to the J1 byte frame of the VC-3 POH (Path Overhead) input for the VC11 mapping.

At this time, the TUG (Tributary Unit Group) having the capacity of four DS1 channels or three DS1E channels must have the same signal, that is, all DS1 for DS1 and DS1E for DS1E. When the DS1 signal is mapped to the VC12, all three signals must be DS1 signals. A signal created with these four DS1 channels or three DS1E channels is called a TUG.

Each TUG has the possibility to be mapped to DS1 (E) or DS1 to VC12 on the corresponding channel, so the format is different for DS1, DS1E, and DS1 to VC12.

In this case, each TUG mapper should have all the options to create the above three cases. Therefore, every 7 channel TUG must have the above option, and 21 TUGs must have the above option for 84 channels of DS1 having the capacity of STM-1.

This prior art causes a lot of circuit redundancy since 21 TUGs must have the same option. In addition, the mapping to VC-3 or VC-4 must have both AU-3 or TUG-3 paths, so the number of options to be implemented is twice that number.

This also occurs in the case where DS3 (E) is input. There are four options for DS3, DS3E, AU-3, and TUG-3 for one channel, because each option must be provided for mapping the input of DS3 (E) to VC-3 and to TUG-3. Should have In this case, all 12 options should be provided for the three-channel DS3 having the capacity of STM-1.

As described above, when mapping the line signals to the VC, the conventional method should have a variety of options according to the signal type that each line signal input can have and the path on the SDH of the VC to be mapped.

However, the above prior art has the following problems.

First, when VC11 / 12 is implemented in the lower TUG stage in order to implement the lower VC11 / 12, duplication of options to be implemented in each TUG stage is greatly increased.

Second, even in the case of mapping DS3 (E) to VC-3, options of DS3 and DS3E must be implemented in each of three channels.

Third, since there are paths of TUG-3 and AU-3 even when mapping TUG to VC-3 / 4, there is a problem that both the first and second options must be doubled.

Therefore, when the VC mapper is implemented using the conventional technology, there is a problem in that the number of gates is greatly increased.

Accordingly, the present invention has been proposed to solve the above conventional problems, and an object of the present invention is to provide a virtual container mapper device on a synchronous digital hierarchy that can implement a virtual container mapper with a low gate count when performing VCx mapping. There is.

In order to achieve the above object, the virtual container mapper on the synchronous digital hierarchy according to the present invention,

An STM-1 address generator for generating an address of STM-1; A mapper address generator for generating an address of the mapper; An STM-1 formatter configured to receive an address signal from the STM-1 address generator and to receive VC3 and VC3 / 4 signals from the mapper address generator to form an STM-1 format; A plurality of controllers which receive a control signal from the mapper address generator and output control signals for DS3, DS3E, AU3, and TUG-3 options; The technical configuration is characterized by consisting of a plurality of VC11 / 12/3/3/4 processing unit for receiving the control signal from the plurality of control units respectively to process VC11 / 12/3/3 and VC11 / 12/3 respectively.

1 is a block diagram of a virtual container mapper device on a conventional synchronous digital hierarchy;

2 is a block diagram of a virtual container mapper device on a synchronous digital hierarchy according to the present invention.

Explanation of symbols on the main parts of the drawings

11: STM-1 address generator 12: mapper address generator

13: STM-1 formatter 14 ~ 16: control unit

17 ~ 19: VC11 / 12/3/4 processing part

Hereinafter, an embodiment according to the technical spirit of the virtual container mapper device on the synchronous digital hierarchy of the present invention will be described.

2 is a block diagram of a virtual container mapper device on a synchronous digital hierarchy according to the present invention.

As shown therein, an STM-1 address generator 11 for generating an address of STM-1; A mapper address generator 12 for generating an address of the mapper; An STM-1 formatter 13 which receives an address signal from the STM-1 address generator 11 and receives VC3 and VC3 / 4 signals from the mapper address generator 12 to form an STM-1 format and output the STM-1 format; Wow; A plurality of controllers 14 to 16 which receive a control signal from the mapper address generator 12 and output control signals for DS3, DS3E, AU3, and TUG-3 options; Comprising a plurality of VC11 / 12/3/4 processing unit (17 ~ 19) for receiving the control signal from the plurality of control unit (14 ~ 16) to process the VC11 / 12/3/3/4 and VC11 / 12/3, respectively do.

The operation of the virtual container mapper device on the synchronous digital hierarchy configured as described above will be described in detail with reference to the accompanying drawings.

First, the STM-1 frame is determined using 19.44MHz. The STM-1 frame is used to determine the position in the VC on each AU-3 timeslot.

After determining the position of the VC, the mapper address generator 12 and the controllers 14 to 16 determine the three frame addresses and control signals for the T1, E1, and DS1-VC12 options, and the WPDJGKDU, DS3, DS3E, Generate the address and control signals corresponding to the AU3 and TUG-3 options, respectively.

Therefore, the mapper address generator 12 and the controllers 14 to 16 generate control signals for making the VC for each address and each TUG mode. Examples of the control signals include a byte data enable signal to be used when the line signals are serially input to the elastic buffer and used to change the data into parallel, and a bit enable signal to control the data in units of bits. And C1 and C2 signals for controlling the stuff bits.

When the tributary signal input using the generated control signal is DS1, the control signal of T1 is multiplexed and mapped to VC11. When the input signal is DS3 and is in the AU3 mode, the corresponding control signals of the mapper address generator 12 and the controllers 14 to 16 are multiplexed and used.

The mapped VCs are multiplexed using the address of the VC to make STM-1.

Therefore, as in the prior art, it is not necessary to implement each TUG block and a block of DS3 / E, AU3, and TUG-3 in a manner in which all options are included in the lower VC generator.

As such, the present invention implements a virtual container mapper with a small gate count when performing VCx mapping.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the virtual container mapper device on the synchronous digital hierarchy according to the present invention may implement each of the TUG blocks and the DS3 / E, AU3, and TUG-3 blocks in a manner in which all the options are included in the lower VC generator. This eliminates the need for a virtual container mapper with fewer gates when doing VCx mapping.

In addition, the present invention also has the effect of preventing the loss of power by processing the address generation block of the mode in the case of an unused mode, such as when the input signal is all T1, or E1.

Claims (1)

An STM-1 address generator for generating an address of STM-1; A mapper address generator for generating an address of the mapper; An STM-1 formatter configured to receive an address signal from the STM-1 address generator and to receive VC3 and VC3 / 4 signals from the mapper address generator to form an STM-1 format; A plurality of controllers which receive a control signal from the mapper address generator and output control signals for DS3, DS3E, AU3, and TUG-3 options; The virtual container on the synchronous digital hierarchy, characterized in that composed of a plurality of VC11 / 12/3/4 processing unit for receiving the control signal from the plurality of control units, respectively, and processes the VC11 / 12/3/3 and VC11 / 12/3 respectively. Mapper device.