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KR100336890B1 - Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device - Google Patents

Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device Download PDF

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Publication number
KR100336890B1
KR100336890B1 KR10-1998-0055063A KR19980055063A KR100336890B1 KR 100336890 B1 KR100336890 B1 KR 100336890B1 KR 19980055063 A KR19980055063 A KR 19980055063A KR 100336890 B1 KR100336890 B1 KR 100336890B1
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film
amorphous silicon
forming
gate
sinx
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KR10-1998-0055063A
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KR20000039662A (en
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임성실
손곤
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주식회사 현대 디스플레이 테크놀로지
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • H01L29/458Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 5개의 마스크를 이용한 박막 트랜지스터 액정표시소자의 제조 공정에서 액티브층의 손상을 방지함과 더불어 데이터 라인의 오픈문제를 방지할 수 있는 방법을 개시한다. 개시된 본 발명의 방법은, 상부에 게이트가 형성된 절연기판 상에 게이트 절연막용 제 SiNx막과 액티브층용 비정질 실리콘막을 순차적으로 형성하는 단계; 상기 게이트 상부의 상기 비정질 실리콘막 상에 제 2 SiNx막으로 이루어진 에치스톱퍼를 형성하는 단계; 상기 에치스톱퍼가 형성된 기판 전면 상에 도핑된 비정질 실리콘막을 형성하는 단계; 상기 게이트 양 측의 도핑된 비정질 실리콘막 상에 걸쳐서 소오스 및 드레인을 형성하는 단계; 상기 소오스 및 드레인을 마스크로하여 상기 도핑된 비정질 실리콘막 및 비정질 실리콘막을 습식식각하여 오믹층 및 액티브층을 형성하는 단계; 상기 오믹층 및 액티브층이 형성된 기판 전면 상에 패시배이션용 제 2 SiNx막을 형성하는 단계; 및 상기 제 3 및 제 1 SiNx막을 건식식각하여 패드오픈공정을 진행하는 단계를 포함한다. 본 실시예에 있어서, 상기 게이트는 절연기판 상에 Al-Nd막을 증착한 후에 이를 습식식각하여 형성하며, 상기 소오스 및 드레인은 Al-Nd막 또는 Al-Nd막의 적층막으로 형성한다.The present invention discloses a method of preventing damage to an active layer and preventing an open line of a data line in a manufacturing process of a thin film transistor liquid crystal display device using five masks. The disclosed method includes sequentially forming a first SiNx film for a gate insulating film and an amorphous silicon film for an active layer on an insulating substrate having a gate formed thereon; Forming an etch stopper made of a second SiNx film on the amorphous silicon film on the gate; Forming a doped amorphous silicon film on an entire surface of the substrate on which the etch stopper is formed; Forming a source and a drain over the doped amorphous silicon film on both sides of the gate; Wet etching the doped amorphous silicon film and the amorphous silicon film using the source and the drain as a mask to form an ohmic layer and an active layer; Forming a second SiNx film for passivation on an entire surface of the substrate on which the ohmic layer and the active layer are formed; And performing a pad opening process by dry etching the third and first SiNx films. In the present embodiment, the gate is formed by depositing an Al-Nd film on an insulating substrate and then wet etching it, and the source and drain are formed of an Al-Nd film or an Al-Nd film.

Description

박막 트랜지스터 액정 표시 소자의 제조방법Method of manufacturing thin film transistor liquid crystal display device

본 발명은 액정표시소자의 제조방법에 관한 것으로, 특히 5개의 마스크를 이용한 박막 트랜지스터 액정표시소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device using five masks.

액티브 매트릭스형 액정표시소자(active matrix-type liquid crystal display; AM-LCD)는 얇아서 다양한 표시장치에 사용된다. 이러한 AM-LCD에서 박막 트랜지스터(thin film transistor; TFT)가 각 화소에 대한 스위칭 소자로서 제공되어 개개의 화소전극들이 독립적으로 구동되며, 이에 따라 AM-LCD는 듀티(duty) 비의 감소에 기인하는 콘트라스트의 감소는 일어나지 않으며, 또한 디스플레이 용량이 증가하여 라인수가 증가될 때에도 시야각이 감소되지 않는다.Active matrix-type liquid crystal displays (AM-LCDs) are thin and are used in various display devices. In such an AM-LCD, a thin film transistor (TFT) is provided as a switching element for each pixel so that individual pixel electrodes are driven independently, and thus the AM-LCD is caused by a reduction in duty ratio. The reduction in contrast does not occur, and the viewing angle does not decrease even when the display capacity increases and the number of lines increases.

한편, 최근에는 이와 같은 AM-LCD를 게이트용 제 1 마스크, 에치스톱퍼용 제 2 마스크, 소오스 및 드레인용 제 3 마스크, 패드 오픈용 제 4 마스크, 및 화소전극용 제 5 마스크를 이용한 5-마스크 공정을 통해 형성함으로써, 공정 단순화를 꾀하고 있다. 여기서, 상기 공정 단순화는 제 3 마스크를 이용하여 소오스 및 드레인을 패터닝한 후에, 상기 소오스 및 드레인을 마스크로 하여 오믹층 및 액티브층 형성 공정을 수행할 수 있기 때문이다.On the other hand, in recent years, such an AM-LCD has a 5-mask using a first mask for a gate, a second mask for an etch stopper, a third mask for source and drain, a fourth mask for opening a pad, and a fifth mask for a pixel electrode. By forming through the process, the process is simplified. The process simplification is that after the source and drain are patterned using the third mask, the ohmic layer and the active layer forming process may be performed using the source and the drain as masks.

그러나, 상기한 바와 같은 종래의 5-마스크를 이용한 박막 트랜지스터 액정표시소자(이하, TFT-LCD)의 제조 공정은 공정 단계를 감소시킬 수 있는 장점이 있는 반면, 소오스 및 드레인을 마스크로 이용하여 액티브층을 형성하는 과정에서 에치스톱퍼의 식각에 기인하여 액티브층의 손상이 야기되고, 이 결과로 박막 트랜지스터의 오프 전류가 커지게 되는 문제가 있다. 즉, 소오스 및 드레인을 마스크로 이용하여 오믹층 및 액티브층을 형성할 경우, 통상, 오믹층용 도핑된 비정질 실리콘막과 액티브층용 비정질 실리콘막을 건식식각하게 되는데, 이 과정에서 SiNx로 이루어진 에치스톱퍼가 동시에 식각되어, 상기 에치스톱퍼 하부의 액티브층 부분에 서 손상이 발생된다.However, the manufacturing process of the thin film transistor liquid crystal display device (hereinafter referred to as TFT-LCD) using the conventional 5-mask as described above has the advantage of reducing the process steps, while using the source and drain as masks to activate the process. In the process of forming the layer, the etching of the etch stopper may cause damage to the active layer, and as a result, the off current of the thin film transistor may increase. In other words, when the ohmic layer and the active layer are formed using the source and the drain as a mask, the doped amorphous silicon film for the ohmic layer and the amorphous silicon film for the active layer are usually dry-etched. In this process, the etch stopper made of SiNx simultaneously Etching causes damage to the active layer portion below the etch stopper.

또한, 종래의 5-마스크를 이용한 TFT-LCD의 제조 공정은 제 4 마스크를 이용한 패드 오픈 공정을 패드를 덮고 있는 패시배이션막 물질인 SiNx막과 게이트 절연막 물질인 SiON막을 습식식각하는 방식으로 진행하고 있는데, 이 과정에서 포토레지스트막에 보이드가 발생하게 되고, 이 보이드를 통해 후속의 화소전극 형성시에 데이터 라인으로의 에천트(etchant) 침입이 일어나, 상기 데이터 라인의 오픈이 야기되며, 그래서 제조 수율이 저하되는 다른 문제가 있다.In addition, the conventional 5-mask TFT-LCD manufacturing process uses a pad opening process using a fourth mask by wet etching a SiNx film, which is a passivation film material covering the pad, and a SiON film, which is a gate insulating film material. In this process, voids are generated in the photoresist film, and through these voids, etchant intrusion into the data line occurs during subsequent pixel electrode formation, causing the data line to open. There is another problem that the production yield is lowered.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 5-마스크를 이용한 TFT-LCD의 제조에서 엑티브층의 손상 유발을 방지하면서 데이터 라인의 오픈을 방지할 수 있는 TFT-LCD의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, the manufacturing of a TFT-LCD that can prevent the opening of the data line while preventing the damage of the active layer in the production of TFT-LCD using a 5-mask. The purpose is to provide a method.

도 1a 및 도 1b는 본 발명의 실시예에 따른 박막 트랜지스터 액정 표시 소자의 제조방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

10 : 절연기판 11 : 게이트10: insulated substrate 11: gate

12 : 게이트 절연막 13 : 비정질 실리콘막12 gate insulating film 13 amorphous silicon film

13a : 액티브층 14 : 에치스톱퍼13a: active layer 14: etch stopper

15 : 도핑된 비정질 실리콘막 15a, 15b : 오믹층15: doped amorphous silicon film 15a, 15b: ohmic layer

16a, 16b : 소오스 및 드레인 17 : 제 3 마스크16a, 16b: source and drain 17: third mask

상기와 같은 목적을 달성하기 위한 본 발명의 5-마스크를 이용한 TFT-LCD의 제조방법은, 상부에 게이트가 형성된 절연기판 상에 게이트 절연막용 제 1 SiNx막과 액티브층용 비정질 실리콘막을 순차적으로 형성하는 단계; 상기 게이트 상부의 상기 비정질 실리콘막 상에 제 2 SiNx막으로 이루어진 에치스톱퍼를 형성하는 단계; 상기 에치스톱퍼가 형성된 기판 전면 상에 도핑된 비정질 실리콘막을 형성하는 단계; 상기 게이트 양 측의 도핑된 비정질 실리콘막 상에 걸쳐서 소오스 및 드레인을 형성하는 단계; 상기 소오스 및 드레인을 마스크로하여 상기 도핑된 비정질 실리콘막 및 비정질 실리콘막을 습식식각하여 오믹층 및 액티브층을 형성하는 단계;상기 오믹층 및 엑티브층이 형성된 기판 전면 상에 패시배이션용 제 2 SiNx막을 형성하는 단계; 및 상기 제 3 및 제 1 SiNx막을 건식식각하여 패드오픈공정을 진행하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a TFT-LCD using a 5-mask according to the present invention includes sequentially forming a first SiNx film for a gate insulating film and an amorphous silicon film for an active layer on an insulating substrate having a gate formed thereon. step; Forming an etch stopper made of a second SiNx film on the amorphous silicon film on the gate; Forming a doped amorphous silicon film on an entire surface of the substrate on which the etch stopper is formed; Forming a source and a drain over the doped amorphous silicon film on both sides of the gate; Wet etching the doped amorphous silicon layer and the amorphous silicon layer using the source and the drain as a mask to form an ohmic layer and an active layer; a second SiNx for passivation on an entire surface of the substrate on which the ohmic layer and the active layer are formed; Forming a film; And performing a pad opening process by dry etching the third and first SiNx films.

본 실시예에 있어서, 상기 게이트는 절연기판 상에 Al-Nd막을 형성한 후에 이를 습식식각하여 형성하며, 상기 소오스 및 드레인은 Al-Nd막 또는 Mo막과 Al-Nd막의 적층막으로 형성한다.In the present embodiment, the gate is formed by forming an Al-Nd film on an insulating substrate and then wet etching it, and the source and drain are formed of an Al-Nd film or a laminated film of an Mo film and an Al-Nd film.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 1a 및 도 1b는 본 발명의 실싱예에 따른 5-마스크를 이용한 TFT-LCD의 제조방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a TFT-LCD using a 5-mask according to a sealing example of the present invention.

도 1a를 참조하면, 절연기판(10) 상에 패드 오픈 공정에서 SiNx막의 건식식각에 대한 선택도(selectivityt)를 확보하기 위하여 게이트 물질로서 제 1 Al-Nd막을 증착하고, 상기 제 1 Al-Nd막 상에 포토리소그라피로 공정을 통해 게이트용 제 1 마스크(미도시)를 형성한다. 그런다음, 상기 제 1 마스크를 이용한 습식식각으로 상기 제 1 Al-Nd막을 식각하여 게이트(11)를 형성하고, 공지된 방법으로 상기 제 1 마스크를 제거한다.Referring to FIG. 1A, a first Al-Nd film is deposited as a gate material in order to secure selectivity for dry etching of a SiNx film in a pad open process on an insulating substrate 10, and the first Al-Nd is deposited. A first mask (not shown) for a gate is formed on the film through a photolithography process. Then, the first Al-Nd film is etched by wet etching using the first mask to form the gate 11, and the first mask is removed by a known method.

다음으로, 게이트(11)가 형성된 기판(10) 전면 상에 제 1 SiNx막으로 이루 어진 게이트 절연막(12)과 액티브층용 비정질 실리콘막(13) 및 에치스톱퍼용 제 2 SiNx막을 순차적으로 증착하고, 상기 제 2 SiNx막 상에 포토리소그라피 공정을 통해서 에치스톱퍼 형성용 제 2 마스크(미도시)를 형성한다. 그런다음, 상기 제 2 마스크를 이용한 습식식각으로 상기 제 2 SiNx막을 식각하여 게이트(11) 상부의 비정 질 실리콘막(13) 상에 에치스톱퍼(14)를 형성하고, 공지의 방법으로 제 2 마스크를제거한다. 여기서, 상기 게이트 절연막(12)의 물질을 종래의 SiON막에서 SiNx막으로 변경한 것은 후속의 패드 오픈 공정이 건식식각으로 진행되도록 하기 위함이다.Next, the gate insulating film 12 made of the first SiNx film, the active silicon layer 13, and the second SiNx film for the etch stopper are sequentially deposited on the entire surface of the substrate 10 on which the gate 11 is formed, A second mask (not shown) for forming an etch stopper is formed on the second SiNx film through a photolithography process. Then, the second SiNx film is etched by wet etching using the second mask to form an etch stopper 14 on the amorphous silicon film 13 above the gate 11, and a second mask by a known method. Remove Here, the material of the gate insulating film 12 is changed from the conventional SiON film to the SiNx film so that the subsequent pad opening process may be performed by dry etching.

계속해서, 에치스톱퍼(14)가 형성된 기판(10) 전면 상에 오믹층용 도핑된 비정질 실리콘막(15)을 증착하고, 그 상부에 후속의 패드 오픈 공정에서 SiNx막의 건식식각에 대한 선택도를 확보하기 위해 소오스 및 드레인 물질로서 제 2 Al-Nd막을 증착한다. 여기서, 제 2 Al-Nd막 대신에 Mo막과 Al-Nd막을 순차 적층하여 액티브층과 접합 스파이킹(junction spiking)의 발생을 방지할 수 있다. 상기 제 2 Al-Nd막 상에 포토리소그라피 공정을 통해 소오스 및 드레인용 제 3 마스크(17)를 형성하고, 상기 제 3 마스크(17)를 이용한 습식식각으로 상기 제 2 Al-Nd막을 식각하여 소오스 및 드레인(16a, 16b)을 형성한다.Subsequently, the doped amorphous silicon film 15 for the ohmic layer is deposited on the entire surface of the substrate 10 on which the etch stopper 14 is formed, and the selectivity for dry etching of the SiNx film is secured thereon in a subsequent pad opening process. To do this, a second Al-Nd film is deposited as the source and drain material. Here, instead of the second Al-Nd film, the Mo film and the Al-Nd film are sequentially stacked to prevent the occurrence of junction spiking with the active layer. A third mask 17 for source and drain is formed on the second Al-Nd film through a photolithography process, and the second Al-Nd film is etched by wet etching using the third mask 17 to form a source. And drains 16a and 16b.

도 1b를 참조하면, 소오스 및 드레인(16a, 16b)을 마스크로하여 도핑된 비정질 실리콘막과 비정질 실리콘막을 습식식각하고, 이를 통해, 오믹층(15a, 15b)과 액티브층(13a)을 형성한다. 이때, 종래에는 도핑된 비정질 실리콘막과 비정질 실리콘막의 식각을 건식식각으로 수행하기 때문에, 이 과정에서 에치스톱퍼(14)의 손상이 야기되지만, 본 발명의 실시예에서는 상기 도핑된 비정질 실리콘막과 비정질 실리콘막의 식각으로 습식식각으로 수행하므로, 비정질 실리콘막에 대한 SiNx막의 식각 선택비에 의해 에치스톱퍼(14)의 손상은 거의 유발되지 않으며, 따라서, 에치스톱퍼(14)의 손상이 유발되지 않는 바, 액티브층(13a)의 손상도 유발되지 않는다.Referring to FIG. 1B, the doped amorphous silicon film and the amorphous silicon film are wet etched using the source and drain 16a and 16b as a mask, thereby forming ohmic layers 15a and 15b and an active layer 13a. . At this time, since the etching of the doped amorphous silicon film and the amorphous silicon film is conventionally performed by dry etching, damage to the etch stopper 14 is caused in this process, but in the embodiment of the present invention, the doped amorphous silicon film and the amorphous silicon film are amorphous. Since the etching of the silicon film is performed by wet etching, the damage of the etch stopper 14 is hardly caused by the etching selectivity of the SiNx film with respect to the amorphous silicon film, and thus, the damage of the etch stopper 14 is not induced. No damage to the active layer 13a is caused.

계속해서, 공지의 방법으로 제 3 마스크를 제거한 후, 도시되지는 않았지만, 기판(10)의 전면 상에 제 3 SiNx로 이루어진 패시배이션막을 형성하고, 상기 패시배이션막 상에 포토리소그라피 공정을 통해 제 4 마스크를 형성한다. 그런다음, 상기 제 4 마스크를 이용한 건식식각으로 패드 영역의 패시배이션막 및 게이트 절연막(12)을 식각하여 패드를 오픈시키고, 공지의 방법으로 제 1 마스크를 제거한다.여기서, 패드 오픈 공정은 게이트 절연막 물질을 SiNx막으로 변경시킬 것으로 인해 건식식각으로도 수행 가능하며, 따라서 패드 오픈 공정에서의 습식식각에 기인하는 보이드의 발생이 유발되지 않는 바, 후속하는 화소전극 형성시에 데이터 라인의 오픈은 유발되지 않는다.Subsequently, after removing the third mask by a known method, although not shown, a passivation film made of third SiNx is formed on the entire surface of the substrate 10, and a photolithography process is performed on the passivation film. Through the fourth mask is formed. Thereafter, the passivation film and the gate insulating film 12 of the pad region are etched by dry etching using the fourth mask to open the pad, and the first mask is removed by a known method. By changing the gate insulating film material to the SiNx film, it is also possible to perform dry etching, and thus no generation of voids caused by wet etching in the pad opening process is caused. Is not triggered.

다음으로, 기판(10)의 전면 상에 ITO막을 증착한 후, 상기 ITO막 상에 포토리소그라피 공정을 통해 제 5 마스크를 형성하고, 그런다음, 상기 제 5 마스크를 이용한 습식식각으로 ITO막을 식각하여 화소전극을 형성하고, 이후, 공지의 방법으로 상기 제 5 마스크를 제거한다.Next, after depositing an ITO film on the entire surface of the substrate 10, a fifth mask is formed on the ITO film through a photolithography process, and then the ITO film is etched by wet etching using the fifth mask. After forming the pixel electrode, the fifth mask is removed by a known method.

상기한 본 발명에 따르면, 소오스 및 드레인을 마스크로 이용한 액티브층의 형성을 습식식각으로 진행함에 따라 에치스톱퍼층의 식각으로 인한 액티브층의 손상을 효과적으로 방지할 수 있으며, 따라서, 박막 트랜지스터의 오픈 전류를 감소시킬 수 있다. 또한, 게이트 절연막을 SiON막 대신에 SiNx막으로 형성함에 따라, 패드 오픈 공정을 건식식각으로 진행하는 것이 가능하기 때문에, 습식식각으로 인한 마스크(포토레지스트막)의 보이드 발생을 방지할 수 있으며, 따라서, 데이터 라인의 오픈 불량을 방지할 수 있어, 소자의 제조수율을 향상시킬 수 있다.According to the present invention described above, as the active layer is formed by wet etching using the source and the drain as a mask, damage to the active layer due to the etching of the etch stopper layer can be effectively prevented, and therefore, the open current of the thin film transistor. Can be reduced. In addition, by forming the gate insulating film as a SiNx film instead of the SiON film, the pad opening process can be performed by dry etching, thereby preventing the generation of voids in the mask (photoresist film) due to wet etching. As a result, open defects of the data line can be prevented, and the manufacturing yield of the device can be improved.

기타, 본 발명은 상기 실시예에 한정되지 않고 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, the present invention is not limited to the above embodiments and can be carried out in various modifications without departing from the technical gist of the present invention.

Claims (4)

상부에 게이트가 형성된 절연기판 상에 게이트 절연막용 제 1 SiNx막과 액티브층용 비정질 실리콘막을 순차적으로 형성하는 단계:Sequentially forming a first SiNx film for a gate insulating film and an amorphous silicon film for an active layer on an insulating substrate having a gate formed thereon: 상기 게이트 상부의 상기 비정질 실리콘막 상에 제 2 SiNx막으로 이루어진 에치스톱퍼를 형성하는 단계:Forming an etch stopper made of a second SiNx film on the amorphous silicon film on the gate; 상기 에치스톱퍼가 형성된 기판 전면 상에 도핑된 비정질 실리콘막을 형성하는 단계:Forming a doped amorphous silicon film on an entire surface of the substrate on which the etch stopper is formed; 상기 게이트 양 측의 도핑된 비정질 실리콘막 상에 걸쳐서 소오스 및 드레인을 형성하는 단계;Forming a source and a drain over the doped amorphous silicon film on both sides of the gate; 상기 소오스 및 드레인을 마스크로하여 상기 도핑된 비정질 실리콘막 및 비정질 실리콘막을 습식식각하여 오믹층 및 액티브층을 형성하는 단계:Forming an ohmic layer and an active layer by wet etching the doped amorphous silicon layer and the amorphous silicon layer using the source and the drain as masks: 상기 오믹층 및 액티브층이 형성된 기판 전면 상에 패시배이션용 제 2 SiNx막을 형성하는 단계; 및Forming a second SiNx film for passivation on an entire surface of the substrate on which the ohmic layer and the active layer are formed; And 상기 제 3 및 제 1 SiNx막을 건식식각하여 패드오픈공정을 진행하는 단계를 포함하는 것을 특징으로 하는 박막 트랜지스터 액정표시소자의 제조방법.And dry-etching the third and first SiNx films to perform a pad opening process. 제 1 항에 있어서, 상기 게이트는 Al-Nd막으로 형성하는 것을 특징으로 하는 박막 트랜지스터 액정 표시 소자의 제조방법.The method of claim 1, wherein the gate is formed of an Al-Nd film. 제 1 항에 있어서, 상기 소오스 및 드레인은 Al-Nd막으로 형성하는 것을 특징으로 하는 박막 트랜지스터 액정표시소자의 제조방법.The method of claim 1, wherein the source and the drain are formed of an Al-Nd film. 제 1 항에 있어서, 상기 소오스 및 드레인은 Mo막과 Al-Nd막의 적층막으로 형성하는 것을 특징으로 하는 액정표시소자의 제조방법.The method of claim 1, wherein the source and the drain are formed of a laminated film of an Mo film and an Al-Nd film.
KR10-1998-0055063A 1998-12-15 1998-12-15 Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device KR100336890B1 (en)

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