KR100335800B1 - CMOS transistor and method for manufacturing the same - Google Patents
CMOS transistor and method for manufacturing the same Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 16
- 230000000087 stabilizing effect Effects 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
본 발명은 채널(Channel) 영역과 반도체 기판의 전기적 연결 통로인 콘택을 형성한 후 채널 영역 형성용 에피택셜(Epitaxial)층을 성장시키므로 상기 반도체 기판이 플로팅(Floating)되는 것을 방지하는 시모스(Complementary Metal Oxide Semi Conductor : CMOS) 트랜지스터 및 그의 제조 방법에 관한 것이다.The present invention forms a contact that is an electrical connection path between a channel region and a semiconductor substrate, and then grows an epitaxial layer for forming a channel region, thereby preventing the semiconductor substrate from floating. Oxide Semi Conductor (CMOS) transistors and a method of manufacturing the same.
본 발명의 CMOS 트랜지스터 및 그의 제조 방법은 채널 영역과 반도체 기판의 전기적 연결 통로인 콘택을 형성한 후 채널 영역 형성용 에피택셜층을 성장시키므로, 상기 반도체 기판이 플로팅되는 것을 방지하여 문턱 전압이 안정되고 킹크(Kink) 현상의 발생을 방지하므로 소자의 특성 및 신뢰성을 향상시키는 특징이 있다.In the CMOS transistor of the present invention and a method of manufacturing the same, an epitaxial layer for forming a channel region is grown after forming a contact, which is an electrical connection passage between a channel region and a semiconductor substrate, thereby preventing the semiconductor substrate from floating, thereby stabilizing a threshold voltage. Since it prevents the occurrence of a kink phenomenon, there is a feature to improve the characteristics and reliability of the device.
Description
본 발명은 시모스(Complementary Metal Oxide Semi Conductor : CMOS) 트랜지스터 및 그의 제조 방법에 관한 것으로, 특히 채널(Channel) 영역과 반도체 기판의 전기적 연결 통로인 콘택을 형성한 후 채널 영역 형성용 에피택셜(Epitaxial)층을 성장시켜 소자의 전기적 특성을 향상시키는 CMOS 트랜지스터 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS metal transistor (CMOS) transistor and a method for fabricating the same. Particularly, an epitaxial layer for forming a channel region is formed after a contact is formed between the channel region and a semiconductor substrate. The present invention relates to a CMOS transistor and a method for manufacturing the same, which grow layers to improve electrical characteristics of the device.
종래 기술에 따른 CMOS 트랜지스터의 제조 방법은 도 1a에서와 같이, 반도체 기판(11) 표면내에 n형 불순물 이온을 주입하여 드레인 영역(12)을 형성한다.In the method of manufacturing a CMOS transistor according to the prior art, as shown in FIG. 1A, n-type impurity ions are implanted into a surface of a semiconductor substrate 11 to form a drain region 12.
도 1b에서와 같이, 상기 드레인 영역(12)이 형성된 반도체 기판(11)상에 제 1 피에스지(Phospho Silicate Glass : PSG)층(13), 산화막(14), 질화막(15) 및 제 2 PSG층(16)을 순차적으로 형성한다.As shown in FIG. 1B, a first PSG layer 13, an oxide film 14, a nitride film 15, and a second PSG are formed on a semiconductor substrate 11 on which the drain region 12 is formed. Layers 16 are formed sequentially.
도 1c에서와 같이, 상기 제 2 PSG층(16)상에 감광막(17)을 도포한 후, 상기 감광막(17)을 채널 영역이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1C, after the photoresist layer 17 is coated on the second PSG layer 16, the photoresist layer 17 is selectively exposed and developed to be removed only at a portion where a channel region is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 감광막(17)을 마스크로 상기 제 2 PSG층(16), 질화막(15), 산화막(14) 및 제 1 PSG층(13)을 선택적으로 식각하여 상기 채널 영역의 반도체 기판(11)을 노출시킨다.The second PSG layer 16, the nitride layer 15, the oxide layer 14, and the first PSG layer 13 are selectively etched using the selectively exposed and developed photoresist layer 17 as a mask. The semiconductor substrate 11 is exposed.
도 1d에서와 같이, 상기 감광막(17)을 제거한 후, 상기 노출된 채널 영역의 반도체 기판(11)과 제 2 PSG층(16)상에 에피택셜층(18)을 성장시킨 다음, 상기 제 2 PSG층(16)을 식각 종말점으로 하는 시엠피(Chemical Mechanical Polishing : CMP) 방법에 의해 상기 에피택셜층(18)을 평탄화한다.As shown in FIG. 1D, after removing the photoresist layer 17, an epitaxial layer 18 is grown on the exposed semiconductor substrate 11 and the second PSG layer 16 in the channel region. The epitaxial layer 18 is planarized by a chemical mechanical polishing (CMP) method using the PSG layer 16 as an etching end point.
도 1e에서와 같이, 상기 제 2 PSG층(16)과 에피택셜층(18)상에 고농도의 n형 불순물이 주입된 다결정 실리콘층, 제 2 질화막(20) 및 제 2 감광막(21)을 순차적으로 형성한다.As shown in FIG. 1E, the polycrystalline silicon layer, the second nitride film 20, and the second photosensitive film 21 in which high concentrations of n-type impurities are implanted on the second PSG layer 16 and the epitaxial layer 18 are sequentially formed. To form.
그리고, 상기 제 2 감광막(21)을 소오스 영역이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.The second photosensitive film 21 is selectively exposed and developed so that only the portion where the source region is to be formed remains.
이어, 상기 선택적으로 노광 및 현상된 제 2 감광막(21)을 마스크로 상기 제 2 질화막(20), 다결정 실리콘층 및 제 2 PSG층(16)을 선택적으로 식각한다.Subsequently, the second nitride film 20, the polycrystalline silicon layer, and the second PSG layer 16 are selectively etched using the selectively exposed and developed second photosensitive film 21 as a mask.
여기서, 상기 다결정 실리콘충의 선택적 식각으로 소오스 영역(19)을 형성한다.Here, the source region 19 is formed by selective etching of the polycrystalline silicon worm.
도 1f에서와 같이, 상기 제 2 감광막(21)을 제거한 후, 상기 제 1, 제 2 질화막(15,20)상에 제 3 질화막을 형성하고, 상기 제 3 질화막을 에치백(Etch back)하여 상기 소오스 영역(19) 양측의 산화막(14)상에 제 3 질화막 측벽(22)을 형성한다음, 상기 산화막(14)을 제거한다.As shown in FIG. 1F, after removing the second photoresist layer 21, a third nitride layer is formed on the first and second nitride layers 15 and 20, and the third nitride layer is etched back. The third nitride film sidewall 22 is formed on the oxide film 14 on both sides of the source region 19, and then the oxide film 14 is removed.
여기서, 상기 제 3 질화막의 에치백 공정 시, 상기 노출된 제 1 질화막(15)도 선택 제거된다.Here, during the etch back process of the third nitride film, the exposed first nitride film 15 is also selectively removed.
도 1g에서와 같이, 전면에 열산화 공정으로 상기 노출된 에피택셜층(18) 표면상에 게이트 산화막을 성장시킨 다음, 전면에 제 2 다결정 실리콘층을 형성하고, 상기 제 2 다결정 실리콘층을 에치백하여 게이트 전극(23)을 형성한다.As shown in FIG. 1G, a gate oxide film is grown on the exposed epitaxial layer 18 surface by a thermal oxidation process on the front surface, a second polycrystalline silicon layer is formed on the front surface, and the second polycrystalline silicon layer is deposited on the surface. The back electrode is formed to form the gate electrode 23.
그러나 종래의 CMOS 트랜지스터 및 그의 제조 방법은 채널 영역이 반도체 기판과 전기적으로 연결되지 않아 상기 반도체 기판이 플로팅(Floating)되므로 문턱 전압이 불안정하고 킹크(Kink) 현상이 발생되어 소자의 특성 및 신뢰성이 저하되는 문제점이 있었다.However, in the conventional CMOS transistor and a method of manufacturing the same, since the channel region is not electrically connected to the semiconductor substrate, the semiconductor substrate is floating, so the threshold voltage is unstable and a kink occurs, thereby degrading the characteristics and reliability of the device. There was a problem.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 채널 영역과 반도체 기판의 전기적 연결 통로인 콘택을 형성한 후 채널 영역 형성용 에피택셜층을 성장시키므로 상기 반도체 기판이 플로팅되는 것을 방지하는 CMOS 트랜지스터 및 그의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above-mentioned problems, the CMOS transistor which prevents the semiconductor substrate from floating because the epitaxial layer for forming the channel region is grown after forming a contact that is an electrical connection passage between the channel region and the semiconductor substrate; Its purpose is to provide a process for its preparation.
도 1a 내지 도 1g는 종래 기술에 따른 CMOS 트랜지스터의 제조 방법을 나타낸 공정 단면도1A to 1G are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to the prior art.
도 2는 본 발명의 실시 예에 따른 CMOS 트랜지스터를 나타낸 구조 단면도2 is a cross-sectional view illustrating a CMOS transistor according to an embodiment of the present invention.
도 3a 내지 도 3h는 본 발명의 실시 예에 따른 CMOS 트랜지스터의 제조 방법을 나타낸 공정 단면도3A to 3H are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
31 : SOI 기판 32 : 실리콘 기판31 SOI substrate 32 Silicon substrate
33 : 매립 산화막 34 : 제 1 에피택셜층33: buried oxide film 34: first epitaxial layer
35 : 제 1 질화막 36 : 제 1 감광막35 first nitride film 36 first photosensitive film
37 : PSG층 38 : BSG층37: PSG layer 38: BSG layer
39 : 제 2 감광막 40 : 제 1 전극 콘택홀39: second photosensitive film 40: first electrode contact hole
41 : 제 2 전극 콘택홀 42 : 제 3 감광막41 second electrode contact hole 42 third photosensitive film
43 : NMOS의 드레인 영역 44 : PMOS의 드레인 영역43: drain region of NMOS 44: drain region of PMOS
45 : 제 2 에피택셜층 46 : NMOS의 채널 영역45: second epitaxial layer 46: channel region of NMOS
47 : PMOS의 채널 영역 48 : p형 웰47: PMOS channel region 48: p-type well
49 : NMOS의 소오스 영역 50 : n형 웰49: source region of NMOS 50: n-type well
51 : PMOS의 소오스 영역 52 : 제 2 질화막51 source region of PMOS 52 second nitride film
53 : 게이트 산화막 54 : NMOS의 게이트 전극53 gate oxide film 54 gate electrode of NMOS
55 : PMOS의 게이트 전극55: gate electrode of PMOS
본 발명의 CMOS 트랜지스터는 실리콘 기판 표면내에 이웃하여 형성된 제 1, 제 2 도전형 웰, 상기 각 제 1, 제 2 도전형 웰 상측에 형성된 제 1, 제 2 전극 콘택홀을 갖으며 상기 실리콘 기판상에 순차적으로 적층되어 형성된 매립 산화막과 제 1 에피택셜층, 상기 각 제 1, 제 2 도전형 웰 상측의 제 1 에피택셜층내에 형성되는 제 1, 제 2 도전형 드레인 영역, 상기 각 제 1, 제 2 전극 콘택홀과 각 제 1,제 2 전극 콘택홀에 인접한 제 1 에피택셜층상에 제 2 에피택셜층의 성장 공정으로 형성되는 제 1, 제 2 도전형 MOS의 채널 영역, 상기 각 제 1, 제 2 도전형 MOS의 채널 영역 양측의 제 1 에피택셜층상에 게이트 절연막을 개재하며 형성되는 제 1, 제 2 도전형 MOS의 게이트 전극 및 상기 각 제 1, 제 2 도전형 MOS의 채널 영역과 각 제 1, 제 2 도전형 MOS의 게이트 전극상에 형성되는 제 1, 제 2 도전형 소오스 영역을 포함하여 구성됨을 특징으로 한다.The CMOS transistor of the present invention has a first and a second conductivity type well formed adjacent to a surface of a silicon substrate, and first and second electrode contact holes formed on each of the first and second conductivity type wells and are formed on the silicon substrate. A buried oxide film and a first epitaxial layer sequentially stacked on the first and second conductivity type wells, and first and second conductivity type drain regions formed in the first epitaxial layer above each of the first and second conductivity type wells. A channel region of the first and second conductivity type MOSs formed by a process of growing a second epitaxial layer on the second electrode contact hole and the first epitaxial layer adjacent to each of the first and second electrode contact holes, wherein each of the first And gate electrodes of the first and second conductivity type MOSs formed on the first epitaxial layers on both sides of the channel region of the second conductivity type MOS, and the channel regions of the first and second conductivity type MOSs. Formed on the gate electrodes of each of the first and second conductivity type MOSs Is characterized by including the first and second conductivity type source regions.
본 발명의 CMOS 트랜지스터의 제조 방법은 제 1, 제 2 도전형 MOS가 형성될 부위가 각각 정의되며 실리콘 기판상에 매립 산화막과 제 1 에피택셜층이 순차적으로 적층되어 형성된 SOI 기판을 마련하는 단계, 상기 제 2 도전형 MOS가 형성될 부위의 SOI 기판상에 제 2 도전형 불순물 이온이 주입된 제 1 절연막을 형성하고, 상기 SOI 기판과 제 1 절연막상에 제 1 도전형 불순물 이온이 주입된 제 2 절연막을 형성하고 평탄화 하는 단계, 상기 제 2 도전형 MOS가 형성될 부위의 제 2 절연막, 제 1 절연막, 제 1 에피택셜층 및 매립 산화막을 선택 식각하여 제 1 전극 콘택홀을 형성하고, 상기 제 1 도전형 MOS가 형성될 부위의 제 2 절연막, 에피택셜층 및 매립 산화막을 선택 식각하여 제 2 전극 콘택홀을 형성하는 단계, 상기 제 2 도전형 MOS가 형성될 부위에서 채널 영역이 형성될 부위의 제 2 절연막과 제 1 절연막을 식각하고, 상기 제 1 도전형 MOS가 형성될 부위에서 채널 영역이 형성될 부위의 제 2 절연막을 식각하는 단계, 전면의 열처리에 의해 상기 제 1, 제 2 절연막에 각각 주입된 제 2 도전형 이온과 제 1 도전형 이온이 상기 제 1 에피택셜층에 주입되어 제 1, 제 2 도전형 드레인 영역을 형성하는 단계, 상기 제 1, 제 2 전극 콘택홀과 채널 영역이 형성될 부위 및 소오스 영역이 형성될 부위에 제 2 에피택셜층을 성장시켜 제 1, 제 2 도전형 MOS의 채널 영역을 형성하는 단계, 상기 제 1, 제 2 절연막을 제거하는 단계, 상기 제 2 도전형 MOS가 형성될 부위의 실리콘 기판 표면내에 제 1 도전형 웰을 형성하고, 상기 제 2 도전형 MOS의 채널 영역상의 소오스 영역이 형성될 부위의 제 2 에피택셜층에 고농도 제 2 도전형 불순물 이온을 주입하여 제 2 도전형 소오스 영역을 형성하는 단계, 상기 제 1 도전형 MOS가 형성될 부위의 실리콘 기판 표면내에 제 2 도전형 웰을 형성하고, 상기 제 1 도전형 MOS의 채널 영역상의 소오스 영역이 형성될 부위의 제 2 에피택셜층에 고농도 제 1 도전형 불순물 이온을 주입하여 제 1 도전형 소오스 영역을 형성하는 단계 및 상기 각 제 1, 제 2 도전형 MOS의 채널 영역 양측의 각 제 1, 제 2 도전형 소오스 영역 하측에 게이트 절연막을 개재한 제 1, 제 2 도전형 MOS의 게이트 전극을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a CMOS transistor of the present invention, the step of forming a first and second conductivity-type MOS is defined, each step of providing an SOI substrate formed by sequentially buried oxide film and the first epitaxial layer on a silicon substrate, A first insulating film in which a second conductivity type impurity ion is implanted on the SOI substrate at the site where the second conductivity type MOS is to be formed, and a first conductivity type impurity ion is implanted on the SOI substrate and the first insulating film Forming and planarizing the second insulating film, and selectively etching the second insulating film, the first insulating film, the first epitaxial layer, and the buried oxide film at the portion where the second conductive MOS is to be formed to form a first electrode contact hole; Selectively etching the second insulating film, the epitaxial layer and the buried oxide film in the portion where the first conductivity type MOS is to be formed to form a second electrode contact hole, and forming a channel region at the portion where the second conductivity type MOS is to be formed Etching the second insulating film and the first insulating film of the portion to be formed, and etching the second insulating film of the portion where the channel region is to be formed in the portion where the first conductive MOS is to be formed; A second conductive type ion and a first conductive type ion implanted in each of the second insulating layer are implanted into the first epitaxial layer to form first and second conductive type drain regions, and the first and second electrode contact holes Forming a channel region of the first and second conductivity type MOSs by growing a second epitaxial layer on the region where the channel region is to be formed and the region where the source region is to be formed, and removing the first and second insulating layers. Forming a first conductivity well in the surface of the silicon substrate of the site where the second conductivity type MOS is to be formed, and forming a high concentration agent in the second epitaxial layer of the site where the source region on the channel region of the second conductivity type 2 implanting impurity ions Forming a second conductivity type source region, forming a second conductivity type well in the surface of the silicon substrate at the site where the first conductivity type MOS is to be formed, and forming a source region on the channel region of the first conductivity type MOS. Implanting a high concentration of first conductivity type impurity ions into a second epitaxial layer of a region to be formed to form a first conductivity type source region and each of first and second sides of channel regions of each of the first and second conductivity type MOSs And forming gate electrodes of the first and second conductivity type MOSs through the gate insulating layer under the second conductivity type source region.
상기와 같은 본 발명에 따른 CMOS 트랜지스터 및 그의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the CMOS transistor and a method of manufacturing the same according to the present invention as described above will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 실시 예에 따른 CMOS 트랜지스터를 나타낸 구조 단면도이고, 도 3a 내지 도 3h는 본 발명의 실시 예에 따른 CMOS 트랜지스터의 제조 방법을 나타낸 공정 단면도이다.2 is a cross-sectional view illustrating a CMOS transistor according to an exemplary embodiment of the present invention, and FIGS. 3A to 3H are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to an exemplary embodiment of the present invention.
본 발명의 실시 예에 따른 CMOS 트랜지스터는 도 2에서와 같이, 실리콘 기판(32) 표면내에 이웃하여 형성된 p형 웰(48)과 n형 웰(50), 상기 각 p형 웰(48)과 n형 웰(50) 상측에 형성된 제 1, 제 2 전극 콘택홀(40,41)을 갖으며 상기 실리콘 기판(32)상에 순차적으로 적층되어 형성된 매립 산화막(33)과 제 1 에피택셜층(34), 상기 각 p형 웰(48)과 n형 웰(50) 상측의 제 1 에피택셜층(34)내에 형성되는 NMOS, PMOS의 드레인 영역(43,44), 상기 각 제 1, 제 2 전극 콘택홀(40,41)과 각 제 1, 제 2 전극 콘택홀(40,41)에 인접한 제 1 에피택셜층(34)상에 제 2 에피택셜층(45)의 성장 공정으로 형성되는 NMOS, PMOS의 채널 영역(46,47), 상기 각 NMOS, PMOS의 채널 영역(46,47) 양측의 제 1 에피택셜층(34)상에 게이트 절연막을 개재하며 형성되는 NMOS, PMOS의 게이트 전극(54,55), 상기 각 NMOS, PMOS의 채널 영역(46,47)과 각 NMOS, PMOS의 게이트 전극(54,55)상에 형성되는 NMOS, PMOS의 소오스 영역(49,51)으로 구성된다.As shown in FIG. 2, a CMOS transistor according to an exemplary embodiment of the present invention has a p-type well 48 and an n-type well 50 formed adjacent to a surface of a silicon substrate 32, and each of the p-type wells 48 and n. A buried oxide film 33 and a first epitaxial layer 34 having first and second electrode contact holes 40 and 41 formed on the upper side of the type well 50 and sequentially stacked on the silicon substrate 32. ), Drain regions 43 and 44 of NMOS and PMOS formed in the first epitaxial layer 34 above the p-type wells 48 and the n-type wells 50, respectively, and the first and second electrodes An NMOS formed by a process of growing a second epitaxial layer 45 on the contact holes 40 and 41 and the first epitaxial layer 34 adjacent to each of the first and second electrode contact holes 40 and 41; NMOS and PMOS gate electrodes 54 formed on the channel regions 46 and 47 of the PMOS, and the first epitaxial layer 34 on both sides of the NMOS and PMOS channel regions 46 and 47, respectively, with a gate insulating film interposed therebetween. 55, the channel regions 46 and 47 of the respective NMOS and PMOS, NMOS and PMOS source regions 49 and 51 formed on gate electrodes 54 and 55 of NMOS and PMOS.
본 발명의 실시 예에 따른 CMOS 트랜지스터의 제조 방법은 도 3a에서와 같이, NMOS와 PMOS가 형성될 부위가 각각 정의된 에스오아이(Silicon On Insulator : SOI) 기판(31)상에 제 1 질화막(35)과 제 1 감광막(36)을 형성하고, 상기 제 1 감광막(36)을 상기 PMOS가 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.In the method of manufacturing a CMOS transistor according to an embodiment of the present invention, as shown in FIG. 3A, a first nitride film 35 is formed on a silicon on insulator (SOI) substrate 31 in which portions of NMOS and PMOS are to be defined, respectively. ) And a first photosensitive film 36, and selectively expose and develop the first photosensitive film 36 so that only the portion where the PMOS is to be formed remains.
여기서, 상기 SOI(Silicon On Insulator) 기판(31)은 실리콘(Si) 기판(32)상에 매립 산화막(33)과 에피택셜층(34)이 순차적으로 적층되어 형성된다.Here, the silicon on insulator (SOI) substrate 31 is formed by sequentially filling the buried oxide film 33 and the epitaxial layer 34 on the silicon (Si) substrate 32.
그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막(36)을 마스크로 상기 NMOS가 형성될 부위의 제 1 질화막(35)을 식각한다.Then, the first nitride film 35 of the portion where the NMOS is to be formed is etched using the selectively exposed and developed first photosensitive film 36 as a mask.
도 3b에서와 같이, 상기 제 1 감광막(36)을 제거하고, 상기 SOI 기판(31)과 제 1 질화막(35)상에 인(P) 이온이 주입된 PSG층(37)을 형성한다.As shown in FIG. 3B, the first photosensitive layer 36 is removed and a PSG layer 37 implanted with phosphorus (P) ions is formed on the SOI substrate 31 and the first nitride layer 35.
그리고, 상기 제 1 질화막(35)을 식각 종말점으로 하는 CMP 방법에 의해 상기 PSG층(37)을 평탄화 하여 상기 NMOS가 형성될 부위의 SOI 기판(31)상에 PSG층(37)을 형성한다.The PSG layer 37 is planarized by a CMP method using the first nitride film 35 as an etching end point to form a PSG layer 37 on the SOI substrate 31 at the portion where the NMOS is to be formed.
도 3c에서와 같이, 상기 제 1 질화막(35)을 제거한 후, 상기 SOI 기판(31)과 PSG층(37)상에 붕소(B)가 주입된 비에스지(Boron Silicate Glass : BSG)층(38)을 형성하고 평탄화 한다.As shown in FIG. 3C, after removing the first nitride layer 35, boron (B) implanted with a boron (B) layer 38 on the SOI substrate 31 and the PSG layer 37. Form and planarize.
그리고, 상기 BSG층(38)상에 제 2 감광막(39)을 도포한 후, 상기 제 2 감광막(39)을 기판 전극 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.After the second photoresist film 39 is coated on the BSG layer 38, the second photoresist film 39 is selectively exposed and developed to be removed only at a portion where a substrate electrode contact is to be formed.
이어, 상기 선택적으로 노광 및 현상된 제 2 감광막(39)을 마스크로 상기 NMOS가 형성될 부위에는 상기 BSG층(38), PSG층(37), 에피택셜층(34) 및 매립 산화막(33)을 선택 식각하여 제 1 전극 콘택홀(40)을 형성하고, 상기 PMOS가 형성될 부위에는 상기 BSG층(38), 에피택셜층(34) 및 매립 산화막(33)을 선택 식각하여 제 2 전극 콘택홀(41)을 형성한다.Subsequently, the BSG layer 38, the PSG layer 37, the epitaxial layer 34, and the buried oxide layer 33 are formed at a portion where the NMOS is to be formed using the selectively exposed and developed second photoresist layer 39 as a mask. And selectively etch to form a first electrode contact hole 40, and the BSG layer 38, the epitaxial layer 34 and the buried oxide layer 33 are selectively etched in a portion where the PMOS is to be formed. The hole 41 is formed.
도 3d에서와 같이, 상기 제 2 감광막(39)을 제거하고, 상기 제 1, 제 2 전극 콘택홀(40,41)을 포함한 전면에 제 3 감광막(42)을 도포한 후, 상기 제 3 감광막(42)을 채널 영역이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 3D, the second photoresist layer 39 is removed, the third photoresist layer 42 is coated on the entire surface including the first and second electrode contact holes 40 and 41, and then the third photoresist layer is formed. The 42 is selectively exposed and developed to be removed only at the site where the channel region is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 3 감광막(42)을 마스크로 상기 NMOS가 형성될 부위에는 상기 BSG층(38)과 PSG층(37)을 선택 식각하고, 상기 PMOS가 형성될 부위에는 상기 BSG층(38)을 선택 식각한다.The BSG layer 38 and the PSG layer 37 are selectively etched in the portion where the NMOS is to be formed using the selectively exposed and developed third photoresist layer 42 as a mask, and in the portion where the PMOS is to be formed, The BSG layer 38 is selectively etched.
도 3e에서와 같이, 상기 제 3 감광막(42)을 제거하고, 상기 PSG층(37)과 BSG층(38)에 각각 주입된 인 이온과 붕소 이온이 상기 제 1 에피택셜층(34)에 주입되어 NMOS의 드레인 영역(43)과 PMOS의 드레인 영역(44)이 형성되도록 전면을 열처리한다.As shown in FIG. 3E, the third photoresist layer 42 is removed, and phosphorus ions and boron ions implanted into the PSG layer 37 and the BSG layer 38, respectively, are implanted into the first epitaxial layer 34. The entire surface is heat-treated to form the drain region 43 of the NMOS and the drain region 44 of the PMOS.
그리고, 상기 노출된 실리콘 기판(32)상의 제 1, 제 2 전극 콘택홀(40,41)과 채널 영역이 형성될 부위에 제 2 에피택셜층(45)을 성장시킨다.Then, the second epitaxial layer 45 is grown on the exposed portions of the first and second electrode contact holes 40 and 41 on the silicon substrate 32.
여기서, 상기 제 1, 제 2 전극 콘택홀(40,41)을 포함한 상기 PSG층(37)과 BSG층(38)의 선택 식각부위에 성장된 제 2 에피택셜층(45)으로 각각 NMOS, PMOS의 채널 영역(46,47)을 형성한다.Here, NMOS and PMOS are respectively formed as the second epitaxial layer 45 grown on the selective etching portions of the PSG layer 37 and the BSG layer 38 including the first and second electrode contact holes 40 and 41. Channel regions 46 and 47.
도 3f에서와 같이, 상기 PSG층(37)과 BSG층(38)을 제거하고, 상기 제 2 에피택셜층(45)을 포함한 전면에 제 4 감광막(도시하지 않음)을 도포한 후, 상기 제 4 감광막을 NMOS가 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 3F, the PSG layer 37 and the BSG layer 38 are removed, and a fourth photosensitive film (not shown) is applied to the entire surface including the second epitaxial layer 45. 4 The photoresist is selectively exposed and developed so as to be removed only at the site where the NMOS is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 4 감광막을 마스크로 실리콘 기판(32) 표면내에 p형 불순물 이온을 주입하여 p형 웰(48)을 형성하고, 상기 NMOS의 채널 영역(46) 이외의 제 2 에피택셜층(45)에 고농도 n형 불순물 이온을 주입하여 NMOS의 소오스 영역(49)을 형성한 후, 상기 제 4 감광막을 제거한다.Then, the p-type impurity ions are implanted into the surface of the silicon substrate 32 using the selectively exposed and developed fourth photoresist film to form a p-type well 48, and other than the channel region 46 of the NMOS. After the high concentration n-type impurity ions are implanted into the 2 epitaxial layer 45 to form the source region 49 of the NMOS, the fourth photoresist layer is removed.
이어, 상기 포토 공정을 반복하여 상기 PMOS가 형성될 부위의 실리콘 기판(32) 표면내에 n형 불순물 이온을 주입하여 n형 웰(50)을 형성하고, 상기 PMOS의 채널 영역(47) 이외의 제 2 에피택셜층(45)에 고농도 p형 불순물 이온을 주입하여 PMOS의 소오스 영역(51)을 형성한다.Subsequently, the photo process is repeated to form n-type wells 50 by implanting n-type impurity ions into the surface of the silicon substrate 32 at the portion where the PMOS is to be formed, and to form an n-type well 50. High concentration p-type impurity ions are implanted into the epitaxial layer 45 to form the source region 51 of the PMOS.
도 3g에서와 같이, 전면에 제 2 질화막(52)과 제 5 감광막(도시하지 않음)을 형성하고, 상기 제 5 감광막을 NMOS가 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 3G, the second nitride film 52 and the fifth photoresist film (not shown) are formed on the entire surface, and the fifth photoresist film is selectively exposed and developed to be removed only at the portion where the NMOS is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 5 감광막을 마스크로 열산화 공정에 의해 상기 노출된 제 1, 제 2 에피택셜층(34,45) 표면상에 게이트 산화막(53)을 성장시킨다.The gate oxide film 53 is grown on the exposed first and second epitaxial layers 34 and 45 by thermal oxidation using the selectively exposed and developed fifth photoresist film as a mask.
이어, 상기 게이트 산화막(53)을 포함한 전면에 n형 불순물이 주입된 제 2 다결정 실리콘층을 형성하고, 포토 공정에 의해 선택 식각하여 상기 NMOS의 채널 영역(46) 양측의 NMOS의 소오스 영역(49) 하측에 NMOS의 게이트 전극(54)을 형성한다.Subsequently, a second polycrystalline silicon layer in which n-type impurities are implanted is formed on the entire surface including the gate oxide layer 53, and is selectively etched by a photo process to form an NMOS source region 49 on both sides of the channel region 46 of the NMOS. NMOS gate electrode 54 is formed below.
여기서, 상기 게이트 산화막(53) 대신에 고 유전 상수를 갖는 탄탈늄(Ta), 하프늄(Hf) 및 지르코늄(Zr) 중 하나로 형성할 수 있다.Instead of the gate oxide film 53, one of tantalum (Ta), hafnium (Hf), and zirconium (Zr) having a high dielectric constant may be formed.
도 3h에서와 같이, 상기 제 2 질화막(52)을 제거하고, 상기 NMOS의 게이트 전극(54) 형성 공정과 동일한 방법을 반복하여 상기 PMOS의 채널 영역(47) 양측의 PMOS의 소오스 영역(51) 하측에 PMOS의 게이트 전극(55)을 형성한다.As shown in FIG. 3H, the second nitride film 52 is removed, and the same method as that of forming the gate electrode 54 of the NMOS is repeated, so that the source region 51 of the PMOS on both sides of the channel region 47 of the PMOS is repeated. On the lower side, a gate electrode 55 of the PMOS is formed.
본 발명의 CMOS 트랜지스터 및 그의 제조 방법은 채널 영역과 반도체 기판의 전기적 연결 통로인 콘택을 형성한 후 채널 영역 형성용 에피택셜층을 성장시키므로, 상기 반도체 기판이 플로팅되는 것을 방지하여 문턱 전압이 안정되고 킹크(Kink) 현상의 발생을 방지하므로 소자의 특성 및 신뢰성을 향상시키는 효과가있다.In the CMOS transistor of the present invention and a method of manufacturing the same, an epitaxial layer for forming a channel region is grown after forming a contact, which is an electrical connection passage between a channel region and a semiconductor substrate, thereby preventing the semiconductor substrate from floating, thereby stabilizing a threshold voltage. Since it prevents the occurrence of a kink phenomenon, there is an effect to improve the characteristics and reliability of the device.
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| JPH05121681A (en) * | 1991-10-25 | 1993-05-18 | Nec Corp | Manufacture of cmos circuit element and soi mos fet |
| JPH05243510A (en) * | 1992-02-29 | 1993-09-21 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| JPH06244365A (en) * | 1993-02-15 | 1994-09-02 | Hitachi Ltd | Semiconductor device, and manufacture thereof |
| JPH06342885A (en) * | 1993-06-01 | 1994-12-13 | Matsushita Electron Corp | Manufacture of cmos semiconductor integrated circuit |
| JPH08222705A (en) * | 1995-02-14 | 1996-08-30 | Hitachi Ltd | Complementary semiconductor device |
| US5883396A (en) * | 1993-07-12 | 1999-03-16 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121681A (en) * | 1991-10-25 | 1993-05-18 | Nec Corp | Manufacture of cmos circuit element and soi mos fet |
| JPH05243510A (en) * | 1992-02-29 | 1993-09-21 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| JPH06244365A (en) * | 1993-02-15 | 1994-09-02 | Hitachi Ltd | Semiconductor device, and manufacture thereof |
| JPH06342885A (en) * | 1993-06-01 | 1994-12-13 | Matsushita Electron Corp | Manufacture of cmos semiconductor integrated circuit |
| US5883396A (en) * | 1993-07-12 | 1999-03-16 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
| JPH08222705A (en) * | 1995-02-14 | 1996-08-30 | Hitachi Ltd | Complementary semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100446933B1 (en) * | 2001-02-19 | 2004-09-01 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device |
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