KR100334529B1 - Capacitor Formation Method of Semiconductor Device - Google Patents
Capacitor Formation Method of Semiconductor Device Download PDFInfo
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- KR100334529B1 KR100334529B1 KR1019980058654A KR19980058654A KR100334529B1 KR 100334529 B1 KR100334529 B1 KR 100334529B1 KR 1019980058654 A KR1019980058654 A KR 1019980058654A KR 19980058654 A KR19980058654 A KR 19980058654A KR 100334529 B1 KR100334529 B1 KR 100334529B1
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- film
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- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000003990 capacitor Substances 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 230000015572 biosynthetic process Effects 0.000 title claims description 4
- 238000003860 storage Methods 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 54
- 230000004888 barrier function Effects 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910008482 TiSiN Inorganic materials 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 229910004491 TaAlN Inorganic materials 0.000 claims description 2
- 229910004200 TaSiN Inorganic materials 0.000 claims description 2
- 229910010037 TiAlN Inorganic materials 0.000 claims description 2
- 125000002524 organometallic group Chemical group 0.000 claims description 2
- 239000010970 precious metal Substances 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- QRDJMFAGNINQFN-UHFFFAOYSA-N CC[Ti](N)CC Chemical compound CC[Ti](N)CC QRDJMFAGNINQFN-UHFFFAOYSA-N 0.000 description 1
- QDGMSMUNXGCWRA-UHFFFAOYSA-N C[Ti](C)N Chemical compound C[Ti](C)N QDGMSMUNXGCWRA-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, Ta2O5막을 유전체막으로 사용하는 캐패시터에서 하부전극 및 상부전극을 Pt계의 금속층으로 형성하여 상기 Ta2O5막의 유효산화막의 두께를 감소시켜 캐패시터의 전기적 특성을 향상시키고, 코아절연막을 사용하여 원하는 높이의 귀금속 저장전극을 형성함으로써 저장전극의 표면적을 증가시키는 동시에 공정을 단순화시키며 그에 따른 반도체소자의 신뢰성 및 수율을 향상시키는 기술이다.The present invention relates to a method for forming a capacitor of a semiconductor device, in which a lower electrode and an upper electrode are formed of a Pt-based metal layer in a capacitor using a Ta 2 O 5 film as a dielectric film to reduce the thickness of the effective oxide film of the Ta 2 O 5 film. By improving the electrical characteristics of the capacitor, and forming a precious metal storage electrode of the desired height by using a core insulating film to increase the surface area of the storage electrode while simplifying the process, thereby improving the reliability and yield of the semiconductor device.
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로서, 특히 유전체막으로 Ta2O5막을 사용하는 캐패시터 형성공정에서 전극물질로 Pt계 금속층을 사용하는 경우 코아절연막을 사용하여 원하는 높이의 저장전극을 형성함으로써 공정을 단순화시키고, 단차를 감소시키며 캐패시터의 전기적 특성을 개선시켜 그에 따른 반도체소자의 특성 및 수율을 향상시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device. In particular, when a Pt-based metal layer is used as an electrode material in a capacitor forming process using a Ta 2 O 5 film as a dielectric film, a storage electrode having a desired height is formed using a core insulating film. As a result, the present invention relates to a method for simplifying a process, reducing a step, and improving an electrical property of a capacitor, thereby improving characteristics and yield of a semiconductor device.
최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.
특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자에서는 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막의 두께를 얇게하거나 또는 전하저장전극의 표면적을 증가시키는 등의 방법이 있다.In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.
도시되어 있지는 않지만, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 살펴보면 다음과 같다.Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.
먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터 및 비트라인을 형성한 후, 상기 구조의 전표면에 층간절연막을 형성한다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, a MOS field effect transistor and a bit line including a gate electrode and a source / drain electrode are formed, and then an interlayer insulating film is formed on the entire surface of the structure.
그 다음 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분 상측의 층간절연막을 제거하여 전하저장전극 콘택홀을 형성하고, 상기 콘택홀을 통하여 소오스/드레인전극과 접촉되는 전하저장전극을 다결정실리콘층 패턴으로 형성한 후, 상기 전하저장전극의 표면에 산화막이나 질화막 또는 산화막-질화막-산화막의 적층구조로된 유전체막을 형성하고, 상기 유전체막상에 플레이트전극을 형성하여 캐패시터를 완성한다.Next, a charge storage electrode contact hole is formed by removing an interlayer insulating layer on an upper portion of the source / drain electrode, which is intended to be a charge storage electrode contact, and polycrystalline a charge storage electrode contacting the source / drain electrode through the contact hole. After forming a silicon layer pattern, a dielectric film having an oxide film, a nitride film, or an oxide film-nitride film-oxide film laminated structure is formed on the surface of the charge storage electrode, and a plate electrode is formed on the dielectric film to complete the capacitor.
상기와 같은 종래기술에 따른 반도체소자의 캐패시터에서 유전체막은 고유전율, 저누설전류밀도, 높은 절연파괴전압 및 상하측 전극과의 안정적인 계면특성 등이 요구되는데, 상기 산화막은 유전상수가 약 3.8 정도이고 질화막은 약 7.2 정도로 비교적 작고, 전극으로 사용되는 다결정실리콘층은 비저항이 800 ∼ 1000μΩ㎝ 정도로 비교적 높아 정전용량이 제한된다.In the capacitor of the semiconductor device according to the prior art as described above, the dielectric film requires high dielectric constant, low leakage current density, high dielectric breakdown voltage, and stable interfacial characteristics with the upper and lower electrodes. The oxide film has a dielectric constant of about 3.8. The nitride film is relatively small at about 7.2, and the polysilicon layer used as the electrode has a relatively high resistivity of about 800 to 1000 mu OMEGA cm.
따라서, 캐패시터의 정전용량을 증가시키기 위하여 기가 비트(giga bit)의 DRAM용 유전체막으로 Ta2O5막과 같은 고유전체막을 사용한다. 상기 Ta2O5막을 이용하여 작은 셀면적에서 충분한 정전용량을 확보하기 위하여 저장전극을 실린더형으로 형성하고, 또 표면적을 증가시키기 위하여 반구형 실리콘(hemispherical silicon, HSG)을 형성하기도 한다.Therefore, in order to increase the capacitance of the capacitor, a high dielectric film such as a Ta 2 O 5 film is used as a gigabit DRAM dielectric film. The Ta 2 O 5 film is used to form a storage electrode in a cylindrical shape to secure sufficient capacitance at a small cell area, and to form a hemispherical silicon (HSG) to increase the surface area.
그러나, 다결정실리콘층/Ta2O5/TiN 적층구조의 캐패시터를 형성하는 경우, 상기 다결정실리콘층과 Ta2O5막의 사이에 필연적으로 존재하게 되는 산화막 때문에 Ta2O5막의 유효산화막 두께가 30 ∼ 35Å 범위의 높은 값을 가지게 된다. 그러나, 내산화성이 우수한 귀금속인 Pt 또는 Ir 등을 전극물질로 사용하면 Ta2O5막의 유효산화막 두께를 10 ∼ 15Å으로 낮출 수 있다.However, when a capacitor having a polycrystalline silicon layer / Ta 2 O 5 / TiN laminated structure is formed, an effective oxide film thickness of the Ta 2 O 5 film is 30 because of an oxide film that is inevitably present between the polysilicon layer and the Ta 2 O 5 film. It has a high value in the range of ˜35 kHz. However, when Pt or Ir, which is a noble metal having excellent oxidation resistance, is used as the electrode material, the effective oxide film thickness of the Ta 2 O 5 film can be reduced to 10 to 15 kPa.
그러나, 상기 Pt 또는 Ir은 화학적으로 매우 안정한 물질이고, 식각공정시 생성되는 부산물의 증기압이 낮아 쉽게 제거되지 않으므로 75°이상의 식각면을 얻는 것이 어렵기 때문에 0.2㎛ 이하의 스페이스를 갖는 패턴에서 0.5 ∼ 1.0㎛의 높이를 갖는 저장전극을 형성하기 어려운 문제점이 있다.However, Pt or Ir is a chemically very stable material, and since the vapor pressure of by-products generated during the etching process is low, it is not easily removed, so it is difficult to obtain an etching surface of 75 ° or more, and thus 0.5 to 0.5 in a pattern having a space of 0.2 μm or less. It is difficult to form a storage electrode having a height of 1.0 μm.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, Ta2O5또는 BST((Ba1-xSRx)TiO3) 재질의 막을 유전체막으로 사용하는 캐패시터 형성방법에서 Pt계의 금속층을 전극물질로 사용하되, 코아절연막을 이용하여 원하는 높이의 저장전극을 형성하여 반도체소자의 고집적화를 가능하게 하고, 상기 유전체막과 저장전극 사이에 형성되는 유효산화막의 두께를 감소시켜 캐패시터의 전기적 특성을 개선하여 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a Pt-based metal layer is formed in a capacitor forming method using a Ta 2 O 5 or BST ((Ba 1 - x SR x ) TiO 3 ) film as a dielectric film. Using as a material, using a core insulating film to form a storage electrode having a desired height to enable high integration of the semiconductor device, and to reduce the thickness of the effective oxide film formed between the dielectric film and the storage electrode to improve the electrical characteristics of the capacitor Accordingly, an object of the present invention is to provide a method of forming a capacitor of a semiconductor device, thereby improving the characteristics and reliability of the semiconductor device.
도 1 내지 도 8 는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 나타낸 단면도.1 to 8 are cross-sectional views showing a capacitor forming method of a semiconductor device according to the present invention.
〈 도면의 주요부분에 대한 부호 설명 〉〈Explanation of the Signs of Major Parts of Drawings〉
11 : 반도체기판 13 : 층간절연막11 semiconductor substrate 13 interlayer insulating film
15 : 저장전극 콘택 플러그 17 : 제1확산방지막15: storage electrode contact plug 17: first diffusion barrier
19 : 제2확산방지막 21 : 코아절연막19: second diffusion barrier film 21: core insulation film
23 : 접착층 25 : 하부전극용 금속층23: adhesive layer 25: metal layer for the lower electrode
27 : 고유전체막 29 : 상부전극용 금속층27: high dielectric film 29: metal layer for the upper electrode
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성방법은,In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택플러그가 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate having a predetermined lower structure formed thereon;
상기 층간절연막 상부에 상기 저장전극 콘택플러그와 접속되는 확산방지막을 형성하는 공정과,Forming a diffusion barrier layer on the interlayer dielectric layer and connected to the storage electrode contact plugs;
저장전극 마스크를 이용하여 상기 확산방지막을 식각하는 공정과,Etching the diffusion barrier layer using a storage electrode mask;
상기 확산방지막 상부에 상기 확산방지막의 양쪽 가장자리를 소정 두께 노출시키는 코아절연막을 형성하는 공정과,Forming a core insulating film on the diffusion barrier to expose both edges of the diffusion barrier to a predetermined thickness;
전체표면 상부에 접착층과 하부전극용 제1금속층을 순차적으로 형성하는 공정과,Sequentially forming an adhesive layer and a first metal layer for the lower electrode on the entire surface;
상기 하부전극용 제1금속층과 접착층을 전면식각공정으로 식각하여 상기 코아절연막의 측벽에 제1금속층 스페이서를 형성하는 공정과,Forming a first metal layer spacer on a sidewall of the core insulating layer by etching the first metal layer and the adhesive layer for the lower electrode by a front etching process;
전체표면 상부에 Ta2O5막 또는 BST((Ba1-xSRx)TiO3) 재질의 고유전체막과 상부전극용 제2금속층을 순차적으로 형성하는 공정과,Sequentially forming a Ta 2 O 5 film or a high dielectric film of BST ((Ba 1 - x SR x ) TiO 3 ) material on the entire surface and a second metal layer for the upper electrode;
급속열처리 및 관상 열처리하는 공정을 포함하는 것을 특징으로 한다.It is characterized by including a step of rapid heat treatment and tubular heat treatment.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1 내지 도 8 은 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1 to 8 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.
먼저, 반도체기판(11)에 소자분리 절연막(도시안됨), 게이트산화막(도시안됨), 게이트전극(도시안됨) 및 비트라인(도시안됨) 등의 하부구조물을 형성한다.First, lower structures such as an isolation layer (not shown), a gate oxide layer (not shown), a gate electrode (not shown), and a bit line (not shown) are formed on the semiconductor substrate 11.
다음, 전체표면에 층간절연막(13)을 형성한다.Next, the interlayer insulating film 13 is formed on the entire surface.
그 다음, 저장전극 콘택마스크를 식각마스크로 이용하여 상기 층간절연막(13)을 식각하여 저장전극 콘택홀(도시안됨)을 형성한다.Next, the interlayer insulating layer 13 is etched using the storage electrode contact mask as an etching mask to form a storage electrode contact hole (not shown).
다음, 상기 층간절연막(13) 상부에 상기 저장전극 콘택홀을 매립하는 다결정실리콘층을 형성한다. 이때, 상기 다결정실리콘층은 화학기상증착(chemical vapor deposition, CVD)방법을 사용하여 500 ∼ 3000Å 두께로 형성한다.Next, a polysilicon layer is formed on the interlayer insulating layer 13 to fill the storage electrode contact hole. At this time, the polysilicon layer is formed to a thickness of 500 ~ 3000Å by chemical vapor deposition (CVD) method.
그리고, 상기 다결정실리콘층을 전면식각 또는 화학기계적 연마(chemical mechanical polishing, CMP)공정을 제거하여 저장전극 콘택플러그(15)를 형성한다. (도 1참조)The storage silicon contact plug 15 is formed by removing the entire surface etching or chemical mechanical polishing (CMP) process of the polysilicon layer. (See Fig. 1)
그 다음, 상기 층간절연막(13) 상부에 상기 저장전극 콘택플러그(15)와 접속되는 제1확산방지막(17)과 제2확산방지막(19)을 형성한다. 이때, 상기 제1확산방지막(17)은 Ti막으로 100 ∼ 1000Å 두께 형성하고, 상기 제2확산방지막(19)은 TiSiN막으로 200 ∼ 1000Å 두께 형성한다. 상기 제2확산방지막(19)은 상기 TiSiN막 이외에도 TiAlN막, TaSiN막 또는 TaAlN막으로 형성할 수 있다. (도 2참조)Next, a first diffusion barrier 17 and a second diffusion barrier 19 are formed on the interlayer insulating layer 13 to be connected to the storage electrode contact plug 15. At this time, the first diffusion barrier 17 is formed of a Ti film 100 ~ 1000 Å thick, the second diffusion barrier 19 is formed of a TiSiN film 200 ~ 1000 Å thick. The second diffusion barrier 19 may be formed of a TiAlN film, a TaSiN film, or a TaAlN film in addition to the TiSiN film. (See Fig. 2)
다음, 상기 저장전극 콘택플러그(15)보다 넓은 영역을 보호하되, 저장전극으로 예정되는 부분을 보호하는 저장전극 마스크를 이용하여 상기 제2확산방지막(19)과 제1확산방지막(17)을 식각한다. (도 3참조)Next, the second diffusion barrier 19 and the first diffusion barrier 17 are etched using a storage electrode mask that protects a wider area than the storage electrode contact plug 15 and protects a portion intended as the storage electrode. do. (See Fig. 3)
그 다음, 전체표면 상부에 코아절연막(21)을 형성한다. 여기서, 상기 코아절연막(21)은 산화막, 피.에스.지.(phospho silicate glass, 이하 PSG 라 함), 비.피.에스.지.(borophospho silicate glass, 이하 BPSG 라 함) 또는 질화막을 이용하여 3000 ∼ 15000Å 두께로 형성한다. (도 4참조)Next, a core insulating film 21 is formed over the entire surface. Here, the core insulation layer 21 may be formed of an oxide film, phospho silicate glass (hereinafter referred to as PSG), borophospho silicate glass (hereinafter referred to as BPSG) or nitride film. To form a thickness of 3000 ~ 15000Å. (See Fig. 4)
다음, 상기 코아절연막(21) 상부에 상기 제2확산방지막(19)에서 저장전극으로 예정되는 부분을 보호하는 감광막 패턴(도시안됨)을 형성한다.Next, a photoresist pattern (not shown) is formed on the core insulation layer 21 to protect a portion of the second diffusion barrier layer 19 as a storage electrode.
그 다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 코아절연막(21)을 건식식각방법으로 제거한 후, 상기 감광막 패턴을 제거한다. (도 5참조)Next, the core insulation layer 21 is removed by a dry etching method using the photoresist pattern as an etching mask, and then the photoresist pattern is removed. (See Fig. 5)
다음, 전체표면 상부에 상기 코아절연막(21)과 후속 공정으로 형성되는 하부전극과의 접착성을 향상시키는 접착층(23)을 화학기상증착방법으로 형성한다. 이때, 상기 접착층(23)은 TiCl4/NH3또는 테트라 디-메틸 아미노 티타늄(tetra di-methyl amino titanium, TDMAT) 또는 테트라 디-에틸 아미노 티타늄(tetra di-ethyl amino titanium, TDMET)를 사용하여 TiN막을 200 ∼ 500Å 두께로 형성하거나, 상기 TiN막 대신 Ti 또는 WN막으로 형성할 수 있다.Next, an adhesion layer 23 is formed on the entire surface of the core insulating layer 21 to improve adhesion between the core insulating layer 21 and the lower electrode formed by a subsequent process by chemical vapor deposition. At this time, the adhesive layer 23 using TiCl 4 / NH 3 or tetra dimethyl amino titanium (TDMAT) or tetra di-ethyl amino titanium (TDMET) The TiN film may be formed to a thickness of 200 to 500 GPa, or may be formed of a Ti or WN film instead of the TiN film.
다음, 상기 접착층(23) 상부에 하부전극용 금속층(25)을 유기금속화학기상증착(metal organic chemical vapor deposition, MOCVD)방법으로 200 ∼ 1000 Å 증착한다. 상기 하부전극용 금속층(25)은 Pt막, Ir막, Ru막 Iro2막 또는 RuO2막 등의 금속층을 사용하여 형성할 수 있다. (도 6참조)Next, the lower electrode metal layer 25 is deposited on the adhesive layer 23 by 200 to 1000 kPa by a metal organic chemical vapor deposition (MOCVD) method. The lower electrode metal layer 25 may be formed using a metal layer such as a Pt film, an Ir film, a Ru film, an Iro 2 film, or a RuO 2 film. (See FIG. 6)
그 다음, 상기 하부전극용 금속층(25) 및 접착층(23)을 전면식각하여 상기 코아절연막(21)의 측벽에 상부가 분리된 스페이서를 형성한다. (도 7참조)Next, the lower electrode metal layer 25 and the adhesive layer 23 are etched entirely to form a spacer having an upper portion separated from the sidewall of the core insulating layer 21. (See Fig. 7)
다음, 전체표면 상부에 화학기상증착 방법으로 고유전체막(27)을 형성한다. 상기 고유전체막(27)으로 Ta2O5막 또는 BST((Ba1-xSrx)TiO3)막을 사용하여 형성할 수 있다. 상기 고유전체막(27)은 화학기상증착방법을 사용하여 300 ∼ 450℃에서 50 ∼ 200Å 두께로 형성한다.Next, a high dielectric film 27 is formed on the entire surface by chemical vapor deposition. The high dielectric film 27 may be formed using a Ta 2 O 5 film or a BST ((Ba 1-x Sr x ) TiO 3 ) film. The high dielectric film 27 is formed to have a thickness of 50 to 200 Å at 300 to 450 ° C. using a chemical vapor deposition method.
그 다음, 상기 고유전체막(27) 상부에 상부전극용 금속층(29)을 유기금속화학기상증착방법을 사용하여 200 ∼ 500℃에서 200 ∼ 1000Å 두께로 형성한다. 상기 상부전극용 금속층(29)은 Pt막, Ir막, Ru막 Iro2막, RuO2막, TiN막 또는 WN막 등의 금속층으로 형성할 수 있다. (도 8참조)Next, the upper electrode metal layer 29 is formed on the high dielectric film 27 to a thickness of 200 to 1000 Å at 200 to 500 ° C. using an organometallic chemical vapor deposition method. The upper electrode metal layer 29 may be formed of a metal layer such as a Pt film, an Ir film, a Ru film, an Iro 2 film, a RuO 2 film, a TiN film, or a WN film. (See FIG. 8)
그 후, 급속열처리(rapid thermal anneal) 공정 및 관상 열처리(furnace anneal)공정을 실시하여 반도체소자의 캐패시터 형성공정을 완료한다.Thereafter, a rapid thermal anneal process and a tubular anneal process are performed to complete the capacitor formation process of the semiconductor device.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, Ta2O5막을 유전체막으로 사용하는 캐패시터에서 하부전극 및 상부전극을 금속층을 사용하여 Ta2O5막의 유효산화막의 두께를 감소시킴으로써 캐패시터의 전기적 특성을 향상시키는 동시에 셀부와 페리부의 단차를 감소시키고, 코아절연막을 사용하여 원하는 높이의 금속 저장전극을 형성함으로써 고집적 반도체소자에서 저장전극의 표면적을 증가시키는 동시에 공정을 단순화시키며 그에 따른 반도체소자의 신뢰성 및 수율을 향상시키는 이점이 있다.As described above, in the capacitor forming method of the semiconductor device according to the present invention, in the capacitor using the Ta 2 O 5 film as the dielectric film, the thickness of the effective oxide film of the Ta 2 O 5 film is reduced by using the lower electrode and the upper electrode as the metal layer. This improves the electrical characteristics of the capacitor and reduces the step between the cell and ferry sections. The core insulating film is used to form metal storage electrodes of desired height, thereby increasing the surface area of the storage electrodes in highly integrated semiconductor devices and simplifying the process. There is an advantage of improving the reliability and yield of the semiconductor device.
Claims (11)
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| JPH1012844A (en) * | 1996-06-27 | 1998-01-16 | Hitachi Ltd | Semiconductor storage device and its manufacture |
| JPH10284699A (en) * | 1997-04-07 | 1998-10-23 | Mitsubishi Electric Corp | Manufacture of semiconductor memory device |
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