KR100321756B1 - Register Delay locked loop operating in high frequency - Google Patents

Abstract

The present invention relates to a delay locked loop of a semiconductor memory device, and implements a delay locked loop operating at a high frequency of 200 MHz or more by removing a limitation on a clock cycle time of a delay model of a conventional register delay locked loop. To this end, the present invention provides a semiconductor memory device, comprising: an input buffer for receiving and buffering an external clock; A clock divider configured to receive an internal clock signal from an input buffer and generate a pulse corresponding to one clock cycle; A delay model unit configured to receive a signal fed back from the delay monitor and generate a delay signal equal to a delay to be compensated for; A frequency detector configured to receive an output signal of the delay model unit and an output signal of the clock divider to detect whether high frequency or low frequency is present; A selector for receiving the output of the clock divider and the output of a frequency detector and selecting one of one clock cycle pulse and two clock cycle pulses; A setup time delay unit configured to compensate for a frequency detection error of a frequency detector by receiving an output signal of a selector and an output of the input buffer; A phase comparator for receiving the delay model unit and the output of the clock divider and comparing rising edges of two signals; A phase shift controller for controlling the shift of the delay monitor to the left or the right by receiving the control signal from the phase comparator; A delay monitor for adjusting delay in response to an output from the phase shift controller, an output from the phase divider, and an output from the input buffer; And an output buffer for receiving the output from the input buffer and the output from the delay monitor to generate a delay locked loop clock.

Description

Register Delay locked loop operating in high frequency

The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop.

In general, a delay locked loop is a circuit used to make an internal clock of a synchronous memory using a clock coincide with an external clock without error. That is, a timing delay occurs when an external clock is used internally. This timing delay is used to control the internal clock to be synchronized with an external clock.

Fig. 1A is a timing diagram when no delay lock loop is used.

Referring to FIG. 1A, a delay locked loop principle is described. When data is output in synchronization with an external clock clk, a delay as much as tAC is generated, and a window of valid data is reduced as much as tAC. This delay is not very important at low frequencies because the window width of valid data is wide, but it is an important problem at high frequencies.

Fig. 1B is a timing diagram when a delay locked loop is used.

Referring to FIG. 1B, a delay locked loop clock DLL clk is made by delaying the external clock clk by tSHIFT. The delay locked loop clock DLL clk is a clock that advances by tAC based on the next external clock. Therefore, when data is synchronized to the delay locked loop clock DLL clk, tAC can be improved by outputting data at the edge of the external clock clk. The relationship between the tSHIFT and tAC is as follows.

tSHIFT = tCK (one clock cycle)-tAC (tSHIFT ≥ 0)

2 is a block diagram of a register delay locked loop of the prior art.

Referring to FIG. 2, the register delay lock loop according to the related art has an input buffer 200 for receiving and buffering an external clock, and a pulse corresponding to one clock cycle by receiving an internal clock signal from the input buffer 200. A clock divider 210 for generating a delay signal, a delay model unit 220 for generating a delay equal to a delay to be compensated by receiving a signal fed back from the delay monitor 250, the delay model unit 220, and the delay model unit 220. A phase comparator 230 for receiving the output of the clock divider 210 to compare the rising edges of the two signals and a control signal from the phase comparator are input to shift the delay of the delay monitor 250 to the left or the right. Phase shift controller 240, an output from the phase shift controller 240, an output from the phase divider, and an output from the input buffer. In response to the output, the delay monitor 250 for adjusting the delay, a power-up signal pwrup, a delay locked loop deactivation signal dis_dll, a cell refresh signal selfrefd, and a delay locked loop preset signal dll_resetb are received. A delay locked loop motor 260 for activating the input buffer 200 and controlling the delay monitor 250, and an output from the input buffer 200 and an output from the delay monitor 250. And an output buffer 270 for generating a delay locked loop clock.

Figure 3 is a timing diagram for the register delay locked loop of the prior art.

Referring to FIG. 3, the rising edge of the output signal dlic4z_r of the clock divider generated in the external clock is compared with the rising edge of the signal dlic7_r fed back through the delay. When the rising edges of the two signals coincide, the delay locked loop is locked, and the delay locked loop clock is advanced by tAC with respect to the external clock.

Fig. 4 is a timing diagram showing a problem for the register delay locked loop of the prior art.

Referring to FIG. 4, there is a limit of an operating range with respect to the external clock cycle time tCK. That is, at high frequencies where tDM (delay to compensate)> tCK (one clock cycle), the delay lock loop does not operate normally. The reason for this is as follows. As shown in the figure, the signal dlic7_r needs to be shifted to the left in order for the delay locked loop to be locked. However, the signal cannot be shifted to the left because no delay unit is passed through the delay monitor 250 (tSHIFT = 0). If tDM> tCK then tSHIFT <0 so the above condition tSHIFT You can see a deviation of ≥ 0.

Therefore, at high frequencies where the delay to be compensated is greater than one clock cycle, there is a limit on the operating frequency. That is, a problem occurs that the delay locked loop does not operate normally at a frequency of tCK smaller than tDM, that is, higher than 1 / tDM.

An object of the present invention is to provide a register delay locked loop that can operate even when a delay to be compensated at a high frequency is greater than one clock cycle.

Fig. 1A is a timing diagram when no delay lock loop is used.

1B is a timing diagram when a delay locked loop is used;

2 is a block diagram of a register delay locked loop of the prior art;

3 is a timing diagram for a register delay locked loop of the prior art;

4 is a timing diagram showing a problem with a register delay locked loop of the prior art;

5 is an algorithm showing the technical principle of the present invention;

6 is a block diagram of a register delay locked loop of the present invention;

7 is a detailed circuit diagram of the frequency detector of the present invention;

8 is a detailed circuit diagram of the frequency detection terminating portion of the present invention;

9 is a timing diagram showing the signal flow of the frequency detector at low frequency;

10 is a timing diagram showing a signal flow of a frequency detector at high frequency;

11 is a timing diagram of a setup time delay unit of the present invention;

12 is a detailed circuit diagram of a setup time delay unit of the present invention;

Fig. 13 is a timing diagram showing a simulation result of a register delay locked loop of the present invention.

Explanation of symbols on the main parts of the drawings

600: clock divider 610: selector

620: frequency detector 630: setup time delay unit

In order to achieve the above object, the register delay lock loop of the present invention comprises: an input buffer for receiving and buffering an external clock; A clock divider configured to receive an internal clock signal from an input buffer and generate a pulse corresponding to one clock cycle; A delay model unit configured to receive a signal fed back from the delay monitor and generate a delay signal equal to a delay to be compensated for; A frequency detector configured to receive an output signal of the delay model unit and an output signal of the clock divider to detect whether high frequency or low frequency is present; A selector for receiving the output of the clock divider and the output of a frequency detector and selecting one of one clock cycle pulse and two clock cycle pulses; A setup time delay unit configured to compensate for a frequency detection error of a frequency detector by receiving an output signal of a selector and an output of the input buffer; A phase comparator for receiving the delay model unit and the output of the clock divider and comparing rising edges of two signals; A phase shift controller for controlling the shift of the delay monitor to the left or the right by receiving the control signal from the phase comparator; A delay monitor for adjusting delay in response to an output from the phase shift controller, an output from the phase divider, and an output from the input buffer; And an output buffer for receiving the output from the input buffer and the output from the delay monitor to generate a delay locked loop clock.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

5 is an algorithm diagram illustrating the technical principle of the present invention.

Referring to FIG. 5, an external clock is divided into high frequency and low frequency using tDM, which is a delay value of the delay model 220, as a reference. In the case of the curse file, a comparison is made to 1 tCK (one clock cycle) as in the conventional register delay locked loop, and to 2 tCK at a high frequency. This can solve the problem of tDM> tCK.

6 is a block diagram of a register delay locked loop of the present invention.

Referring to FIG. 6, the register delay lock loop generates an input buffer 200 for receiving and buffering an external clock and an internal clock signal from the input buffer 200 to generate a pulse corresponding to one clock cycle. A delay model unit 220 for generating a clock divider 600, a delay signal dlic7_r corresponding to a delay to be received by the signal fed back from the delay monitor 250, and an output signal of the delay model unit 220. A clock which receives a frequency detector 620 for detecting a high frequency and a low frequency by receiving dlic7_r and the output signal dlic4z_r of the clock divider, and an output of the clock divider 600 and an output of the frequency detector 620. A selector 610 for selecting one of a cycle pulse and two clock cycle pulses, an output signal dlic5z_r of the selector and an output of the input buffer, A setup time delay unit 630 for compensating for frequency detection error, and a phase comparator 230 for comparing the rising edges of the two signals by receiving the outputs of the delay model unit 220 and the clock divider 600. And a phase shift controller 240 for controlling the shift of the delay monitor 250 to the left or the right by receiving a control signal from the phase comparator, an output from the phase shift controller 240, and A delay monitor 250 for adjusting the delay in response to an output from the phase divider and an output from the input buffer, a power-up signal pwrup, a delay locked loop disable signal dis_dll, and a cell refresh signal selfrefd And a delay locked loop actuator 260 for receiving the delay locked loop preset signal dll_resetb to activate the input buffer 200 and to control the setup time delay unit 630. It receives input from the output of the delay output and the monitor 250 from the input buffer group 200, and a output buffer 270 for generating a delay-locked loop clock.

7 is a detailed circuit diagram of the frequency detector 620.

Referring to FIG. 7, the frequency detector 620 receives the output signal dlic7_r and the enable signal (enable) of the delay model unit 220 and controls the frequency detection termination unit 621 to control that the frequency detection is completed. A first NAND gate 622 and the first NAND gate that negatively multiply the output of the frequency detection termination unit 621, the output signal dlic4z_r of the clock divider 600, and the output signal dlic7_r of the delay model unit 220. A pulse generator 623 for generating a pulse by receiving the output of the first latch, a first latch stage 624 for latching the signal dlic4z_r and the signal dlic7_r, and an output of the first latch stage 624; Second and third NAND gates 625 and 626 that are negative logic multiplied by the output of the pulse generation stage 623, and second latch stages that receive and latch the outputs of the second and third NAND gates ( 627).

Initially, if enable is logic low, output signal low is logic high. Thus, the frequency detector initially detects low frequencies. That is, at the beginning of the locking, the register delay lock loop operates in the same manner as the conventional one, and compares the signal dlic4z_r with the signal dlic7_r to detect whether the low frequency and the high frequency are high. If the rising edge of the signal dlic4z_r is to the right of the rising edge of the signal dlic7_r, the signal is detected at low frequency. If the rising edge of the signal dlic4z_r is to the left of the rising edge of the signal dlic7_r, the signal is detected at high frequency. Since the detection only needs to be performed once, the frequency detection termination unit 621 prevents further detection after the detection is completed.

8 is a detailed circuit diagram of the frequency detection termination unit 621. FIG.

Referring to FIG. 8, the frequency detection termination unit 621 includes a first latch stage 650 for receiving and latching the enable signal, a first inverter 656 for inverting the signal dlic7_r, Two enMOS transistors 653 connected to the first output node of the first latch terminal and the ground terminal and receiving the output of the enable signal and the first inverter 656 and the enable signal (enable) ) Is a second latch stage 651 for receiving and latching, two second outputs of the first latch stage and the signal dlic7_r, which are connected in series between a third output node of the second latch stage and a ground terminal. An n-MOS transistor 654, a third latch stage 652 for receiving and latching the enable signal, a second inverter 657 for inverting the signal dlic7_r, and a second latch stage. Four outputs and an output of the second inverter 657 are input, and between the fifth output node of the third latch stage and the ground terminal. Column and two NMOS transistors 655 are connected, are series-connected to said fifth output node, and having an even number of inverters (658) for generating an output signal DTCT_STOP_B.

When the enable signal is logic low, the second output node Q0, the fourth output node Q1, and the sixth output node Q2 of the third latch stage are mode logic low, and the signal dlic7_r is logic. The value of the second output node Q0, the fourth output node Q1, and the sixth output node Q2 are sequentially shifted to logic high as the logic is changed from low to logic high. When the fourth output node Q1 is logic high, the output signal DTCT_STOP_B becomes logic low to stop detection. The detection is performed at the rising edge of the signal dlic7_r and the detection termination is performed at the next falling edge, thus ensuring sufficient time margin for detection.

9 is a timing diagram showing the signal flow of the frequency detector 620 at low frequency.

Referring to FIG. 9, when the enable signal is enabled at a logic high and the rising edge of the signal REF (dlic4z_r) is located to the right of the rising edge of IN (dlic7_r), it is detected as a low frequency and is an output signal of the frequency detector. Keep (LOW) at a logic high. In this state, the output signal C3 of the pulse generator 623 generates a pulse, and the output signal DTCT_STOP_B of the frequency detection termination unit 621 goes down from logic high to logic low to indicate that frequency detection is completed.

10 is a timing diagram showing the signal flow of the frequency detector 620 at high frequency.

Referring to FIG. 10, when the enable signal is enabled at a logic high and the rising edge of the signal REF (dlic4z_r) is located to the left of the rising edge of IN (dlic7_r), it is detected as a high frequency and is an output signal of the frequency detector. Move (LOW) from logic high to logic low. In this state, the output signal C3 of the pulse generator 623 generates a pulse, and the output signal DTCT_STOP_B of the frequency detection termination unit 621 goes down from logic high to logic low to indicate that frequency detection is completed.

11 is a timing diagram of the setup time delay unit 630.

Referring to FIG. 11, when the delay tDM to be compensated is similar to tCK (one clock cycle), there is a possibility that an error is detected in the detection of low frequency and high frequency due to external factors such as temperature or voltage change. When the low frequency is detected at a high frequency, the value of tSHIFT is larger by tCK than the actual time, and the time until the delay locked loop is locked is long, but it is not a big problem for normal operation. However, if an error of detecting a high frequency at a low frequency occurs, a problem such as the register delay locked loop of the prior art shown in FIG. 4 occurs. In order to solve this problem of detection, a margin of tSD (set-up delay) was set. That is, the signal dlic5z_r is further delayed by tSD and the signal dlic7_r is compared with the signal dlic4z_r.

For example, assuming that tDM = 4 nanoseconds and tSD = 1 nanosecond, the frequency detector detects at a low frequency when tCK> (tDM + tSD), that is, tCK> 5 nanoseconds. If tSD is not present, the frequency detector will detect low frequencies from tCK> 4 nanoseconds.

12 is a detailed circuit diagram of the setup time delay unit 630.

12, a latch stage 1200 for latching in response to an output of the delay locked loop actuator 260 and an output of the phase shift controller 240, and an output signal dlic5z_r of the selector 610; A NAND gate 1210 that receives the output of the latch stage 1200 and performs a negative logic multiplication, and a unit delay 1220 that performs a time delay in response to the output of the NAND gate 1210 and the output of the previous unit delay. It is provided with a basic configuration as described above, the basic configuration is a plurality of series connected.

Fig. 13 is a timing diagram showing a simulation result of a register delay locked loop of the present invention.

Referring to FIG. 13, the frequency detector detects a low frequency as an initial value. The output signal low of the frequency detector drops from logic high to logic low at the moment it is detected. Comparing the signal dlic4z_r with the signal dlic7_r when the signal low is logic high, it can be seen that the signal dlic7_r is on the right side. Therefore, the frequency detector detects a high frequency and the signal low becomes a logic low. At this time, the signal dlic5z_r is 2tCK (two clock cycles) to the left of the rising edge of the signal dlic4z_r, as shown by a thick dotted line in FIG. That is, locking is performed during 2tCK.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention uses a frequency detector to compare 1tCK at low frequencies and 2tCK at high frequencies to operate at a high frequency of 200MHz or more.

Claims (5)

In a semiconductor memory device, An input buffer for receiving and buffering an external clock; A clock divider configured to receive an internal clock signal from an input buffer and generate a pulse corresponding to one clock cycle; A delay model unit configured to receive a signal fed back from the delay monitor and generate a delay signal equal to a delay to be compensated for; A frequency detector configured to receive an output signal of the delay model unit and an output signal of the clock divider to detect whether high frequency or low frequency is present; A selector for receiving the output of the clock divider and the output of a frequency detector and selecting one of one clock cycle pulse and two clock cycle pulses; A setup time delay unit configured to compensate for a frequency detection error of a frequency detector by receiving an output signal of a selector and an output of the input buffer; A phase comparator for receiving the delay model unit and the output of the clock divider and comparing rising edges of two signals; A phase shift controller for controlling the shift of the delay monitor to the left or the right by receiving the control signal from the phase comparator; A delay monitor for adjusting delay in response to an output from the phase shift controller, an output from the phase divider, and an output from the input buffer; And An output buffer for receiving the output from the input buffer and the output from the delay monitor to generate a delay locked loop clock Register delay lock loop made, including. The method of claim 1, Frequency detector, A frequency detection termination unit configured to receive the output signal and the enable signal (enable) of the delay model unit to control that the frequency detection is completed; A first NAND gate negatively multiplying the output of the frequency detecting end with the first signal, which is the output of the clock divider, and the second signal, which is the output of the delay model unit; A pulse generator for generating a pulse by receiving the output of the first NAND gate; A first latch stage for receiving and latching the first signal and the second signal; Second and third NAND gates which receive a negative logic multiplication by receiving the output of the first latch stage and the output of the pulse generator; And A second latch stage for receiving and latching outputs of the second and third NAND gates; Register delay lock loop made, including. The method of claim 2, Frequency detection end part, A first latch stage configured to receive and enable the enable signal; A first inverter for inverting the second signal; Two NMOS transistors connected in series between the first output node of the first latch stage and the ground terminal, receiving the enable signal and the output of the first inverter; A second latch stage for receiving and receiving the enable signal; Two NMOS transistors receiving the second output of the first latch stage and the second signal and being connected in series between a third output node of the second latch stage and a ground terminal; A third latch stage for receiving and latching the enable signal; A second inverter for inverting the second signal; Two NMOS transistors connected to the fourth output node of the second latch stage and the output of the second inverter and connected in series between the fifth output node of the third latch stage and the ground terminal; And An even number of inverters connected in series with the fifth output node to generate an output signal. Register delay lock loop made, including. The method of claim 1, The setup time delay unit A latch stage for receiving and latching an output of the phase shift controller and a signal of a first node and outputting a signal of a second node; A NAND gate receiving an output of the latch stage and an output of the selector; And Unit delay for receiving the output of the NAND gate and the signal of the third node to delay the time and output the signal of the fourth node Register delay lock loop made, including. The method of claim 4, wherein A plurality of latch stages connected in series to output a signal of the first node and receive a signal of the second node; And A plurality of serially connected unit delays which output the signal of the third node and receive the output of the previous unit delay Register delay lock loop made, including.