KR100324280B1 - method for duplexing control bus fail checking in switching system processor - Google Patents

Abstract

When a system reset or board disconnection occurs while the device access processors in the switching system perform redundancy, stable operation is prevented by preventing abnormal switching of the control bus.

According to the present invention, if a reset occurrence is detected while one of the redundant boards having a processor is in an active state and the other is in a standby state, the present invention determines whether the corresponding board to which the reset is currently maintained is active. Process of doing; If the board on which the reset occurs is currently in the active state, the state signal of the active state board is output to the board in the standby state at the same level as the state signal input from the board in the standby state, thereby providing the board in the standby state. Switching to an active state; If the board on which the reset occurs is a board currently maintaining a standby state, the state information of the corresponding standby state board is output to the board in the active state at a level different from the state information applied from the board in the active state, thereby providing the current active state. It characterized in that it comprises a process of continuously maintaining the operation of the holding board.

Accordingly, the present invention provides stability to the operation of the system by eliminating the occurrence of abnormal switching by continuously maintaining the operation of the board in the active state even if a reset or hernia occurs in the board in the standby state.

Description

Method for duplexing control bus fail checking in switching system processor

The present invention relates to a redundancy control method of a switching system, and more particularly, to control when a system reset or a board detachment occurs while a redundancy operation is performed between device access processors in a switching system. The present invention relates to a method of preventing a malfunction in the duplication of a control bus of a processor in an exchange system that prevents abnormal switching of a bus to maintain stable operation.

In general, the exchange system has two identical boards mounted in a mirror form to minimize subscriber complaints and to ensure stable operation of the system, one of which is kept active and the other board is in a standby state. To keep it.

As can be seen in the accompanying Figure 1, the A side board 10 and the B side board 20 is configured in a mirror form, each board is connected to the device 30 via a control bus, the A side In the board 10 and the B-side board 20, the processor is provided with status information signals (dbseloutA, dbselinA, dbseloutB, dbselinB) of each board for redundant switching of the control bus, and a signal (sfailA, rfailA, sfailB, rfailB) are connected to each other.

In the above, the signal active * for the processor in the A-side board 10 or the B-side board 20 to occupy the control bus for transmitting and receiving data with the device 30 is a signal (dbseloutA, dbselinA) detected on its own board. Alternatively, dbseloutB, dbselinB) is generated by the exclusive OR result by XOR, which is a logical operation means (not shown). In order to be, the signal dbseloutA output from the own board to the B side board 20 and the signal dbselinA applied from the B side board 20 are '1' and '0' or '0' and '1. 'B', the B-side board 20 outputs the signal from its own board to the A-side board 10 in order to become an active state that transmits and receives data with the device 30 through the control bus. ) And A side board (10) Signal (dbselinB) that must maintain a '1' and '1' or '0' and '0'.

In addition, when a board is dismounted or reset, as shown in FIG. 2, a signal (dbselout) applied to the other board as status information of its own board is initialized to '1' and its board as described above. In the event of a reset, error information (sfail) about its board is transmitted as an interrupt signal (rfail) to the processor of the partner board so that the processor of the partner board can recognize it.

In the above, the conditions for maintaining the A-side board 10 and the B-side board 20 in an active state are summarized in Table 1 below.

dbselin dbselout Active board Standby board 0 0 B A 0 One A B One 0 A B One One B A

The operation of performing the redundancy transfer in the state of satisfying the above condition is as follows.

The processor of the board which maintains an active state among the A-side board 10 or the B-side board 20, which is made redundant, sends a signal 'active' output to the control bus to transmit / receive data with the device 30 to 'low'. The processor on the other side of the board, which is in standby mode, keeps the signal (active *) output to the control bus 'high'.

In this case, the device 30 maintains data transmission and reception with a processor on the board side in which a signal active * received through the control bus maintains a low state.

In the above, the status information signal (dbseloutA or dbseloutB) of the own board notifying the other board to determine the signal (active *) for controlling the control bus occupancy (active *) as 'low' or 'high' The signal applied to its board side (dbselinA or dbselinB) is detected through an exclusive logical sum through a logical calculation means (not shown). When the result of the calculated exclusive logical sum is '1', that is, the signal of the own board (dbseloutA or If the levels of the signals (dbselinA or dbselinB) applied from the other board (dbseloutB) are different from each other, the signal (active *) for accessing the device 30 through the control bus in the A-side board 10 is active. If the result of the exclusive OR being calculated is '0', that is, a signal (dbseloutA or dbseloutB) that notifies the other board of the status information of its own board and the other board itself If the levels of the signals (dbselinA or dbselinB) applied to the boards are the same, the B side board 20 is active and outputs a signal active * for accessing the device 30 through the control bus as low. .

The determination of a signal (active *) for accessing the device 30 in each of the above boards is made by analyzing the state information of both boards by a software program and then setting the signal (dbselout) for the state information of the own board. As shown in FIG. 2, the signal dbselout of the board state is set by the signal of the control register (WCR) applied as the clock signal, and when the reset is applied, the state of the board The signal for dbselout is initialized to 'high' and applied to the other board as an interrupt signal, and the redundant transfer of the control bus is executed by the operation of the processor in the other board.

Therefore, when the other board is detached or reset while the other board occupies the control bus and maintains data transmission and reception with the device 30, the signal of the status information applied from the other board (dbselin) becomes 'high'. As a result, the occupancy of the control bus in the normal state is changed to an abnormal state.

In the redundant control apparatus of the conventional switching system as described above, the processor on the board side, in which the processors in each board must monitor the state of both boards in a mirror form and maintain the active state, provides a signal (active *) for occupying the control bus. At the same time, it outputs a low signal and outputs a signal (dbselout) of the state of its own board to the other board so that the processor of the other board cannot occupy the control bus.

For example, when the processor of one board that is in an active state transitions to an abnormal state, when the board A 10 is active, the status information signal dbseloutA and B of its own board detected by the board A 10 are detected. The signal dbselinA of the status information applied from the side board 20 maintains '1' and '0' or '0' and '1', and the status information signal of the own board detected by the B side board 20. (dbseloutB) and the signal (dbselinB) of the status information applied from the A side board 10 also maintains '1' and '0' or '0' and '1'.

In this state, even though the A side board 10 is reset, the status information signal dbseloutA of the A side board 10 and the signals dbselinA applied from the B side board 20 are '1' and '0'. 'Is maintained continuously so that no signal transition occurs.

Therefore, since the signal transition must be generated in the B side board 20 under control by software, the processor of the A side board 10 interrupts the signal sfailA for an error occurrence to the B side board 20 side. Since the signal is applied as a signal, the processor of the B-side board 20 controls the state information signal dbseloutB of its own board to be output as '1' in software according to the interrupt signal applied thereto.

Therefore, the signals dbseloutA and dbselinA detected by the processor of the A side board 10 are in a state of '1' and '1' or '0' and '0', thus maintaining a standby state, and the B side board 20 The signals (dbseloutB, dbselinB) detected by the processor of the processor become active by maintaining the state of '1' and '1' or '0' and '0', so the signal (active *) for the control bus occupancy is 'low'. By outputting the data to and from the device 30 can be maintained.

In addition, the operation in the case where reset is performed while the B-side board 20 remains active is operated as described above.

However, a problem occurs when a board holding a standby state or a status signal (dbseloutA or dbseloutB) that is output due to a reset or a reset is abnormally transitioned. For example, the A side board 10 is active. Assuming that the B side board maintains the standby state, the status information signal dbseloutA of its own board detected by the A side board 10 and the status information signal dbselinA applied from the B side board 20 are assumed. ) Maintains '1' and '0' or '0' and '1' and is applied by the status information signal dbseloutB of its own board detected by the B side board 20 and the A side board 10. The information signal (dbselinB) also holds '1' and '0' or '0' and '1'.

In this state, when the B side board 20 maintaining the standby state is reset or reset, the signal dbseloutB of the status information applied from the B side board 20 to the A side board 10 is '1'. Since the signal (dbseloutA, dbselinA) recognized by the processor in the A side board 10 is transitioned to the state of '1' and '1'.

Therefore, the processor of the A side board 10 that needs to remain active cannot maintain the active state due to the abnormal state of the B side board 20 processor that is in the standby state and thus cannot occupy the control bus. Therefore, data transmission and reception with the device 30 is not made.

Therefore, in the case of a conventional redundant control device, if an abnormal state occurs due to a disconnection or reset of a board that is in a standby state, the board that is in an active state may also be abnormally operated and thus fail to occupy the control bus. There was a problem that the transmission and reception cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described general problems, and its object is to detect the current state of the board and the state information of the other board in the redundancy control device, thereby preventing the board from being mounted or reset in the active or standby state. Even if it occurs, it controls the status information signal (dbselout) output from the board so as not to affect the processor of the other board so that abnormal redundancy switching is not performed.

1 is a schematic configuration diagram of a redundancy control device in an exchange system,

2 is a configuration diagram of a main part for outputting a redundancy control signal in a conventional exchange system,

3 is an operational flowchart of performing control bus redundancy of a processor in an exchange system according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: A side board 20: B side board

30: device

A feature of the present invention for achieving the object as described above, in the method of preventing malfunction in the control bus redundancy of the processor in the exchange system, one of the redundant board having the processor is active and the other standby Determining whether a corresponding board on which a reset occurs is currently active when a reset occurs while maintaining a state; If the board on which the reset occurs is currently in the active state, the state signal of the active state board is output to the board in the standby state at the same level as the state signal input from the board in the standby state, thereby providing the board in the standby state. Switching to an active state; If the board on which the reset occurs is a board currently maintaining a standby state, the state information of the corresponding standby state board is output to the board in the active state at a level different from the state information applied from the board in the active state, thereby providing the current active state. It includes the process of continuously maintaining the operation of the holding board.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The processor in each board composed of redundancy analyzes the status information of its own board and the signal (dbselin) applied from the other board to determine whether the current board is active or standby (S101).

Subsequently, when a board reset or a reset of the system by the user is detected, it is determined whether the board on which the reset or the run occurs is a board that remains active (S102) (S103).

If it is determined that the board in which the reset or hernia occurred is a board that maintains the current active state and maintains data transmission and reception with the device 30 through the control bus, the other board maintains its state information in the standby state. By notifying the board, adjust the signal (dbselin) applied from the other board and the signal (dbselout) output from one's own board to the same level, switch from the active state to the standby state, and then activate the other board maintaining the standby state. Transfer to the control bus to perform the transfer (S104)

If the board in which reset or hernia occurs is currently in standby state, the processor of the board determines that it is a request for abnormal transfer, initializes a signal (dbselout) that outputs the status information of its own board, and then The board that is currently active and outputs a signal different from the applied signal dbselin maintains the occupancy of the control bus so that the device 30 can be transmitted and received (S105).

If the occurrence of the reset signal is not detected and it is determined that the signal WCR to set the output signal of the board by the control register is set, the data value is set to the signal of the board (dbselout) and outputted (S106) (107). ).

The signal dbselout set above is, for example, a signal output from the A side board 10 when the A side board 10 maintains an active state and the B side board 20 maintains a standby state. Is to maintain a state of '1', B board 20 is to maintain a state of '0'.

The operation as described above will be described by way of example.

Assuming that the A side board 10 remains active and the B side board 20 is in a standby state, the signal (dbseloutA) and the B side board for the own board detected by the processor in the A side board 10 are assumed. Since the signal (dbselinA) applied at (20) maintains '1' and '0' or '0' and '1', the signals (dbseloutB, dbselinB) detected by the processor of the B side board 20 are also '1'. And '0' or '0' and '1'.

As shown in FIG. 2, when the reset signal is applied to the B-side board 20 which maintains the standby state in the above state, the output terminal Q of the flip-flop is '0'. Since the signal dbselout is input to the clear terminal CLRN, the finally output signal dbselout maintains the initial value and the unchanged value of '0' in the state of '0'.

Therefore, even if the reset on the B-side board 20 in the standby state does not affect the A-side board 10 in the active state.

On the contrary, assuming that the A side board 10 is in the standby state and the B side board 20 is in the active state, the signal of its own board detected by the processor of the B side board 20 (dbseloutB) And the information signal dbselinB applied from the A side board 10 maintains '1' and '1' or '0' and '0', and the information of the own board detected by the processor of the A side board 10 is maintained. The status signal dbseloutA and the signal dbselinA of the status information applied from the B-side board 20 also maintain the states of '1' and '1' or '0' and '0'.

As shown in FIG. 2, when the A side board 10 maintaining the standby state in the above state resets while maintaining the '0' and '0', as shown in FIG. 2, the output terminal of the flip-flop is provided. In (Q), since the signal dbselout of the '0' state is input to the clear terminal CLRN, the finally output signal dbselout is the state of '0' and the initial value and the value of '0' without change. Keep it.

Therefore, even if the reset on the A side board 20 in the standby state does not affect the B side board 10 in the active state.

In addition, even if the A-side board 10 is reset while holding '1' and '1', the B-side board 20 holding the active state is not affected.

In the above, the case of resetting the board maintaining the standby has been described. However, the case of resetting the board maintaining the active state will be described below.

For example, assuming that the A side board 10 is active and the B side board is in a standby state, the signals dbseloutA and dbselinA recognized by the processor of the A side board 10 are '1'. It maintains a state of 'and'0' or '0' and '1'.

In this state, when a reset is applied to the A-side board 10 that remains in the active state, as shown in FIG. 2, the signal dbselout output from the output terminal Q of the flip-flop is '1'. Since the state is applied to the B-side board 20, the processor determines that the applied signal dbselinB and its current state signal dbseloutB maintain '1', and then transfers from the standby state to the active state. Occupies transmission and reception with the device 30 by occupying the control bus.

As described above, according to the present invention, even when a reset or a hernia of a board is maintained in a board maintaining a standby state in a redundant control device of an exchange system, an abnormal switching is generated by continuously maintaining an operation of a board maintaining an active state. To provide stability to the operation of the system.

Claims (1)

In the method of preventing malfunction when the control bus of the exchange system is redundant, When a reset occurs when one of the redundant boards having a processor is active and the other is in a standby state, determining whether the corresponding board on which the reset occurs is currently active; ; If the board on which the reset occurs is currently in the active state, the state signal of the active state board is output to the board in the standby state at the same level as the state signal input from the board in the standby state, thereby providing the board in the standby state. Switching to an active state; If the board on which the reset occurs is a board currently maintaining a standby state, the state information of the corresponding standby state board is output to the board in the active state at a level different from the state information applied from the board in the active state, thereby providing the current active state. A method of preventing a malfunction when a control bus of a processor is duplicated in an exchange system, the method comprising continuously maintaining an operation of a holding board.