KR100313115B1 - Method for driving plasma display panel - Google Patents

Abstract

The driving method according to the present invention has a front substrate and a rear substrate spaced apart from each other, wherein X and Y electrode lines are formed parallel to each other, and the address electrode lines are orthogonal to the X and Y electrode lines. The minimum driving period includes a display discharge period, a reset period, and an address period, and a scan pulse is applied to at least one Y electrode line in the address period. At the same time, wall charges are formed on the pixels to be displayed by applying a corresponding display data signal to each address electrode line, and wall charges are formed by alternately applying pulses for display discharge to the X and Y electrode lines in the display discharge period. Display discharge occurs in the pixels and the wall charge remaining from the previous sub-field in the reset period Reset pulse for forming the space charge, removing the drive method is applied to at least any one of the Y electrode lines. Here, the minimum driving period corresponding to the case where the reset pulse is not applied to any of the Y electrode lines in the reset period includes only the display discharge period and the address period.

Description

Driving method for plasma display panel {Method for driving plasma display panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a plasma display panel of a three-electrode surface discharge method.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 illustrates an electrode line pattern of the plasma display panel of FIG. 1. FIG. 3 shows an example of one pixel of the panel of FIG. 1. Referring to the drawings, between the front and rear glass substrates 10 and 13 of the general surface discharge plasma display panel 1, address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am Dielectric layers 11 and 15, Y electrode lines Y ₁ , Yn, X electrode lines X ₁ , Xn, phosphor 16, barrier 17, and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am are formed in a predetermined pattern on the front surface of the rear glass substrate 13. The lower dielectric layer 15 is entirely coated on the front surface of the address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am. The barrier ribs 17 are formed on the front surface of the lower dielectric layer 15 in a direction parallel to the address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am. These partitions 17 function to partition the discharge area of each pixel and to prevent optical cross talk between each pixel. The phosphor 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., Xn) and the Y electrode lines (Y ₁ , ..., Yn) are front glass substrates to be orthogonal to the address electrode lines (A ₁ , ..., Am). 10 is formed in a constant pattern on the back side. Each intersection point defines a corresponding pixel. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Yn) is an indium tin oxide (ITO) electrode line (Xna, Yna of FIG. 3) of a transparent conductive material. And a bus electrode line (Xnb, Ynb of FIG. 3) made of metal are combined. The upper dielectric layer 11 is formed by coating the entire surface on the rear surfaces of the X electrode lines X ₁ ,..., Xn and the Y electrode lines Y ₁ ,..., Yn. A magnesium monoxide (MgO) layer 12 for protecting the panel 1 from a strong electric field is formed by applying a front surface to the back surface of the upper dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

The driving method basically applied to the plasma display panel is a method in which the reset, address, and display discharge steps are sequentially performed in the unit subfield. In the reset step, the residual wall charges in the previous subfield are erased and driven so that the space charges are generated evenly. In the addressing step, the wall charges are formed in the selected pixels. In the display discharge step, light is driven to generate light in pixels in which wall charges are formed in the address step. That is, when alternatingly applying a pulse of a relatively high voltage to all the X electrode lines (X ₁ , ..., Xn) and all the Y electrode lines (Y ₁ , ..., Yn), wall charges are formed. It causes surface discharge in the pixels. At this time, a plasma is formed in the gas layer, and the phosphor 16 is excited by the ultraviolet radiation to generate light.

4 illustrates a unit display cycle according to a general plasma display panel driving method, for example, a unit frame in a sequential driving method or a unit field in an interlaced driving method. The driving method shown in FIG. 4 is commonly called a multiple address overlapping display driving method. According to this driving method, display discharge pulses are continuously applied to all X electrode lines (X ₁ , ..., Xn in FIG. 1) and all Y electrode lines (Y ₁ , ..., Y ₄₈₀ ). Reset or address pulses are applied between each display discharge pulse. That is, the reset and address steps are performed sequentially for individual Y electrode lines or groups in the unit sub-field, and the display discharge step is performed for the remaining time. Accordingly, there is an advantage in that the display luminance is increased as compared with the address-display separation driving method. Here, an address-display separation driving method is, units of the sub-fields in all Y electrode lines, while accounting for the reset and address periods in which steps _{(Y 1, ..., Y 480} ) the display discharge after step performed on Says how it is done.

Referring to FIG. 4, a unit frame is divided into _eight sub-fields SF ₁ , SF ₈ for time division gray scale display. Reset, address and display discharge steps are performed in each sub-field, and the time allocated to each sub-field is determined by the display discharge time corresponding to the gray scale. For example, in the case of displaying 256 gray levels in frame units as 8-bit image data, if a unit frame (typically 1/60 second) consists of 256 units of time, driving is performed according to the image data of the least significant bit (Least Significant Bit). The first sub-field SF ₁ is 1 ( ) Unit time, the second sub-field SF ₂ is 2 ( ) Unit time, the third sub-field SF ₃ is 4 ( ) Unit time, the fourth sub-field SF ₄ is 8 ( ) Unit time, the fifth sub-field SF ₅ is 16 ( ) Unit time, the sixth sub-field SF ₆ is 32 ( ) Unit time, the seventh sub-field SF ₇ is 64 ( ) The eighth sub-field SF ₈ driven according to the unit time and the image data of the most significant bit is 128 ( ) Each has a unit time. That is, since the sum of the unit times allocated to each of the sub-fields is 257 unit time, 255 gray scale display is possible, and if the gray scale in which no display discharge occurs in any sub-field is included, 256 gray scale display is possible.

Display after an address step is performed on the first Y electrode line Y ₁ or the first Y electrode line group (eg, Y ₁ ,..., Y ₄ ) in the first sub-field SF ₁ . When the discharging step is performed, an address step is performed on the first Y electrode line Y ₁ or the first Y electrode line group Y ₁ ,..., Y _{4 in} the second sub-field SF ₂ . . The same process applies to the following subfields SF ₃ ,..., SF ₈ . For example, after the address step is performed on the second Y electrode line Y ₂ or the second Y electrode line group Y ₅ ,..., _{8 in} the seventh sub-field SF ₇ , the display is performed. When the discharging step is performed, an address step is performed on the second Y electrode line Y ₂ or the second Y electrode line group Y ₅ ,..., Y _{8 in} the eighth sub-field SF ₈ . . The time of the unit subfield is the same as the time of the unit frame, but each unit sub-field overlaps each other based on the driven Y electrode lines Y ₁ ,..., Y ₄₈₀ to form a unit frame. Therefore, since there are all sub-fields SF ₁ , ..., SF ₈ at every time point, the time slot for address according to the number of sub-fields between each display discharge pulse for performing each address step. Are set.

As one of the above-described address-display overlapping driving methods, a driving method in which an address step is performed in the order of sub-fields SF ₁ , ..., SF ₈ between each display discharge pulse is commercially available. . In such a driving method, conventionally, the minimum driving period is fixed to include a display discharge period, a reset period, and an address period. That is, even when the reset pulse is not applied to any of the Y electrode lines in any one reset period, it is fixed to include all of the display discharge period, the reset period, and the address period in the corresponding minimum driving period.

According to such a conventional driving method, the time allocated to the display discharge period and the address period becomes relatively short due to the presence of unnecessary reset periods. As a result, the stability and accuracy of the addressing and the display discharge are relatively low, resulting in poor image quality.

SUMMARY OF THE INVENTION An object of the present invention is to provide a driving method in which the image quality can be improved by increasing the stability and accuracy of addressing and display discharge by setting the minimum driving cycle more efficiently in the driving method of the plasma display panel.

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is an electrode line pattern diagram of the plasma display panel of FIG. 1.

3 is a cross-sectional view illustrating an example of one pixel of the panel of FIG. 1.

4 is a timing diagram illustrating a configuration of a unit display period by a driving method of a general plasma display panel.

5 is a voltage waveform diagram showing driving signals in a unit display period by the driving method according to the present invention.

6 is an enlarged voltage waveform diagram illustrating the Y electrode driving signal S _Y1 of FIG. 5.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 magnesium monoxide layer,

13 back glass substrate, 14 discharge space,

16 phosphors, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line, Y ₁ , ..., Yn ... Y electrode line,

A ₁ , ..., Am ... address electrode line, Xna, Yna ... ITO electrode line,

Xnb, Ynb ... bus electrode line. SF ₁ , ... SF ₈ ... sub-field,

S _X1..4 , S _X5..8 ... X electrode drive signal, GND ... ground voltage,

S _Y1 , ..., S _Y8 ... Y electrode drive signal, S _A1 .. _m ... display data signal,

2, 5 ... Display discharge pulse, 3 ... Reset pulse,

6 ... scan pulse, SH ₁ , ..., SH ₅ ... minimum drive cycle,

T _11D ... display discharge cycle, T _11R ... reset cycle,

T ₁₂ , T ₂₂ , T ₃₂ , T ₄₂ , T ₅₂ ... address cycles.

The driving method of the present invention for achieving the above object has a front substrate and a rear substrate spaced apart from each other, the X and Y electrode lines are formed parallel to each other between the substrates, the address electrode lines are the X and Y electrodes For a plasma display panel which is formed orthogonal to the lines and in which pixels corresponding to each intersection point are set, the minimum driving period includes a display discharge period, a reset period, and an address period, and at least one Y electrode line in the address period. The wall charges are formed on the pixels to be displayed by applying a scan pulse to the respective address electrode lines, and a display discharge pulse is applied to the X and Y electrode lines in the display discharge period. Alternatingly, display discharge occurs in pixels in which the wall charges have been formed. A driving method applied to a reset pulse to at least one of the Y-electrode lines for forming the space charge and eliminate the wall charges remaining on the field - the former sub-group in the reset period. Here, the minimum driving period corresponding to the case where the reset pulse is not applied to any of the Y electrode lines in the reset period includes only the display discharge period and the address period.

According to the driving method of the present invention, since the unnecessary reset periods do not exist, the time allocated to the display discharge period and the address period becomes relatively long. As a result, the stability and accuracy of the addressing and the display discharge are relatively increased, thereby improving the image quality.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

5 shows driving signals in a unit display period by the driving method according to the present invention. In Fig. 5, reference numerals S _Y1 , ..., S _Y8 denote driving signals applied to corresponding Y electrode lines of each sub-field. More specifically, S _Y1 is a drive signal applied to any Y electrode line of the first sub-field (SF ₁ of FIG. 4), and S _Y2 is any of the second sub-field (SF ₂ of FIG. 4). A drive signal is applied to one Y electrode line, S _Y3 is a drive signal applied to any Y electrode line of the third sub-field (SF _{3 in} FIG. 4), and S _Y4 is a fourth sub-field (FIG. 4). Is a drive signal applied to any one Y electrode line of SF ₄ ), S _Y5 is a drive signal applied to any one Y electrode line of the fifth sub-field (SF ₅ of FIG. 4), and S _Y6 is a sixth drive signal. The drive signal applied to any one Y electrode line of the sub-field (SF ₆ of FIG. 4), the S _Y7 is the drive signal applied to any one Y electrode line of the seventh sub-field (SF ₇ of FIG. 4). And S _Y8 indicate driving signals applied to any one Y electrode line of the eighth sub-field (SF ₈ of FIG. 4). Reference numerals S _X1 .. ₄ , S _X5 .. ₈ denote drive signals applied to the X electrode line groups corresponding to the Y electrode lines to be scanned, S _A1 .. _m is a display data signal, and GND is a ground voltage. , SH ₁ , ..., SH ₅ for the minimum drive cycle, T _11D for the display discharge cycle, T _11R for the reset cycle, and T ₁₂ , T ₂₂ , T ₃₂ , T _42, and T ₅₂ for the address cycle. Point. 6 is an enlarged view of the Y electrode driving signal S _Y1 of FIG. 5.

Referring to FIGS. 5 and 6, each display discharge period T _11D is a display room on the X and Y electrode lines (X ₁ , ..., Xn, and Y ₁ , ..., Yn in FIG. 1). By alternately applying the dedicated pulses 2 and 5, it is a period for causing display discharge in the pixels in which the wall charges have been formed. Each reset period T _11R is to be scanned in a subsequent address period T ₁₂ , T ₂₂ , T ₃₂ , T ₄₂ , T ₅₂ to remove the remaining wall charges from the previous sub-field and form space charges. This is a period for applying the reset pulse 3 to the electrode lines. Each address period T ₁₂ , T ₂₂ , T ₃₂ , T ₄₂ , T ₅₂ corresponds to the corresponding indication while sequentially applying the scan pulse 6 to the Y electrode lines corresponding to the four sub-fields. It is a period for forming wall charges in the pixels to be displayed by applying the data signal S _A1 .. _m to each address electrode line.

Here, the minimum driving period SH ₁ , SH ₂ in which the reset pulse 3 exists includes the display discharge period T _11D , the reset period T _11R , and the address period T ₁₂ , T ₂₂ . However, the minimum driving period SH ₃ , SH ₄ , SH _{5 in which the} reset pulse 3 does not exist includes only the display discharge period T _11D and the address periods T ₃₂ , T ₄₂ , and T ₅₂ . Therefore, since the unnecessary reset periods do not exist, the time allocated to the display discharge period and the address period becomes relatively long. As a result, the stability and accuracy of the addressing and the display discharge are relatively increased, thereby improving the image quality.

Indication discharge pulses 2 and 5 are sustained in the X electrode lines (X ₁ , ..., Xn in FIG. 1) and all the Y electrode lines (Y ₁ , ..., Y _{480 in} FIG. 1). The reset pulse 3 or the scan pulse 6 is applied between the display discharge pulses 2 and 5. Here, reset or address pulses are applied to the corresponding Y electrode lines of the plurality of sub-fields SF ₁ ,..., SF ₈ .

After the reset pulse 3 is applied until the scan pulse 6 is applied, a predetermined rest period is allowed to smoothly distribute the space charges in the corresponding pixel region. In FIG. 5, the times T ₁₂ , T ₂₁ , T ₂₂ and T ₃₁ correspond to the rest periods corresponding to the Y electrode line groups of the first to fourth sub-fields, and T ₂₂ , T ₃₁ , T ₃₂ and T ₄₁ represent Indicates a rest period corresponding to the Y electrode line group of the fifth to eighth sub-fields. The pulses for display discharges 5 applied in each pause period do not cause actual display discharges and allow the space charges to be smoothly distributed in the corresponding pixel region. However, the display discharge pulses 2 applied outside the rest period cause the display discharge to occur in the pixels in which the wall charges are formed by the scan pulse 6 and the display data signal S _A1 .. _m .

Among the display discharge pulses 5 applied in the rest period, four addressing is performed between the final pulses and the subsequent first display discharge pulses 2 (T ₃₂ or T ₄₂ ). For example, at time T ₃₂ , addressing is performed on the corresponding Y electrode line group of the first to fourth sub-fields. In addition, at time T ₄₂ , addressing is performed on the corresponding Y electrode line group of the fifth to eighth sub-fields. As mentioned in the description of FIG. 4, since all sub-fields SF ₁ ,..., SF ₈ are present at all time points, the sub-fields between each display discharge pulse for performing each address step. Time slots for the address are set according to the number of pieces.

After termination of the Y-electrode lines (Y _1, ..., Y ₄₈₀₎ at the same time the display discharge pulse is applied (2, 5) is simultaneously applied to the X electrode lines (X _1, ..., Xn) Display discharge pulses 2 and 5 are started. Simultaneously with the Y electrode lines Y ₁ , ..., Y ₄₈₀ after the end of the display discharge pulses 2, 5 which are simultaneously applied to these X electrode lines X ₁ , ..., Xn. Scan pulses 6 and corresponding display data signals are applied until the display discharge pulses 2 and 5 are started.

As described above, according to the driving method of the plasma display panel according to the present invention, since unnecessary reset periods do not exist, the time allocated to the display discharge period and the address period becomes relatively long. As a result, the stability and accuracy of the addressing and the display discharge are relatively increased, thereby improving the image quality.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (1)

Having a front substrate and a rear substrate spaced apart from each other, X and Y electrode lines are formed parallel to each other between the substrates, and address electrode lines are formed orthogonal to the X and Y electrode lines, and at each intersection For a plasma display panel in which a corresponding pixel is set, the minimum driving period includes a display discharge period, a reset period, and an address period, wherein a scan pulse is applied to at least one Y electrode line in the address period and a corresponding display data signal Are applied to the respective address electrode lines, and wall charges are formed on the pixels to be displayed, and pixel discharges are formed by alternately applying display discharge pulses to the X and Y electrode lines in the display discharge period. An indication discharge occurs at and remains from the previous sub-field in the reset period. A reset pulse for the walls, removing the charge to form a space charge in the driving method is applied to the at least one Y electrode line, The minimum driving period corresponding to the case where the reset pulse is not applied to any of the Y electrode lines in the reset period includes only the display discharge period and the address period.