KR100314235B1 - Data descrambling device of TS bit string - Google Patents

Abstract

The present invention relates to a descrambling apparatus for descrambling a DES (Data Encryption Standard) algorithm, which is most widely used among block encryption algorithms, and a decryption system for decrypting encrypted data. A signal preprocessing unit (1) for receiving encrypted data of a TS bit sequence, a key for decrypting the encrypted data, an initializing vector, and transmitting the received vector to a DES decrypter; DES decrypter (2) which decrypts the transmitted encrypted data using the key and the initialization vector to efficiently encrypt the encrypted data of the encrypted MPEG-2 TS bit stream in various operating modes. There is an advantage that can be decrypted.

Description

Data descrambling device of TS bit string

The present invention relates to a descrambling device for descrambling a DES (Data Encryption Standard), which is the most widely used block encryption algorithm, and more particularly, to an encrypted MPEG-2 TS ( TS) A data bit descrambling apparatus of a TS bit string supporting data of a bit string in various operation modes.

The remarkable development of computer networks represented by the Internet has required a huge amount of data transmission, and e-commerce using the network is already easily accessible through the World Wide Web (WWW). Due to the development of this network, a huge amount of data transmission and processing of information are possible, while security issues are most urgently raised. In the case of over-the-air broadcasting, one of the important parts of the MPEG-2 system standard adopted by HDTV is technology that maintains the security of information by encrypting the restricted reception information that only paid subscribers can see. Encryption is done as follows.

The basic algorithms of encryption used in DS are permutation and substitution, and using these two forms a basic step called round, and as shown in FIG. It is repeated to form one encrypted DS block.

In FIG. 1, a key is generated by a key generation unit (not shown). The key generation unit first removes 8-bit parity bits from a 64-bit key and generates an operation key from the remaining 56 bits to use for data encryption. Done. The 64-bit plaintext block is divided into 32 bits after initial permutation (IP), and the right 32 bits are expanded through an expansion process, and the 48-bit key and the exclusive-or (exclusive-or) are selected from 56-bit keys. Exclusive logic: hereinafter referred to as "XOR" to create a 48-bit value, make it 32-bit by using S-box substitution algorithm, and then go through the P-box substitution process once more and finally the left 32-bit before XORs the value to form a new right 32 bit. The previous right 32-bit value is the new left 32-bit value.

This process is repeated 16 times, and the right 32 bits and the left 32 bits, which are generated lastly, are combined to undergo an inverse permutation process to obtain the final encrypted DS block.

In this case, initial permutation (IP) replaces an incoming block with a given table. For example, the 58th bit of the input is the 1st bit of the output and the 62nd bit of the input is the 17th bit of the output. To change.

Expansion permutation extends 48 bits from the given table by inputting the 32 bits of the right side among the 64 bits generated by the initial substitution (IP). For example, the 32nd bit of the input is the 1st bit of the output. The eighth bit of the input is the thirteenth bit of the output.

The initial 64-bit key generated by the key generator is 56 bits by removing each 8th parity bit according to the given table, and these 56 bits are divided into 28 bits so that one or two bits are shifted to the left by a certain rule. A 48-bit key is formed from the table.

S-box substitution is an XOR of the 48-bit compressed key and 48-bit obtained through extended substitution, and then the 32-bit output is produced by using eight substitution boxes. First, the input 48 bits are divided into eight 6-bit units, and the divided blocks are made into eight 4-bit blocks using eight S-boxes. For example, the first input of the eight input blocks If 6 bits are in1 to in6, the sum of in1 and in6 is used to make a 2-bit number, and the 2 bits (decimal value between 0 and 3) created at this time indicate which line (starting from 0) of S-box1. , in2 ~ in5 are added to make 4 bits, and this value is converted into decimal number (0-15) to indicate which column of the table (starting from 0), and the value obtained from the table is converted to binary number. This is a 4-bit output value. Through the above process, 8 4-bit blocks, that is, 32-bit output values are obtained. S-box substitution is a key part of the security of the DS because it has a non-linear characteristics unlike the above-described substitutions.

Since P-box substitution is a simple substitution, the value of replacing 32 bits as input using the given table is also 32 bits. For example, the 16th value of the input becomes the 1st bit of the output-the 2nd bit of the input becomes the 17th bit of the output.

Inverse permutation is the inverse of the initial substitution, which is made after 16 rounds and replaces the 64-bits of R16 + L16 with the given table to get the final 64-bit block.

The above-mentioned DS has various operation modes to encrypt the entire data by connecting them properly when the length of data to be encrypted exceeds 64 bits. Among them, three operation modes proposed in the standard are shown in Figs. 4, respectively.

<ECB (Electronic CodeBook) mode>

After dividing the plain text by the block size (64-bit) of the cryptographic system, and encrypting each block to generate a ciphertext, the entire structure is shown in FIG. ECB mode is recommended to use when the size of the plain text is small, and since the same cipher text is generated for the same plain text, there may be a security problem when encrypting the plain text where the same sentence is repeated. That is, it has a disadvantage of being vulnerable to decryption attacks.

<CBC (Cipher Block Chaining) Mode>

In order to compensate for the weakness of the weak security in the ECB mode is an operation mode for generating a different cipher text when the same plain text is repeated, the structure is shown in FIG. The input to the DES Encrypter for encryption is the XOR value of the plaintext coming into the current input and the previously encrypted block of encryption, and an Initialization Vector (IV) for the initial encryption. To generate a carry C1. Decryption is the reverse process of encryption, and initial vector values are just as important as keys, so be careful about security. CBC mode is suitable for encrypting messages with long plain text.

<CFB (Cipher FeedBack) mode>

DES mode is a block encryption system, but CFB mode can be used to enable stream encryption. Stream encryption has the advantage of not having to make plaintext blocks of a certain size. The same method is used for decryption, but note that the decryption algorithm of DES is not used, but the encryption algorithm is used as it is. In addition, since the carry C1 enters the input of the shift register, the error is propagated when an error occurs. When the transmission unit is j bits, the transmission unit is usually 8 bits (since one character = 8 bits). The 64-bit input to the DES Encrypter for encryption is initially obtained from a 64-bit shift register with an Initialization Vector, which is shifted left by 8 bits and previously encrypted. As the carry C1 value of 8 bits enters the least significant 8 bits, the overall structure is as shown in FIG.

As described above, in order to descramble the encrypted information at the receiving side, a systematic study and development of a scheme and a structure of a decrypter should be preceded. As a result of the inventors of the present invention, the present invention provides a data bit descrambling apparatus of a TS bit stream that efficiently decrypts encrypted data of an encrypted MPEG-2 TS bit stream in various modes of operation. There is a purpose.

1 is a diagram illustrating a DES algorithm;

2 is a structural diagram of an ECB mode;

3 is a structural diagram of a CBC mode;

4 is a structural diagram of a CFB mode;

5 is a configuration diagram of a data DS descrambling apparatus of the present invention TS bit string;

6 is a configuration diagram of a DS decoder according to the present invention;

7 is a configuration diagram of a control register unit according to the present invention;

8 is a block diagram of a rounding block decoder according to the present invention.

9 is a waveform diagram of a clock used in the present invention;

10 is a configuration diagram of a control register unit in the ECB mode according to the present invention;

11 is a configuration diagram of a control register unit in a CBC mode according to the present invention;

12 is a signal waveform diagram in ECB, CBC mode operation according to the present invention,

13A is a flowchart illustrating an operation of a control register unit in an ECB mode operation according to the present invention;

13B is a flowchart illustrating an operation of a control register unit in a CBC mode operation according to the present invention;

14 is a configuration diagram of a control register unit out of the CFB mode according to the present invention;

15 is a signal waveform diagram in the CFB mode operation according to the present invention;

16A and 16B are flowcharts illustrating operations of the control register unit in the CFB mode operation according to the present invention;

17A to 17C are flowcharts illustrating operations of a rounding block decoder according to the present invention.

* Explanation of symbols for main parts of the drawings

1: signal preprocessor 2: DS decoder

11: control register part 12: rounding block decoder

21-25: 1st-5th register 26: signal input part

27: initial substitution 28: reverse initial substitution

29: Optional replacement part BF1 to BF7: Buffer

RS: Right shift PC-2: Optional replacement part

E-func: Extended substitution TAU: Exclusive logic

S1 to S8: S-box substitution part P-func: Simple substitution part

X-func: Exclusive Logic

According to an aspect of the present invention, there is provided a decryption system for decrypting encrypted data, comprising: encrypted data of a TS bit sequence, a key for decrypting the encrypted data, and an input signal including an initialization vector; A signal preprocessing unit (1) for processing the signal and outputting the signal necessary for DS decoding; The control register unit 11 for receiving the output signal of the signal preprocessing unit 1 and controlling the decryption operation of the encrypted data according to the operation mode and the encrypted data transmitted through the control register unit 11. DES decrypter (2) comprising a rounding block decoder (12) for decrypting by performing 16 roundings required by the DS standard using the key and the initial set vector. .

The control register unit 11 connects the buffers BF2 and BF3 to the buffer BF1 to which the data signal eb is input through the fifth register 25, respectively, and the data signal eb. Is connected to the buffer BF3 through which the first register 21 is connected to the buffers BF4 and BF5 and the initial replacement unit 27, and the buffer BF6 is connected to the buffer BF4 through the register 23. And a buffer BF7 through a second register 22 to which the output of the reverse initial replacement unit 28 is input to the buffer BF5. The buffer BF6 is connected to the buffer BF2 through the fourth register 24, and the selection replacer 29 is connected to the signal input unit 26, and the initial value is connected to the first register 21. The rounding block decoder 12 divides the bits of the key and performs a right shift operation of a DS decoding algorithm on the value of the signal LS-SEL. Connect the light shift unit RS, which shifts by as much as possible, and the selection exchange unit PC-2 that generates a key value from the data input to the RS, and determine the value of the lower bit of the input block IN-BL. The S-box substitution unit (S1 to S8) is connected to the expansion substitution unit (E-func), and through the exclusive logic unit (TAU) to the selective substitution unit (PC-2) and the expansion substitution unit (E-func). Is connected to the S-box substitution unit (S1 to S8) through a simple substitution unit (P-func), the value of the upper bit side of the input block (IN-BL) and the simple substitution unit (P-func) XOR the output of The exclusive logic unit (X-func) is composed by combining a plurality of configurations.

Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the data DS descrambling device of the TS bit string of the present invention.

FIG. 5 is an overall configuration diagram of a device for descrambling a data bit of a TS bit stream of the present invention. The entire system receives a data of a TS bit stream and transmits the data to the TS decoder 2 to decrypt and decode the TS bit string. (initialization vector) and a signal preprocessing unit (1) for transmitting encrypted data, and a DS decoder (2) for performing a substantial decryption operation from the transmitted signal.

The DS decoder 1 is composed of two modules, a control register 11 and a rounding block decoder 12, as shown in FIG. 6, and the control register 11 is one of the EBS modes. As shown in FIG. 7, the rounded block decoder processes one round for 16 rounds of DC decryption, so that the encrypted bit string data can be decrypted in three modes, CBC mode and CFB mode. By operating (12) 16 times, one block can be decoded.

The signal input to the system is divided into TS data, Control Word signal CW, Initialization Vector signal IV-CW, and system clock, and TS data data is composed of 8-bit data, a clock, and a signal (Data-valid) indicating the validity of the data. The control word signal CW and the initialization vector signal IV-CWT are input in the form of 64 bits. The signal preprocessing unit 1 functions to transmit the necessary signals for the actual DS decoding from the input signal to the DS decoder 2. As a signal output from the signal preprocessor 1, an encrypted 8-byte data signal eb and a signal inValid. Clock, signal (KEY), (IV), three mode (ECB mode, CBC mode, CFB mode) for operation of DS decoder 2, mode selection signal (mode-sel), compliance field ( There is a signal (AF-L) for transmitting the size of the adaptation field.

Referring to the clock, the number of clocks used in the DS decoder 2 is equal to 3 of the clock TS-c1ocl, the clock RB-ECBC-clock, and the clock RB-CFB-clock as shown in FIG. Used. The encrypted data signal eb and the decoded data signal de of the bit string actually input and output are input and output in accordance with the clock TS-clock. As can be seen from FIG. 9, the clock (RB-ECBC-clock) is a clock defined for the decoding operation in the ECB mode and the CBC mode, and is twice as fast as the clock (TS-clock) but is input to the control register unit 11. In order to decode the encrypted 8-bit encrypted data signal (eb; encrypted byte) in 8-byte (64-bit) register, there is 8 cycles before entering the round block decoder 12. The round block decoder 12 must process 16 round decoding operations for one block. That is, since the rounding block decoder 12, which processes one round for eight cycles of the TS-clock, must be operated 16 times, the clock is used at least twice as fast.

The clock (RB-CFB-clock) is the clock required for CFB mode, which is designed 16 times faster than the clock (TS-clock) because CFB mode is the stream encryption. In this mode, one block of data is transmitted to the round block decoder 12 using the shift register for the one-byte encrypted data input to the control register unit 11. That is, since it takes one cycle from the input of the encrypted data to the one block of data to the rounding block decoder 12, the rounding block decoder 12 that processes one round in one cycle before the next block enters. The clock was 16 times faster because it had to be operated 16 times.

The signal AF-L is used by the control register unit 11 to receive the size of the compliance field and pass it by performing the decoding operation by the compliance field bytes of the size. 12 and 15 are ECB examples of TS packets having 4 bytes of headers and 20 bytes of data. I / O signal timing charts for CBC and CFB modes are shown.

The TS packet data is input in synchronization with the clock TS-clcok. At the first byte of the TS packet header, the signal TS-packet-start becomes an active high level state for one cycle of the signal TS-clock. It takes 18 cycles for ECB, CBC mode and 4 cycles for CFB mode until the first byte is input and decoded. In the ECB and CBC modes, one cycle is required for the latching of the first data and an output signal, and eight cycles are transmitted from the control register unit 11 to the rounding block decoder 12. The rounding block decoder 12 8 cycles are required for one cycle and one block of rounding block decoding in the signal input / output with the control register section 11, which takes a total of 18 cycles. In the CFB mode, one cycle is required for latching the first data and the output signal, and one cycle is transmitted from the control register unit 11 to the rounding block decoder 12 to control the rounding block decoder 12 and the control. One cycle and one block of rounding block decoding processing are required for signal input / output with the register section 11, which takes four cycles in total.

ECB. In order to implement the CBC and CFB modes, the control register unit 11 includes two 8-byte registers (first and second registers 21 and 22) and one 16-byte register (third register 23). One byte register (fourth register 24), one byte register (five registers 25), and buffers BF1 to BF7 are implemented. Each mode is determined by a mode-sel value, and receives a key signal KEY and an initialization vector signal IV to perform decoding. At this time, when the CBC mode de-encryption is implemented, a signal (in-valid-first-blk) is input as shown in FIG. 7 to XOR the value of the initialization vector signal IV.

Next, the decryption operation of the encrypted data for each mode will be described.

<ECB, CBC mode>

FIG. 10 is a configuration diagram of the control register unit 11 in the ECB mode. The control register unit 11 receives a signal in units of bytes from the signal preprocessing unit 1 and sends it to the rounding block decoder 12 in 8-byte units ( Two 8-byte registers 21 and 22 are required to output in units of blocks, and to input signals to the rounding block decoder 12, and a three-byte register buffer ( BF3), (BF5) and (BF7) are required.

And for the input and output to the round block decoder 12, the initial replacement unit (IP), inverse IP, and 64-bit key values, which are used only once in the first and last ones of the DS algorithm, are converted into 56-bit values. By implementing the substitution part (PC-1) portion to the control register unit 11 to replace the round block decoder 12 for processing one round 16 times it was configured to implement 16 rounds.

FIG. 11 is a configuration diagram of the control register unit 11 in the CBC mode, which is similar to the ECB mode, but uses a third register 23 that is a 16-byte shift register to implement a chaining algorithm. The decoded signal db is finally output by XORing the value of 1 byte and the decoded 1 byte value obtained from (23). 12 is a signal waveform diagram in ECB and CBC mode operation according to the present invention, and FIGS. 13A and 13B respectively show an algorithm for receiving an input from the signal preprocessor 1 and outputting it to the rounding block decoder 12 in 8-byte units. As an operation flowchart of the control register unit 11 during ECB and CBC mode operation according to the present invention, the header and the rest are first distinguished and passed without reverse encryption as in the case of encryption. When valid encrypted data comes in, the count is counted to 8, that is, 1 block (8 bytes), the data is transmitted to the round block decoder 12. When the decrypted block is input from the round block decoder 12, in the case of the CBC mode, the first 1-block plaintext that is inversely encrypted is obtained through an XOR process between the initial first decrypted block and the initialization vector IV. The block is output by the second register 22 in units of 1 byte, and the data output of the reverse encrypted one byte thereafter is transmitted to the control register unit 11 before the encrypted statement and the round block decoder 12. It can be obtained through XOR with the decoded byte stored in the second register 22 after being reverse-initialized by the transmission in.

<CFB mode>

FIG. 14 is a configuration diagram of the control register unit 11 in the CFB mode. First, the initial setting vector IV loaded in the first register 21, which is a shift register, to obtain the first decoded 1-byte output. ) 8 bytes is transmitted to the rounding block decoder 12 via the initial replacement unit 27. The 8-byte value decoded by the rounding block decoder 12 is transmitted to the second register 22, which is a control register, and only the most significant byte of the 8-bytes transmitted as the input value of the control register 11 is eb. ) And exclusive or, finally, the decoded output value 1 byte is obtained. The output values are then loaded with the previous signal eb in the least significant 8 bits of the first register 21 to obtain the decoded byte in the same manner as above.

Since the CFB mode is a stream encryption system, there is no need to block the block in units of 8 bytes. Therefore, there is no residue. In the ECB and CBC modes described above, there is a rest because the block is encrypted. The header and the rest are inputted and outputted as they are, without being encrypted or decrypted. In order to obtain the decoded byte from the initialization vector IV, that is, one cycle is initially required to transmit one block to the rounding block decoder 12, the fifth register 25 is used for this delay. The fourth register 24 is used to XOR the pass and the rounding block decoder 12 and the previous signal eb to obtain the decoded byte.

FIG. 15 is a signal waveform diagram of the CFB mode operation according to the present invention, and FIG. 16 is a flowchart illustrating the operation of the control register unit during the CFB mode operation according to the present invention. . The effective one block data accumulated in the first register 21 is applied to the rounding block decoder 12 via the initial replacement unit 27, and the block decoded by the rounding block decoder 12 is passed through the inverse initial replacement unit 28. XOR the encryption byte inputted to the second register 22 and transmitted to the control register unit 11 to the reverse encrypted byte inputted to the second register 22 using the fourth register 24 to finally perform the XOR. Get a single-byte plaintext that has been inversely encrypted.

8 is a block diagram of a rounding block decoder 12 according to an embodiment of the present invention, in order to decode one block by operating a round block unit that processes one round block 16 times to implement a 16-round DS decoding algorithm. As designed, the ECB and CBC modes have the same structure of the write shift unit RS. In the CFB mode, the encoder algorithm is used without using the DS decoder algorithm.

In the DS round block algorithm, the selective substitution unit (PC-1) for acquiring the 56-bit signal (K) value obtained by removing the parity bit from the initial and inverse initial substitution and the 64-bit key required only at the beginning and end of the DS is performed in the control register unit. Built in (11), only the other parts were designed to be processed by the rounding block decoder 12.

First, the input of the rounding block decoder 12 is an operation clock (RB-clock) of the rounding block decoder 12, an operation clock (TS-clock) of the TS stream, a signal (K) of 56 bits, and the control register unit 11. It consists of an input block (IN-BLK) and a data synchronization signal (IN-BLK-IN) in units of 64-bit blocks.

The block for the algorithm of the key generation unit, which first divides the 56-bit key into 28 bits for decryption, and shifts the right shift operation of the DS decryption algorithm by the value of the signal LS-SEL. (RS), and a selection switch which receives two 28-bit data shifted to the right side in which the bit or two bits are shifted to the right side in the reverse direction of encryption by the value of the signal LS-SEL, and generates a 48-bit key value. (PC-2).

The extended replacer (E-func) implements an algorithm for extending the right 32-bit value (lower bit value) of the 64-bit block to 48 bits. The 48-bit key and the extended replacer (E-func) obtained above. There is an exclusive logic unit (TAU) that XORs a 48-bit value through func). The S-box replacements S1 to S8 implement S-box substitution that makes the output value of the 48-bit exclusive logic unit (ATU) 32-bit values. Such 32-bit S-box values are simple replacements. P-func generates 32-bit substitution value, and finally XORs the left 32-bit value (higher bit value) that has not been used among this value and 64-bit input block (IN-BL). A 32-bit right-hand side is generated via an exclusive logic unit (X-func). The left 32 bits thus rounded are updated with the value of the right 32 bits of the input 64 bits.

The last right 32 bit value obtained by repeating this round 16 times becomes the upper 32 bit value of the 64-bit output value (OUT-BLK) as opposed to the input, and the last left 32 bit value is the lower 32 bit value. The output value OUT-BLK, which is the output 64-bit block value, and the output value OUT-BLK-OUT, which are the signals Validated, are transferred to the control register unit 1 by being the value.

17A to 17C are flowcharts illustrating the operation of a rounding block decoder in which an input block received from the control register unit 11 is processed and output by the rounding block decoder 12. First, a required clock is determined according to a mode. ECB. CBC mode uses a clock twice as fast as TS-clock, and CFB mode uses a clock 16 times faster. When the mode is determined, the input block IN-BLK from the control register unit 11 is loaded using the valid signal IN-BLOCK. The ECB, CBC and CFB modes are similar in operation, but the decoding time is different and the valid signal of the input signal (IN-BLOCK) is different. The 1-block data loaded in this way transmits 16 blocks of decoded data blocks to the control register unit 11 when the count reaches 17, that is, when 16 rounds of repetitions are completed. .

The apparatus for descrambling data of the TS bit string of the present invention, which operates as described above, has an advantage of efficiently decrypting encrypted data of the encrypted MPEG-2 TS bit string in various operation modes.

Claims (3)

A (correction) decryption system for decrypting encrypted data, comprising processing encrypted data of a TS bit sequence, a key for decrypting the encrypted data, and an input signal including an initialization vector to decipher the DS. A signal preprocessor 1 for outputting the required signal; The control register unit 11 for receiving the output signal of the signal preprocessing unit 1 and controlling the decryption operation of the encrypted data according to the operation mode and the encrypted data transmitted through the control register unit 11. DES decrypter (2; DES decrypter) consisting of a rounding block decoder 12 for decrypting by performing 16 roundings required by the DS standard using the key and the initial set vector. A device for descrambling data of a TS bit string. (Correction) The data signal eb according to claim 1, wherein the buffers BF2 and BF3 are connected to a buffer BF1 to which the data signal eb is input through a fifth register 25, respectively. Is connected to the buffers BF4 and BF5 and the initial replacement unit 27 via the first register 21 to the buffer BF3 to which the input is performed, and the buffer BF6 is connected to the buffer BF4 through the register 23. And a buffer BF7 through a second register 22 to which the output of the reverse initial replacement unit 28 is input to the buffer BF5, and a fourth register 24 to the buffer BF2. The buffer register BF6 is connected to the signal input unit 26, and the preliminary replacement unit 29 is connected to the first input unit 21, and the control register unit 11 is connected to the first register 21. And a data bit descrambling device of a TS bit string. 2. The write shift unit RS of claim 1, which divides a bit of the key KEY to shift a right shift operation of a DS decoding algorithm by a value of a signal LS-SEL. (E-func) that extends the value of the lower bit of the input block (IN-BL), while connecting the selection exchanger (PC-2) for generating a key value with data inputted to the (RS). To S-box substitution unit (S1 to S8) through the exclusive logic unit (TAU) to the selection substitution unit (PC-2) and the expansion substitution unit (E-func), and the S-box substitution An exclusive logic unit XORing the values of the upper bit side of the input block IN-BL and the output value of the simple replacing unit P-func through the simple replacing unit P-func to the units S1 to S8. A plurality of data bit descrambling apparatus of a TS bit string, characterized in that a plurality of configurations formed by connecting X-func are combined to form a rounding block decoder (12).