KR100294645B1 - Ferroelectric Memory - Google Patents

Abstract

The present invention provides a ferroelectric memory device having a stable data sensing margin and a data sensing method. The present invention provides a storage node for storing data and a first ferroelectric connected between the storage node and the data signal line. A data sensing method of a ferroelectric memory device comprising a capacitor and a second ferroelectric capacitor having one side node connected to the data signal line, wherein the other node of the second ferroelectric capacitor and the data signal line are pre-supplied with a half supply voltage. Occupying the first step; A second step of driving the storage node to a ground voltage after the first step; A third step of driving the other node of the second ferroelectric capacitor to a supply voltage after the second step; And a fourth step of sensing and amplifying data from the data signal line having the third step completed using the half supply voltage as a reference voltage.

Description

Ferroelectric Memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric random access memory (FeRAM), and more particularly to a ferroelectric memory device using a reference voltage for sensing and amplifying data from a memory cell directly as a half supply voltage (Half Vcc) rather than a dummy cell. will be.

As is well known, capacitors using ferroelectric materials have a hysteresis curve in the relationship between the voltage across the capacitor and the amount of charged charge. FIG. 1A shows a symbol of a ferroelectric capacitor formed between terminals a and b, and FIG. 1B shows an equivalent of a ferroelectric capacitor, and FIG. 1C shows a relationship of charge amount according to voltage between both terminals a and b of a capacitor. It is. Referring to FIGS. 1A, 1B, and 1C, when there is no potential difference across the ferroelectric capacitors a and b, the amount of charge maintained by polarization exists in two states, 'a' and 'b', so that no power is supplied. It can store binary data. When the information of '1' is stored as 'A' when there is no potential difference between a and b terminals, and the information of '0' is displayed as 'I', the terminal b is read to read the stored information. When a certain voltage (V) is applied, the polarization at the 'ga' position is dragged to the 'da' state to generate the amount of charge as DELTA Q1. At this time, since the state of polarization changes beyond the voltage (Vc) that can cause switching, as shown in FIG. 1B, the nonlinear capacitance (Csw) component during switching and the linear capacitance (Cln) component when not switching are simultaneously present. . In addition, the polarization at the position of 'I' is also drawn to the state of 'C', and since no switching occurs, only the linear capacitance (Cln) exists and generates a quantity of charge as ΔQ0. Due to the difference in the amount of charge caused by these two state changes, the ferroelectric capacitor is used as a storage means for the nonvolatile memory device.

2 is a circuit diagram corresponding to a core portion of a ferroelectric memory device according to the related art. In FIG. 2, a first bit line pair consisting of a right bit line bl0n and a sub bit line bl0bar, and a second bit line pair consisting of another right bit line bl1n and a sub bit line bl1bar are respectively connected. The circuits are shown.

Referring to FIG. 2, unit cells including one NMOS transistor and one ferroelectric capacitor are arrayed to form a cell array unit 130. Specifically, the NMOS transistor of the unit cell has a drain connected to the bit line and a gate connected to the word lines wl0, wl1 ... wln-2, wln-1, and the ferroelectric capacitor of the unit cell has a plate line. ) And the source terminal of the an-MOS transistor. Each bit line includes a bit line pull-down unit 110 for pulling down the bit line to the ground voltage in the standby state by the control signal pbl, and a positive bit line and a sub bit during read driving by the control signal. The sense amplifier 120 is configured to sense and amplify the voltage difference between the lines.

On the other hand, in order to read data from the cell, the data between the positive bit line and the sub bit line is sensed. In this case, when the unit cell connected to the positive bit line is selected, the sub bit line connected to the unselected cell is further selected. Since the reference voltage is received from the micelle 150, the voltage difference between the positive bit line and the sub bit line is sensed by the sense amplifier 120. In this case, the reference voltage is transmitted to the sub bit line by driving the reference voltage generated by driving the reference voltage transmitter 140 by the control signals dtg_even and dtg_odd.

In the dummy cell unit 150, the dummy positive bit line RBL is commonly connected to the first bit line pair bl0n and bl0bar, and the dummy sub bit line RBLB is connected to the second bit line pair bl1n and bl1bar. Are connected in common to each other, and two dummy cells DC1 and DC2 are connected between the dummy positive bit line RBL and the dummy sub bit line RBLB. In addition, the dummy positive bit line RBL and the dummy sub bit line RBLB include a transistor for pulling down the pair of dummy bit lines to the ground voltage in the standby state by the control signal prl, and the dummy by the control signal eq_rl. Transistors that equalize the bit line pairs are connected. Data "0" is always stored in the first dummy cell DC1 and data "1" is always stored in the second dummy cell DC1, so that the dummy word line rwl and the dummy plate line rpl are stored. When enabled and equalizing the dummy bit line pairs RBL and RBLB, a reference voltage corresponding to an intermediate level between '0' and '1' is transferred to the bit line.

However, ferroelectric capacitors have a characteristic aging phenomenon in which the amount of charge charged to a capacitor gradually decreases as the number of uses increases, so that the reference voltage induced from the dummy cell becomes unstable according to the frequency of use. As a result, the sensing margin is reduced, which is a big problem for the reliability of the memory. 3 shows that the hysteresis curve of the ferroelectric capacitor changes with age. That is, when a reference voltage is generated using a dummy cell as in the conventional method, since a dummy cell storing '1' and '0' is read, one dummy cell of the two cells is switched to cause aging as shown in FIG. This causes a change in the reference voltage. In particular, since a dummy cell is used for a bit line in which a plurality of memory cells are arrayed, the number of dummy cells is read more than the number of reads of the memory cells. Therefore, there is a problem in that the life of the device is determined according to the aging of the dummy cell.

The present invention has been made to solve the above problems, and an object thereof is to provide a ferroelectric memory device having a stable data sensing margin.

Another object of the present invention is to provide a data sensing method for obtaining a stable data sensing margin in a ferroelectric memory device.

1A shows a symbol of a ferroelectric capacitor;

1B is an equivalent circuit diagram of a ferroelectric capacitor;

Figure 1c is a hysteresis curve showing the characteristics of the ferroelectric capacitor,

2 is a circuit diagram corresponding to a core portion of a ferroelectric memory device according to the prior art;

3 is a diagram illustrating a aging phenomenon, which is a characteristic of a ferroelectric capacitor;

4 and 5 are views for explaining the technical principle of the present invention for using the half supply voltage (Vcc / 2) as a reference voltage,

6 is a core circuit diagram of a ferroelectric memory device according to an embodiment of the present invention;

7 is an exemplary view of a reference voltage generation circuit portion for generating a half supply voltage Vcc / 2;

8 is a timing diagram for a read operation in the embodiment of FIG. 6;

9 is a simulation result diagram for the circuit of FIG.

10 is a core circuit diagram of a ferroelectric memory device according to another embodiment of the present invention.

One characteristic of the present invention for achieving the above object is a ferroelectric memory device, the bit line, word line, and plate line; A memory cell comprising a storage node, a switch element switching between the bit line and the storage node in response to the word line signal, and a first ferroelectric capacitor connected between the storage node and the plate line; A second ferroelectric capacitor having one node connected to the plate line; Driving means connected to the other node of the second ferroelectric capacitor to selectively drive the other node of the second ferroelectric capacitor to a half supply voltage or a supply voltage; Reference voltage generating means for generating a half supply voltage; And sensing amplifying means for sensing and amplifying the signal of the plate line as a read data signal according to the output signal from the reference voltage generating means.

Preferably, the present invention is characterized in that: a bit line driving means connected to said bit line for selectively driving said bit line to a half supply voltage or a ground voltage; And plate line driving means connected to the plate line to selectively drive the plate line to a half supply voltage or a ground voltage.

More preferably, the present invention further comprises means for feeding back the output signal of the sense amplifying means to the bit line for re-storing after reading, wherein the second ferroelectric capacitor is the first ferroelectric capacitor. It is characterized by having an area of 1.5 times to 2.5 times.

In addition, another characteristic of the present invention for achieving the above object, the ferroelectric memory device, the first bit line, word line, and plate line; A memory cell comprising a storage node, a switch element switching between the first bit line and the storage node in response to the word line signal, and a first ferroelectric capacitor connected between the storage node and the plate line; A second ferroelectric capacitor having one node connected to the first bit line; Driving means connected to the other node of the second ferroelectric capacitor to selectively drive the other node of the second ferroelectric capacitor to a half supply voltage or a supply voltage; Precharge means for precharging a second bit line adjacent to the first bit line with a half supply voltage; And sensing amplifying means for sensing and amplifying the signal of the first bit line as a read data signal according to the signal of the second bit line precharged with the half supply voltage.

Preferably, the present invention further includes means for feeding back an output signal of the sense amplifying means to the first bit line for re-storing after reading, wherein the second ferroelectric capacitor is configured to provide the first ferroelectric. It is characterized by having an area of 1.5 to 2.5 times the capacitor.

The present invention also provides a storage node for storing data, a first ferroelectric capacitor connected between the storage node and a data signal line, and a second node having one side node connected to the data signal line. A data sensing method of a ferroelectric memory device including a ferroelectric capacitor, comprising: a first step of precharging the other node of the second ferroelectric capacitor and the data signal line with a half supply voltage; A second step of driving the storage node to a ground voltage after the first step; A third step of driving the other node of the second ferroelectric capacitor to a supply voltage after the second step; And a fourth step of sensing and amplifying data from the data signal line having the third step completed using the half supply voltage as a reference voltage. The method may further include a fifth step of driving the storage node to a half supply voltage before the second step.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 and 5 are views for explaining the technical principle of the present invention for using the half supply voltage (Vcc / 2) as a reference voltage. As shown in FIG. 4, a typical ferroelectric memory device includes one ferroelectric capacitor 410 connected between a storage node (a) of a cell (node connected to a switch transistor and a ferroelectric capacitor) and a plateline. When a separate drive ferroelectric capacitor 420 is connected to the plateline and the drive node b is driven at an appropriate voltage, the voltage signal from the plateline is set to Vcc / 2 as a reference voltage. Detection can be amplified.

That is, in FIG. 4, when the plate line is precharged to Vcc / 2 and the storage node a is also Vcc / 2, the voltage applied across the ferroelectric capacitor 410 of the cell is 0V, so the ferroelectric capacitor 410 is It exists in the state 'a' or 'b' of FIG. 5 (section A of FIG. 4). Subsequently, when the storage node (a) is fixed at a potential of 0 V, since the negative voltage is applied to the ferroelectric capacitor 410, the polarization state of the ferroelectric capacitor 410 is changed, and the amount of charge corresponding to the changed polarization state is the plate line parasitic capacitor 430. ) To change the plate line voltage (B section in FIG. 4). At this time, the plate line parasitic capacitor 430 is a main component of the ferroelectric capacitor connected to the unselected word line and the series connection capacitor of the junction transistor, and the parasitic capacitor existing between the plate line and the word line, and between the plate line and the substrate becomes a minor component. . The ferroelectric capacitor 410 has the ferroelectric capacitor 410. When you have been present in the "a" state in the Figure 5 data "0" storage node (a) is 0V and the shell, and changes to the "all" state ΔQ _zero charge changes The plate line potential, which was Vcc / 2, becomes a V1 voltage lower than Vcc / 2. On the other hand, if the ferroelectric capacitor 410 was in the 'I' state of the data '1', the storage node (a) is changed to the 'LA' state when the storage node (a) is 0V, and the change in the ΔQ ₁ charge amount occurs and the plate line potential is the V1 voltage. The higher V2 voltage is slightly lower than Vcc / 2. Subsequently, when the driving node b of the driving ferroelectric capacitor 420 is driven from Vcc / 2 to Vcc, the amount of charge induced from the driving ferroelectric capacitor 420 is reduced from the plate line parasitic capacitor 430 to the cell ferroelectric capacitor 410. ), The plate line becomes a V3 voltage higher than Vcc / 2 in the case of data '1', and the plate line becomes a V4 voltage lower than Vcc / 2 in the case of data '0'.

For this reason, when reading data from the ferroelectric memory cell, the bit line connected to the storage node a through the switch transistor is precharged to Vcc / 2 and driven to the ground voltage (0V), and the driving ferroelectric capacitor 420 If the driving node b is precharged to Vcc / 2 and then driven to Vcc, the data signal can be sensed and amplified from the plate line using the Vcc / 2 voltage as a reference voltage. If the area of the driving ferroelectric capacitor 420 is 1.5 times to 2.5 times the area of the ferroelectric capacitor 410 of the cell, the intermediate voltage between the V3 voltage and the V4 voltage on the plate line may be optimized to be Vcc / 2.

6 illustrates a core circuit of a ferroelectric memory device according to an embodiment of the present invention.

Referring to Figure 6, looks at the characteristic configuration of the ferroelectric memory device according to an embodiment of the present invention. Although FIG. 6 shows two column-based circuits adjacent to each other, for convenience of understanding in describing the configuration of FIG. 6, the circuits connected to the bit line bl0 and the plate line pl0 will be described here. .

First, an NMOS transistor 611 having a word line wl1 connected to a gate and a bit line bl0 connected to a source, one node connected to a drain of the NMOS transistor 611, and a plate line connected to the other node. The ferroelectric capacitor 612 to which (pl0) is connected forms a unit cell, and a plurality of unit cells are arrayed to form the ferroelectric memory cell array unit 610. In the unit cell, the node to which the NMOS transistor 611 and the ferroelectric capacitor 612 are connected is the storage node 613.

The bit line bl0 includes an NMOS transistor 621 that is gated by the control signal blv0 and drives the bit line bl0 with a ground voltage, and a bit line bl0 by Vcc / 2 (halfvcc) under gate control by the control signal blh0. The bit line driver 620 is formed of an NMOS transistor 622 for driving ().

In the plate line pl0, the NMOS transistor 631 drives the plate line pl0 with the ground voltage under gate control by the control signal plv0, and the plate line pl0 with Vcc / 2 (halfvcc) under gate control by the control signal plh0. The plate line driver 630 is formed of an MOS transistor 632 for driving the s).

The driving ferroelectric capacitor 640 is connected to the plate line pl0. In the driving ferroelectric capacitor 640, one electrode thereof is connected to the plate line pl0, and the other electrode connects the driving ferroelectric capacitor 640 to a ground voltage. And a driving circuit 650 for driving at Vcc / 2. The driving circuit 650 is gate-controlled by the control signal drvo to drive the other electrode of the driving ferroelectric capacitor 640 to ground voltage, and the gate-controlled by the control signal drho of the driving ferroelectric capacitor 640. It is composed of an enMOS transistor 652 which drives the other electrode at Vcc / 2 (halfvcc).

In the present embodiment, a separate reference voltage generation circuit unit 600 is provided instead of the dummy cell in the sense amplification, and the voltage of the Vcc / 2 level output from the reference voltage generation circuit unit 600 is used as the reference voltage halfvcc. . 7 shows a Vcc / 2 reference voltage generator circuit commonly used in DRAM. For example, the reference voltage generator circuit having the circuit configuration as shown in FIG. 7 can be configured as the reference voltage generator circuit 600.

In this embodiment, the sensing amplifier 670 receives a signal from the plate line pl0 to sense and amplify the data of the memory cell. In this case, the reference voltage is a reference voltage signal from the reference voltage generation circuit 600. halfvcc). The sense amplifiers are enabled and disabled by the control signal san. The plate line pl0 is connected to the data line PDL through the NMOS transistor 660 gate-controlled by the control signal psl0, and the data line PDL is connected to the input transistor gate of the sensing amplifier 670. .

On the other hand, since the stored data is lost if the ferroelectric memory device does not restore after reading the data, the read data must be restored. Therefore, the output of the sense amplifier 670 should be sent to the data output buffer 681 and at the same time fed back to the bit line (bl0) to be a means for restoring. For this purpose, the bit line bl0 is connected to the data line BDL through the fast transistor 690 gate-controlled by the control signal bsl0, and the data line BDL is connected to the output terminal of the sensing amplifier 670. A latch unit 682 controlled by the control signal lch is provided between the data line BDL and the output terminal of the sensing amplifier 670. The output terminal of the sensing amplifier 670 controls the gate of the control signal san for precharging. The receiving PMOS transistor 683 is connected.

FIG. 8 illustrates timing for a read operation in the embodiment of FIG. 6, through which the operation of FIG. 6 will be described in detail. Consider a case where a value stored in the ferroelectric capacitor 612 of a memory cell is read. Before the word line is enabled, plh0 is first enabled by the column address so that the selected plateline pl0 is precharged to the level Vcc / 2 at ground voltage 0V. The unselected plate line (e.g., pl1) has the control signal plv1 as Vcc and plh1 as 0v, so that the potential is fixed at 0V.

If the voltage of the storage node 613 of the selected cell is Vs, Equation 1 can be obtained.

[ Cc : Ferroelectric cell capacitance, Cj : Junction capacitance]

In the above Equation 1, since the ferroelectric cell capacitance Cc is much larger than the junction capacitance Cj due to the large dielectric constant, the voltage Vs of the storage node 613 is approximately Vcc / 2, so that the polarization state of the ferroelectric capacitor 612 is almost unchanged.

After the selected plate line pl0 is precharged to the level Vcc / 2, the word line wl0 is selected. At this time, both the selected bit line bl0 and the unselected bit line bl1 are fixed to 0V. When the wordline wl0 is enabled, the storage node 613 of the selected cell drops in potential from Vcc / 2 to 0V, so the polarization state of the ferroelectric capacitor 612 changes and causes a change in charge, which causes the Vcc / 2 voltage of the plate line pl0 to In case of '1', V2 is slightly lower than Vcc / 2, and in case of data '0', V1 is lowered to V1.

Thereafter, when the node connected to the driving ferroelectric capacitor 640 is applied from Vcc / 2 to Vcc with the control signal drv0 set to 'low', the plate line is induced to the voltage V3 for the data '1' and V4 for the data '0'. Since this principle has been described in detail with reference to FIG. 4, it will be omitted. In the induced voltage V3 or V4, when the control signal psl0 becomes 'high', the NMOS transistor 660 is turned on and transferred to the sensing amplifier 670 through the data line PDL, and the voltage of the data line PDL is equal to the voltage induced in the plate line pl0. When the same, the control signal psl0 is set to 'low' to turn off the NMOS transistor 660. The reason for turning off the NMOS transistor 660 connected to the control signal psl0 is to fix the voltage of the plate line pl0 to Vcc / 2 to restore the memory cell capacitor read after the data sensing to its original state. This is to avoid affecting this sense amplifier amplification. Subsequently, the sensing amplifier 670 is enabled by setting the control signal san to high. At this time, the reference voltage of the sense amplifier is Vcc / 2 (halfvcc). After the sense amplification, activate the control signal lch from 'low' to 'high' to get the read value from the output node output.

Since the read cell must be restored, the output of the sense amplifier 670 is fed back to the bit line bl0 and the control signal bsl0 is 'low' so that the bitline must be floated. If the data is '1', the output node output should be 'high', but if the bit line is 'low', if the data is '0', the output node output should be 'low' but the bit line should be 'high'. When the bit line is 'high', since the cell's switch transistor is an MOS transistor, the word line wl0 voltage must be Vcc + Vth to transfer the Vcc voltage to the storage node 613. Vth is the threshold voltage of NMOS transistor 611. In the case of data '0', the bit line bl0 becomes Vcc, and the voltage applied across the ferroelectric capacitor 612 becomes Vcc / 2. Thus, the polarization state moves to the 'la' state of FIG. 1c. In the case of data '1', the bitline bl0 becomes The voltage applied across the ferroelectric capacitor 612 at the ground voltage becomes -Vcc / 2, so that the polarization state is shifted to the "multi" state of FIG. Then, when the control signal bsl0 is applied as low and blh0 is applied as high, the voltage of the bit line bl0 becomes Vcc / 2. Therefore, the voltage applied across the ferroelectric capacitor 612 becomes 0V, and the data is '1'. In the case of '0', if the data is '0', it moves to the 'I' state and restores the original value.

After resave completes, the wordline wl0 voltage is pulled low from Vcc + Vth to maintain standby to prepare for the next cycle. At this time, when the voltages of both nodes of the ferroelectric capacitor 612 become Vcc / 2 in the standby state, the Vcc / 2 voltage of the storage node 613 will continue to decrease due to leakage current and eventually become 0 V. Therefore, the ferroelectric capacitor polarization state will be changed. The voltage at both nodes of the capacitor must remain at 0V. To do this, after the word line wl0 is turned off, the plateline voltage pl0 is driven from Vcc / 2 to 0V to maintain the voltage across the ferroelectric capacitor at 0V.

As described in the above operation, one driving ferroelectric capacitor 640 is attached to one plate line, and a plurality of cells are connected to the plate line so that the number of operation of the driving ferroelectric capacitor when the device is operated is determined in the memory cell. The driving ferroelectric capacitor 640 does not age since the polarization state does not occur when the driving capacitor is operated. In FIG. 8, the ferroelectric capacitor 612 of the cell is denoted as "Ferro Cap", and the driving ferroelectric capacitor 640 is denoted as "Driving Cap". Referring to the polarization state thereof, the driving ferroelectric capacitor 640 shows that the polarization state is not switched. have.

9 is a simulation result for the circuit of FIG. pl0 is the plateline voltage when data is stored with '1' and pl1 is the plateline voltage when data is stored with '0'. The driving circuit 650 drives the driving ferroelectric capacitor 640 from Vcc / 2 to Vcc while driving the word line wl high. It can be seen that pl0 is Vcc / 2 + ΔV1, Vcc / 2-ΔV0 (ΔV1 is about 200 mV, ΔV0 is about 250 mV). It can be seen that the detection amplification is normally performed, so that output node output0 has 'high' data and output node output1 has 'low' data.

10 shows a core circuit of a ferroelectric memory device according to another embodiment of the present invention. With reference to Figure 10 looks at the configuration according to another embodiment of the present invention. Another embodiment of the present invention has a method of detecting and amplifying a data signal induced in a selected bit line by using a signal of a bit line that is unselected and precharged with a half supply voltage (Vcc / 2) as a reference voltage signal. In this context, we look at its composition.

Referring to FIG. 10, a storage node 913, a switch element 911 that switches between a first bit line BL0 and the storage node 913 in response to a word line signal wl0, and the storage node. The first ferroelectric capacitor 912 connected between the 913 and the plate line PL0 constitutes a memory cell 910. One node of the second ferroelectric capacitor 920 is connected to the first bit line BL0, and the other node of the second ferroelectric capacitor 920 is half-supplied to the other node of the second ferroelectric capacitor 920. A driving circuit portion 930 for selectively driving at a voltage or a supply voltage is connected. The driving circuit 930 has the same configuration as the driving ferroelectric capacitor driving circuit portion 650 shown in FIG. On the other hand, the same circuits as the circuits connected to the first bit line are connected to the second bit line BL1 adjacent to the first bit line BL0 with the plate line PL0 as a common plate line. . In addition, a bit line precharge part 640 is connected to the first bit line BL0 and the second bit line BL1 for precharging itself to a half supply voltage when it is not selected. The sensing amplifier 650 senses and amplifies the signal of the first bit line BL0 and the signal of the second bit line BL1. Meanwhile, although not shown in FIG. 10, an apparatus for feeding back the output signal of the sensing amplifier 650 to the selected bit line is required for re-storing after reading, which may be easily implemented by those skilled in the art. . In another embodiment of the present invention, as in the exemplary embodiment, when the second ferroelectric capacitor has an area of 1.5 times to 2.5 times of the first ferroelectric capacitor, the voltage induced in the selected bit line may be optimized during reading.

This embodiment of the present invention having such a configuration, unlike the embodiment (Fig. 6), does not drive the selected plate line with the drive ferroelectric capacitor but drives the selected bit line with the drive ferroelectric capacitor. It's a way to sense and amplify data from In the sense amplification, the reference voltage signal becomes an unselected bit line signal, and the unselected bit line signal has a Vcc / 2 potential in a precharged state.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention adopts a method of precharging a bit line to VCC / 2 in a memory device using a ferroelectric as a memory cell, and makes it possible to sense and amplify the reference voltage as VCC / 2. This method reduces current consumption and shortens the amplification time during sensing amplification, enabling stable data sensing. In addition, since the dummy cell for generating the reference voltage is not used, the reliability of the device can be increased.

Claims (12)

In ferroelectric memory device, Bitlines, wordlines, and platelines; A memory cell comprising a storage node, a switch element switching between the bit line and the storage node in response to the word line signal, and a first ferroelectric capacitor connected between the storage node and the plate line; A second ferroelectric capacitor having one node connected to the plate line; Driving means connected to the other node of the second ferroelectric capacitor to selectively drive the other node of the second ferroelectric capacitor to a half supply voltage or a supply voltage; Reference voltage generating means for generating a half supply voltage; And Sensing amplifying means for sensing and amplifying a signal of the plate line as a read data signal according to an output signal from the reference voltage generating means; Ferroelectric memory device comprising a. The method of claim 1, Bit line driving means connected to said bit line for selectively driving said bit line to a half supply voltage or a ground voltage; And Plate line driving means connected to said plate line for selectively driving said plate line to a half supply voltage or a ground voltage; A ferroelectric memory device, characterized in that further comprises. The method according to claim 1 or 2, And the second ferroelectric capacitor has an area of 1.5 to 2.5 times the area of the first ferroelectric capacitor. The method according to claim 1 or 2, And means for feeding back the output signal of the sense amplification means to the bit line for re-storing after reading. The method according to claim 1 or 2, And a switching means for switching between the plate line and the input end of the sense amplification means. In ferroelectric memory device, First bit lines, word lines, and plate lines; A memory cell comprising a storage node, a switch element switching between the first bit line and the storage node in response to the word line signal, and a first ferroelectric capacitor connected between the storage node and the plate line; A second ferroelectric capacitor having one node connected to the first bit line; Driving means connected to the other node of the second ferroelectric capacitor to selectively supply a half supply voltage or a supply voltage to the other node of the second ferroelectric capacitor; Precharge means for precharging a second bit line adjacent to the first bit line with a half supply voltage; And Sensing amplification means for sensing and amplifying a signal of the first bit line as a read data signal according to a signal of the second bit line precharged with the half supply voltage; Ferroelectric memory device comprising a. The method of claim 6, And a means for feeding back the output signal of the sense amplifying means to the first bit line for re-storing after reading. The method according to claim 6 or 7, And the second ferroelectric capacitor has an area of 1.5 to 2.5 times the area of the first ferroelectric capacitor. A data sensing method of a ferroelectric memory device comprising a storage node for storing data, a first ferroelectric capacitor connected between the storage node and a data signal line, and a second ferroelectric capacitor having one node connected to the data signal line. To A first step of precharging the other node of the second ferroelectric capacitor and the data signal line with a half supply voltage; A second step of driving the storage node to a ground voltage after the first step; A third step of driving the other node of the second ferroelectric capacitor to a supply voltage after the second step; And A fourth step of sensing and amplifying data from the data signal line having the third step completed using the half supply voltage as a reference voltage; Data sensing method comprising a. The method of claim 9, And a fifth step of driving the storage node to a half supply voltage before the second step. In ferroelectric memory device, A memory cell having a first ferroelectric capacitor for storing data; A data signal line connected to one node of the first ferroelectric capacitor; A second ferroelectric capacitor having one node connected to the data signal line; First driving means connected to the other node of the second ferroelectric capacitor to drive the second ferroelectric capacitor at a half supply voltage; Second driving means connected to the other node of the second ferroelectric capacitor to drive the second ferroelectric capacitor to a supply voltage; Sensing amplification means for sensing and amplifying a signal of the data signal line using a signal having a half supply voltage as a reference voltage; Ferroelectric memory device comprising a. The method of claim 11, And the second ferroelectric capacitor has an area of 1.5 to 2.5 times the area of the first ferroelectric capacitor.