KR100281125B1 - Nonvolatile Ferroelectric Memory Device - Google Patents

Abstract

The present invention is to implement a stable sensing operation and to maintain a constant bit line induced voltage by the reference cell and the main cell, a plurality of sub-cell array and a plurality of main is formed in a direction crossing each of the sub-cell array A global bitline and at least one pair of reference global bitlines, a main local bitline and reference local bitlines formed corresponding to each of the main global bitline and the reference global bitline, and each of the local bitlines A main cell array unit including switching elements configured between global bit lines; A reference bit line control unit formed at a lower portion or an upper portion of the main cell array unit and configured as a reference sense amplifier configured to sense a signal applied through one bit line among the pair of reference global bit lines and output a reference voltage; A main bit line control unit formed at one side of the reference bit line control unit and configured to include a plurality of main sense amplifiers connected to each of the main global bit lines to receive the reference voltage and sense a signal applied through the corresponding global bit line; A word line driver formed on one side of the main cell array unit and outputting a driving signal for cell selection; And a plate line driver formed on the other side of the main cell array unit to output a drive signal for cell selection together with a drive signal of the word line driver.

Description

Nonvolatile Ferroelectric Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a nonvolatile ferroelectric memory device.

A next generation memory is a ferroelectric memory, or FRAM (Ferroelectric Random Access Memory), which has a data processing speed of about DRAM (Dynamic Random Access Memory), which is commonly used as a semiconductor memory device, and preserves data even when the power supply is turned off. It is attracting attention as an element.

FRAM is a memory device having a structure almost similar to that of DRAM, and uses a ferroelectric as a material of a capacitor and uses high residual polarization characteristic of the ferroelectric.

Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

1 is a characteristic diagram showing a hysteresis loop of a general ferroelectric.

As shown in FIG. 1, it can be seen that the polarization induced by the electric field maintains a constant amount (d, a state) without being eliminated due to the presence of residual polarization (or spontaneous polarization) even when the electric field is removed.

The d and a states correspond to 1 and 0, respectively, and are applied as a memory device.

Hereinafter, a nonvolatile ferroelectric memory device according to the related art will be described with reference to the accompanying drawings.

2 is a block diagram of a conventional nonvolatile ferroelectric memory cell composed of two unit cells.

Word line W / L formed in one direction, plate word line P / L (hereinafter referred to as "plate line") formed in parallel with word line W / L1, word line W / L and plate A plurality of bit lines (..., Bit_n, Bit_n + 1, ...) formed in a direction crossing the line (P / L), the bit lines, the word lines (W / L) and plate lines Unit cells C111, C121, ... are formed between (P / L).

In other words, the unit cell includes one transistor T1 and one ferroelectric capacitor FC1.

Referring to the driving circuit according to the conventional ferroelectric memory device as follows.

3A to 3B show a driving circuit for driving a conventional ferroelectric memory device.

The driving circuit for driving a ferroelectric memory having a conventional 1T / 1C structure includes a reference voltage generator 1 for generating a reference voltage, a plurality of transistors Q1 to Q4, a capacitor C1, and the like.

Since the reference voltage output from the reference voltage generator 1 cannot be directly supplied to the sense amplifier, a reference voltage stabilizer 2 for stabilizing the reference voltages of two adjacent bit lines, a plurality of transistors Q6 to Q7, The first reference voltage storage unit 3 and the transistors Q5 which store the reference voltages of logic values "1" and "0" in adjacent bit lines formed of capacitors C2 to C3, respectively, A first equalizer 4 for equalizing the bit lines, a first main cell array 5 connected to different word lines and plate lines for storing data, and a plurality of transistors Q10 to Q15 And a first sense amplifier unit 6 configured to sense data of a cell selected by the word line from among a plurality of cells of the first main cell array unit 5, including a P-sense amplifier (PSA), and the like. Other A second main cell array unit 7 connected to the draw line and the plate line to store data, and a plurality of transistors Q28 to Q29, capacitors C9 to C10, and the like, each have a logic value of "1". A second reference voltage storage unit 8 storing reference voltages of " and " and " 0 ", a plurality of transistors Q16 to Q25, an N-sense amplifier NSA, and the like. And a second sense amplifier unit 9 for sensing and outputting data of 7).

The data input / output operation according to the conventional ferroelectric memory device configured as described above is as follows.

4 is a timing diagram illustrating an operation of a write mode of a ferroelectric memory device according to the related art, and FIG. 5 is a timing diagram illustrating an operation of a read mode.

First, in the write mode, the chip enable signal CSBpad applied from the outside is activated from high to low. At the same time, if the write enable signal WEBpad is applied from high to low, the write mode is activated. Begins.

Then, when address decoding starts in the write mode, a pulse applied to the corresponding word line transitions from "low" to "high" so that the cell is selected.

As described above, in the section in which the word line maintains the "high" state, the "high" signal and the "low" signal of the predetermined section are sequentially applied to the corresponding plate line.

In order to write a logic value "1" or "0" to the selected cell, a "high" or "low" signal is applied to the corresponding bit line in synchronization with the write enable signal WEBpad.

That is, when the signal "high" is applied to the bit line and the signal applied to the plate line is "low" in the period in which the signal applied to the word line is "high", the logic value "1" is written in the ferroelectric capacitor.

When a low signal is applied to the bit line and the signal applied to the plate line is a high signal, a logic value "0" is written to the ferroelectric capacitor.

The operation for reading data stored in the cell by the operation of the write mode is as follows.

First, when the chip enable signal CSBpad is externally activated from "high" to "low", all bit lines are equipotentially "low" voltage by the equalizer signal before the corresponding word line is selected.

That is, when the "high" signal is applied to the equalizer unit 4 and the "high" signal is applied to the transistors Q18 and Q19 in FIGS. 3A to 3B, since the bit line is grounded through the transistor Q19, a low voltage is applied. Equipotential to (Vss).

The transistors Q5, Q18, and Q19 are turned off to deactivate each bit line, and then the address is decoded. The decoded address causes a "low" signal to transition to a "high" signal to select the corresponding cell. do.

A "high" signal is applied to the plate line of the selected cell to destroy the data corresponding to the logic value "1" stored in the ferroelectric memory.

If the logic value "0" is stored in the ferroelectric memory, the corresponding data is not destroyed.

The destroyed data and the unbroken data are outputted with different values according to the principle of the hysteresis loop as described above, so that the sense amplifier senses a logic value "1" or "0".

In other words, when data is destroyed, it is a case where d is changed from f to f as in the hysteresis loop of FIG. 1, and when data is not destroyed, it is when a case is changed from a to f.

Therefore, if the sense amplifier is enabled after a certain time has elapsed, it is amplified when data is destroyed and outputs a logic value "1", and when data is not destroyed, a logic value "0" is output.

As described above, after the data is output from the sense amplifier, the original data must be restored to deactivate the plate line from "high" to "low" while the "high" signal is applied to the corresponding word line.

In the conventional ferroelectric memory device having such a 1T / 1C structure, the data input / output operation requires more operation of the reference cell than the main cell.

The conventional ferroelectric memory device as described above has the following problems.

Since the reference cell is configured to be used for the read operation of many main cells more than several hundred times when the characteristics of the ferroelectric film are not completely secured, the reference cell needs to operate more than the main cell. The sharp deterioration causes the reference voltage to become unstable.

Therefore, the operating characteristics of the device are deteriorated and the life is shortened.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem, and keeps the bit line induced voltage by the reference cell and the bit line induced voltage by the main cell constant by equalizing the number of accesses of the main cell and the reference cell. It is an object of the present invention to provide a nonvolatile ferroelectric memory device capable of improving operating characteristics and extending lifespan.

1 is a characteristic diagram showing a hysteresis loop of a typical ferroelectric

2 is a cell diagram illustrating a conventional nonvolatile ferroelectric memory device.

3A to 3B illustrate a driving circuit for driving a conventional ferroelectric memory device.

4 is a timing diagram illustrating an operation of a write mode of a ferroelectric memory device according to the related art.

5 is a timing diagram illustrating an operation of a read mode.

6 is a configuration diagram of a cell array according to a first embodiment of the nonvolatile ferroelectric memory device of the present invention.

FIG. 7 is a block diagram illustrating a cell array when the FIG. 6 is repeatedly configured.

8 is a configuration diagram of a main cell array unit including a plurality of sub cell array units;

9 is a configuration diagram of a main cell array unit of FIG. 6;

FIG. 10 is a detailed configuration diagram of the subcell array unit of FIG. 8.

11 is an enlarged view of a portion “A” of FIG. 10.

FIG. 12 is a block diagram of the main cell array unit, the main bit line control unit, and the response bit line control unit in the configuration block of FIG. 6;

FIG. 13 is a diagram illustrating the main bit line control unit and the reference bit line control unit in more detail among the building blocks of FIG. 6; FIG.

14 is a diagram illustrating in detail a bit line precharge circuit according to a first exemplary embodiment of the present invention.

15A is a view showing a first embodiment of a bit line precharge level supply unit according to the present invention;

15B is a view showing a second embodiment of the bit line precharge level supply unit according to the present invention;

15C is a view showing a third embodiment of the bit line precharge level supply unit according to the present invention;

16A is a block diagram illustrating a simplified configuration of a reference sense amplifier according to the present invention.

16B is a block diagram of another embodiment of a reference sense amplifier according to the present invention;

17A shows a first embodiment of a level shifter in accordance with the present invention;

Figure 17b illustrates a second embodiment of a level shifter in accordance with the present invention.

FIG. 18 is a detailed view of a first embodiment of a sense amplifier in accordance with a nonvolatile ferroelectric memory device of the first embodiment of the present invention;

19 illustrates a second embodiment of a sense amplifier in accordance with a nonvolatile ferroelectric memory device of the first embodiment of the present invention.

20 is an operation timing diagram according to the sense amplifier of FIG. 18.

21 is an operation timing diagram in a lido mode according to the sense amplifier of FIG. 18.

FIG. 22 is an operation timing diagram in a write mode according to the sense amplifier of FIG. 18.

23A is an operation timing diagram according to the sense amplifier of FIG. 19.

FIG. 23B is a view illustrating comparison between signals used in the sense amplifier of FIG. 19 and the REFCON signal used in the level shifter of FIG. 17B.

24 is a configuration diagram of a cell array in a nonvolatile ferroelectric memory device according to a second embodiment of the present invention.

FIG. 25 is a diagram illustrating the main cell array unit in the configuration of FIG. 24 in more detail.

FIG. 26 is a diagram illustrating the first main bit line control unit and the first reference bit line control unit in more detail.

FIG. 27 is a diagram illustrating in more detail the second main bit line control unit and the second reference bit line control unit in the configuration of FIG. 24; FIG.

Explanation of symbols for main parts of the drawings

61,201: main cell array unit 63: word line driver

65: plate line driver 67: main bit line control unit

69: reference bit line control unit

61_1,61_2,61_3, ...: sub cell array unit

75_1,75_2, ...: Main sense amplifier 77a: Reference sense amplifier

71_1,71_2, ...: bit line equalization switch

72_1,72_2, ...: bit line precharge switching unit

100: first amplifying unit 103: second amplifying unit

A nonvolatile ferroelectric memory device of the present invention for achieving the above object is a plurality of sub-cell arrays, a plurality of main global bit lines and at least one pair of reference global bits formed in a direction crossing each of the sub-cell arrays Lines, main local bit lines and reference local bit lines formed corresponding to the main global bit lines and the reference global bit lines, and switching elements configured between the local bit lines and the corresponding global bit lines. A main cell array unit; A reference bit line control unit formed at a lower portion or an upper portion of the main cell array unit and configured as a reference sense amplifier configured to sense a signal applied through one bit line among the pair of reference global bit lines and output a reference voltage; A main bit line control unit formed at one side of the reference bit line control unit and configured to include a plurality of main sense amplifiers connected to each of the main global bit lines to receive the reference voltage and sense a signal applied through the corresponding global bit line; A word line driver formed on one side of the main cell array unit and outputting a driving signal for cell selection; And a plate line driver formed on the other side of the main cell array unit to output a drive signal for cell selection together with a drive signal of the word line driver.

Hereinafter, a nonvolatile ferroelectric memory device of the present invention will be described with reference to the accompanying drawings.

6 is a block diagram illustrating a cell array according to a nonvolatile ferroelectric memory device according to a first embodiment of the present invention.

As shown in FIG. 6, the main cell array unit 61, the word line driver unit 63 formed on one side of the main cell array unit 61, and the other side of the main cell array unit 61 are formed. A plate line driver 65, a main bit line control unit 67 formed below the main cell array unit 61, and a reference bit line control unit 69 formed on one side of the main bit line control unit 67. It is configured to include.

Here, the main cell array unit 61 is composed of several cell array units again internally.

When the configuration of FIG. 6 is repeatedly configured, the structure shown in FIG. 7 is obtained.

8 is a detailed configuration diagram of the main cell array unit according to the present invention. As described above, the main cell array unit includes a plurality of cell array units (hereinafter, referred to as a “sub cell array unit”).

As such, the main cell array unit is composed of the sub cell array units 61_1, 61_2, 61_3,... 61_n, and the two subcell array units are not activated at the same time.

9 is a view illustrating FIG. 8 in more detail.

As shown in FIG. 9, a plurality of global bit lines Blg_n, Blg_n + 1, ... are formed across the sub-cell array units 61_1, 61_2,...

In addition, the local bit lines BLL1_n, BLL2_n, ..., BLLn_n correspond to the global bit lines BGL_n, Blg_n + 1, ... in the sub-cell array units 61_1, 61_2, ..., respectively. It is composed.

That is, switching elements SW11, SW12, ... SW1n (SW21, SW22, ... SW2n) (SWn1, SWn2, ... SWnn) are formed between each local bit line and the global bit line. The local bit line and the global bit line are electrically connected to each other.

10 shows one sub cell array unit in more detail.

As shown in Fig. 10, a word line pair consisting of a word line W / L and a plate line P / L is repeatedly composed of several pairs.

And a plurality of global bit lines (..., BLG_n, BLG_n + 1, ...) in a direction crossing the word line (W / L1, P / L1, ... W / Ln, P / Ln) pairs. Are formed.

Unit cells C111, C112, ..., C11n / C121, C122, ..., C12n / C1n1 for each local bit line intersecting the paired word line (W / L) and plate line (P / L) , C1n2, ..., C1nn) are connected.

Switching elements are configured between the last bit of the local bit line and the corresponding global bit line to transfer data of a selected cell among a plurality of cells connected to the local bit line to the global bit line.

In the sub cell array unit configured as described above, a process of selecting a cell is as follows.

As described above, the main cell array unit is implemented by a repetitive configuration of the sub cell array units as shown in FIG. 10.

Only one subcell array unit of the plurality of subcell array units is activated, among which only a pair of word lines W / L and plate lines P / L are activated.

Therefore, when a pair of word lines and plate lines are activated, the unit cells connected to the activated word lines W / L and plate lines P / L are transferred to the corresponding global bit lines through the corresponding local bit lines. do.

The global bitline transfers the cell data transferred from the local bitline to the bitline control unit (not shown) through the switching element.

A sense amplifier (not shown) is connected to each global bit line to the bit line controller.

Therefore, only data output from one sense amplifier among the plurality of sense amplifiers is output to the outside through the data line.

FIG. 11 illustrates a portion “A” of FIG. 10 in more detail, in which unit cells are formed between a word line (W / L), a plate line (P / L), and a local bit line, and a local bit line. At the end of, it shows that the switching element is connected to the corresponding global bit line.

The unit cell is composed of one transistor and one ferroelectric capacitor, the gate of each transistor is connected to a corresponding word line, one terminal of the ferroelectric capacitor is connected to the drain (or source) of the transistor, and the other terminal is It is connected to the corresponding plate line.

FIG. 12 is a detailed configuration diagram of FIG. 6 and shows the main cell array unit 61, the main bit line control unit 67, and the response bit line control unit 69.

As described above, the main cell array unit 61 includes a plurality of sub cell array units 61_1, 61_2,...

The main global bit lines BLK_n, Blg_n + 1, ..., which cross the sub-cell array units 61_1, 61_2,..., Are connected to the main bit line control unit 67 and the reference global bit lines. BLRG_1 and BLRG_2 are connected to the reference bit line control unit 69.

Here, the reference bit line controller 69 accommodates two reference global bit lines BLRG_1 and BLRG_2.

As shown in the figure, in each sub cell array unit, main local bit lines are configured to correspond to the main global bit line.

For example, a plurality of main local bit lines BLL1_n, BLL2_n, ... are configured in the first main global bit line Blg_n.

The switching elements SW11, SW21, ... are configured between the corresponding main local bit line and the corresponding main global bit line.

Reference local bit lines BLLR1_1, BLLR2_1, ... / BLLR1_2, BLLR2_2, ... / ... / BLLR1_n, BLLR2_n, ... are configured to correspond to the reference global bit lines BLRG_1 and BLRG_2. .

The switching elements SWR11, SWR21 / SWR12, SWR22 / SWR1n, SWR2n, ... are formed between the reference local bit line and the reference global bit lines BLRG_1 and BLRG_2.

Accordingly, any sub cell array unit among the sub cell array units 61_1, 61_2, ... is selected, and the main local bit line in the sub cell array unit is connected to the main global bit line, thereby finally controlling the main bit line. Data is passed to the section 67.

Similarly, the reference local bit line in the corresponding sub cell array unit is connected to the corresponding reference global bit line, and finally data is transferred to the reference bit line control unit 69.

FIG. 13 is a diagram illustrating the main bit line control unit and the reference bit line control unit in more detail.

As shown in FIG. 13, the main sense amplifiers SA1, SA2, ..., 67_1, 67_2, ... are connected to the main global bit lines Blg_n, Blg_n + 1, ..., respectively. do.

One of two reference global bit lines BLRG_1 and BLRG_2 is connected to a reference sense amplifier 69_1, and a reference voltage CREF output from the reference sense amplifier 69_1 is connected to the main sense amplifiers 67_1 and 67_2. Commonly applied per ..)

In this case, a bit line precharge circuit (BPC: 68_1, 68_2, ...) is disposed between the main global bit lines BLK_n and BLG_n + 1 or BLG_n + 1 and BLG_n + 2, which are adjacent to each other. Is composed.

A bit line precharge circuit 70_1 is also configured between the last main global bit line Blg_n + n and the reference global bit line BRG_2 connected to the reference sense amplifier 69_1.

A constant voltage CONSTANT VOLTAGE is applied to one reference global bit line BLRG_1 that is not connected to the reference sense amplifier 69_1.

14 illustrates the bit line precharge circuit in detail according to the first embodiment of the present invention.

As shown in FIG. 14, a bit line equalization configured between a plurality of global bit lines Blg_n, Blg_n + 1, ..., and each of the global bit lines Blg_n, Blg_n + 1, ... The switch unit BQESW 71_1, 71_2, ... and the signal BEQLEV output from the bit line precharge level supply unit (not shown) may be used for the respective global bit lines Blg_n, Blg_n + 1,

Bitline precharge switch unit (BPCSW) 72_1, 72_2, ... for switching to ...)

It is configured to include.

The bit line equalization switch unit 71_1, 71_2,..., Or the bit line precharge switch unit 72_1, 72_2,... Includes an NMOS transistor.

Therefore, the level of the signal output from the bit line precharge level supply unit is equal to or slightly higher than the threshold voltage of the NMOS transistor.

As a result, the output signal of the bit line precharge level supply unit precharges the level of the corresponding global bit line through the bit line precharge switch unit 72_1, 72_2,...

The bit line equalization switch unit 71_1, 71_2,... Is turned on by a switch control signal to equalize two adjacent global bit lines to the same level.

15A is a detailed block diagram of the first embodiment of the bit line precharge level supply unit supplying the bit line precharge level.

As shown in Fig. 15A, the first PMOS transistor MP1 and the source are connected to the power supply terminal Vcc and controlled by the activation signal EQLEN for activating the bit line precharge level supply. A second PMOS transistor MP2 connected to a drain of the first PMOS transistor MP1 and having a drain and a gate connected in common, and the second PMOS transistor with respect to a drain of the first PMOS transistor MP1; A first NMOS transistor MN1 connected in parallel with the transistor MP2 and having a gate connected to a gate of the second PMOS transistor MP2 in common, and serially connected to the second PMOS transistor MP2. Is connected to the drain of the second PMOS transistor MP2, and the gate and the drain are respectively connected to the drain of the NMOS transistor MN1. A third NMOS transistor MN3 connected in common with the source connected to the ground terminal Vss, and a fourth gate connected to a drain of the first NMOS transistor MN1 and controlled by the drain voltage. A fifth NMOS transistor MN5 configured to face the NMOS transistor MN4 and the fourth NMOS transistor MN4 and having a drain connected to a drain of the fourth NMOS transistor MN4 in common; A sixth NMOS transistor MN6 connected to a common drain of the fourth and fifth NMOS transistors MN4 and MN5 and a source connected to a ground terminal, a source of the fourth NMOS transistor MN4 and the source; The fourth PMOS transistor MP4 connected between the drain of the first PMOS transistor MP1 and the source of the fifth NMOS transistor MN5 and the drain of the first PMOS transistor MP1 are connected. Being A third PMOS having a PMOS transistor MP5 and a drain of the first PMOS transistor MP1 in parallel with the first NMOS transistor MN1 and having a drain and a gate connected in common. A seventh NMOS transistor MN7 configured to face the transistor MP3 and the third PMOS transistor MP3 and having a gate connected to the gate of the third PMOS transistor MP3 in common; An eighth NMOS transistor MN8 connected to the drain of the seventh NMOS transistor MN7, and a source connected to the drain of the third PMOS transistor MP3, and the fourth PMOS transistor MP4. A ninth NMOS transistor MN9 and a collector connected to the seventh NMOS transistor MN7 in series and controlled by a drain voltage of the NMOS transistor MN7, and an emitter is connected to a drain of the ninth transistor MN9, It is configured to include a bipolar transistor (PNP1) which base is connected to the ground terminal in common.

Here, the fifth NMOS transistor MN5 is controlled by a bit line precharge voltage for precharging the bit line.

The operation of the bit line precharge level supply unit will now be described in detail.

As shown in FIG. 15A, when the activation signal of the bit line precharge level supply part transitions low during the normal operation, the first PMOS transistor MP1 is activated to bring the potential of the node N1 to the high level.

Initially, when the drain side voltage of the second NMOS transistor MN2, that is, the node N2 is low, the second PMOS transistor MP2 is turned on to increase the level of the node N2.

Accordingly, the first NMOS transistor MN1 having the gate connected to the node N2 is turned on to increase the level of the node N3.

When the level of the node N3 rises above the threshold voltage of the third NMOS transistor MN3, the third NMOS transistor MN3 is turned on to emit current to the ground terminal.

Thus, the level of node N3 is fixed to the threshold voltage.

Since the second NMOS transistor MN2 is turned on by the level of the node N3, the level of the node N2 is gradually lowered.

When the level of the node N2 is lowered, the on resistance of the first NMOS transistor MN1 increases, resulting in a decrease in current supplied to the node N3.

Accordingly, the threshold voltage level is provided by using a feedback loop of the first NMOS transistor MN1 and the second PMOS transistor MP2, the second NMOS transistor MN2, and the third NMOS transistor MN3. The voltage at node N3 is obtained.

On the other hand, if node N7 is initially low, the third PMOS transistor MP3 is turned on to raise the level of node N7.

When the level of the node N7 rises above the threshold voltage of the seventh NMOS transistor MN7, the seventh NMOS transistor MN7 is turned on to discharge current to the ground terminal through the bipolar transistor PNP1 connected to the node N8. do.

Here, the bipolar transistor PNP1 is a PNP bipolar transistor.

Therefore, the level of the output terminal, that is, the output terminal of the bit line precharge level supply unit, is fixed at the same threshold voltage level as that of the node N3.

Here, the bipolar transistor PMP1 functions as a PN diode in which a collector and a base are connected to a ground terminal in common, and an emitter is connected to a node N8.

In addition, since the eighth NMOS transistor MN8 is turned on by the output terminal of the bit line precharge level supply unit maintaining the threshold voltage level, the voltage of the node N7 is lowered.

When the voltage of the node N7 decreases, the on resistance of the seventh NMOS transistor MN7 increases to decrease the current applied to the output terminal of the bit line precharge level supply unit.

Accordingly, threshold voltage levels are provided by using feedback loops of the seventh, eighth, and ninth NMOS transistors MN7, MN8, and MN9, the third PMOS transistor MP3, and the bipolar transistor PNP1 operating as a PN diode. The output voltage of is obtained.

Here, the fourth, fifth, and sixth NMOS transistors MN4, MN5, and MN6 and the fourth and fifth PMOS transistors MP4 and MP5 form an amplifier, and thus, the fourth and fifth NMOS transistors. Amplify the output of node N4 according to the input of (MN4, MN5).

In the bit line precharge level supply unit according to the present invention operating as described above, how the voltage of the node N3 becomes equal to the voltage of the output terminal (output of the bit line precharge level supply unit) will be described.

The voltage of the node N3 is used as the gate input of the fourth NMOS transistor MN4, and the output terminal voltage is used as the gate input of the fifth NMOS transistor MN5.

If the voltage at node N3 is greater than the voltage at the output terminal, the voltage at node N4 is reduced and the voltage at node N5 is amplified.

The smaller node N4 is fed back to the ninth NMOS transistor MN9 to increase the ON resistance of the ninth NMOS transistor MN9, thereby reducing the amount of current emitted to the output stage, thereby raising the output stage level. do.

If the voltage of the node N3 is smaller than the voltage of the output terminal, the voltage of the node N5 becomes small and the voltage of the node N4 becomes large.

The increased voltage of the node N4 is fed back to the ninth NMOS transistor MN9 to reduce the ON resistance of the ninth NMOS transistor MN9, thereby increasing the amount of current discharged to the output stage, thereby reducing the level of the output stage. .

At this time, in order to prevent the level of the output terminal from being excessively reduced, a bipolar transistor PNP1 operating as a PN diode is configured between the node N8 and the ground terminal, that is, the PN diode is turned off below the threshold voltage of the PN diode so that a further current Suppress the release.

15B illustrates a second embodiment of the bit line precharge level supply unit according to the present invention.

As shown in Fig. 15B, the first PMOS transistor MP1 and the source are connected to the power supply terminal Vcc and controlled by the activation signal BQLEN for activating the bit line precharge level supply, respectively. Of the second PMOS transistor MP2 and the third PMOS transistor MP3 and the third PMOS transistor MP3 branched to a drain of the first PMOS transistor MP1 and commonly connected to a gate thereof. A first NMOS transistor MN1 that is controlled by a drain voltage and selectively outputs the ground voltage, is connected between the second PMOS transistor MP2 and the first NMOS transistor NM1, and applied externally. The second NMOS transistor MN2 controlled by the reference voltage REF_IN and the third PMOS transistor MP3 and the first NMOS transistor MN1 are connected to an output terminal (no De 1) A fourth PMOS transistor MP5 and a fifth P branch connected to a third NMOS transistor MN3 controlled by a voltage, a drain of the first PMOS transistor MP1, and having a gate connected in common. A fourth NMOS transistor MN4 controlled by a gate voltage of the MOS transistor MP5, the gate voltages of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5, and selectively outputting a ground voltage; A source is connected to the drain of the first PMOS transistor MP1, and the fifth NMOS transistor MN5 and the fifth NMOS transistor MN5 are controlled by the drain voltage of the fifth PMOS transistor MP5. And the drain of the sixth NMOS transistor MN6 connected between the gate and the drain of the NMOS transistor MN2 and controlled by the drain voltage of the second NMOS transistor MN2. A seventh NMOS transistor MN7 and a drain voltage of the second NMOS transistor MN2 connected by the fourth PMOS transistor MP4 and the fourth NMOS transistor NM4. Controlled by the drain voltage of the eighth NMOS transistor NM8 and the second NMOS transistor MN2 connected between the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4. A ninth NMOS transistor NM9 having a drain connected to the output terminal (node 1), a source connected to a source and ground terminal Vss of the ninth NMOS transistor NM9, and having a gate and a drain connected in common; It consists of 10 transistors NM10.

Here, the drain and the gate of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected in common.

The bit line precharge level supply unit according to the second embodiment of the present invention configured as described above compares the reference voltage input from the outside with the voltage of the output terminal (node 1) so that the level of the output terminal is always a constant level.

That is, since the level of the output terminal is connected to the bit line, there may be a change in the level. As in the second embodiment of the present invention, the bit line precharge level supply unit is configured to apply the level of the input reference voltage to the output terminal without change. As a result, a stable output level can be obtained at all times.

FIG. 15C shows a third embodiment of the bit line precharge level supply unit of the present invention.

As shown in Fig. 15C, the configuration is similar to that of the second embodiment described above. However, to further stabilize the level of the troops, the following configuration was added.

That is, as illustrated in FIG. 15C, the branch connected between the power supply terminal Vcc and the first PMOS transistor MP1 and controlled by the activation signal BQLEN for activating the bit line precharge level supply unit. A sixth PMOS transistor MP6 and a seventh PMOS transistor MP7 and an eleventh NMOS transistor MN11 connected in series between a ground terminal Vss of the sixth PMOS transistor MP6. .

Here, the drain and the gate of the seventh PMOS transistor MP7 are connected in common, and the gate of the eleventh NMOS transistor MN11 is connected in common with the drain so that the gate of the second NMOS transistor MN2 is connected. Is applied to.

The bit line precharge level supply unit according to the third exemplary embodiment also changes the drain voltage of the first PMOS transistor MP1 when the level of the output terminal changes.

Since the fluctuation of the drain voltage of the first PMOS transistor MP1 eventually causes the level of the output terminal to fluctuate, the output terminal (node 1) is influenced by the power supply voltage Vcc to prevent such a cause. Approved to places that do not have.

Therefore, the precharge level of the output stage can be applied at a more stable level.

16A is a simplified block diagram of a reference sense amplifier according to the present invention.

As shown in FIG. 16A, the reference sense amplifier configured in the reference bit line control unit receives the signal of the reference global bit line BLRG_2 and shifts the level of the signal to sense the main sense amplifiers 67_1, 67_2,... The level shifter 80 outputs a reference voltage CREF applied to the signal, and a pull-down control unit 80a which pulls down the reference bit line by receiving the signal of the reference global bit line BLRG_2.

On the other hand, as shown in Figure 16a, in addition to the method of outputting the reference voltage applied to the main sense amplifier by shifting the level using the level shifter 80, as shown in Figure 16b, without using the level shifter, It is also possible to configure only the down and pull-up control unit 81a to use the signal of the reference global bit line as the reference voltage CREF.

When the level shifter does not need to be used as shown in Fig. 16B, it requires a few hundred bits or less such as an IC card that does not require a large capacity. Since the number of sense amplifiers is not large, a sufficient reference voltage can be made even with a high signal. Because.

However, as shown in FIG. 16A, when the number of sense amplifiers is large, a reference voltage is generated with a low signal using a level shifter.

Here, the level shifter shown in FIG. 16A will be described in more detail.

17A shows a first embodiment of the level shifter shown in FIG. 16A.

As shown in FIG. 17A, the first PMOS transistor MP1 and the first PMOS transistor, which are controlled by the enable signal LSEN that enables the level shifter and whose source is connected to the power supply terminal Vcc, A first N-MOS transistor MP2 and a third PMOS transistor MP3 branched from the drain of the MP1 and a first N < " > controlled by a reference global bit line and connected to the second PMOS transistor MP2. A MOS transistor MN1, a second NMOS transistor MN2 configured between the first NMOS transistor MN1 and the third PMOS transistor MP3, the first NMOS transistor MN1, and a ground In parallel with the third PMOS transistor MP3 between the third NMOS transistor MN3 configured between the stage Vss and between the first PMOS transistor MP1 and the second NMOS transistor MN2. Fourth coat formed by A fourth NMOS transistor MN4 which is controlled by a transistor MP4, an output signal of the third PMOS transistor MP3 and whose source is connected to the first PMOS transistor MP1, the ground terminal and the The fifth NMOS transistor MN5 formed between the fourth NMOS transistor MN4, the fifth PMOS transistor MP5 formed between the first PMOS transistor MP1 and the output terminal CREF, and the global A sixth NMOS transistor MN6 controlled by a signal of a bit line, a sixth PMOS transistor MP6 formed between the sixth NMOS transistor MN6 and the first PMOS transistor MP1, A gate is connected in common with the gate of the sixth PMOS transistor MP6, and a source is connected to the seventh PMOS transistor MN7 connected to the drain of the first PMOS transistor MP1, and the sixth NMOS Transges The sixth NMOS transistor between the seventh NMOS transistor MN7 formed between the MN6 and the seventh PMOS transistor MP7, and the ground terminal Vss and the seventh NMOS transistor MN7. And an eighth NMOS transistor MN8 connected in parallel with MN6.

The operation of the level shifter according to the first embodiment configured as described above is as follows.

In FIG. 17A, the signal LSEN applied to the gate of the first PMOS transistor MP1 is a signal for activating the level shifter.

That is, the activation signal LSEN goes low during operation to output the signal CREF normally.

When the chip is inactive, the LSEN signal is pulled high to block current flow.

When LSEN goes low, the first PMOS transistor MP1 is activated to bring the node N1 to the high level.

Initially, if node N3 is low, the fourth PMOS transistor MP4 is turned on to raise the level of node N3.

Accordingly, the fourth NMOS transistor MN4 is turned on to increase the level of the output terminal CREF. The level of the output terminal may be equal to or smaller than the voltage of the reference global bit line BLRG_2.

Here, since the first, second, and third NMOS transistors MN1, MN2, and MN3 and the second and third PMOS transistors MP2 and MP3 constitute one amplifier, the first NMOS transistor MN1 is formed. ) And the output of the node N3 are amplified by the input of the second NMOS transistor MN2.

The sixth, seventh, and eighth NMOS transistors MN6, MN7, and MN8 and the sixth and seventh PMOS transistors MP6 and MP7 also form one amplifying unit, and thus the sixth NMOS transistor MN6. ) And the output of the node N5 are amplified according to the input of the seventh NMOS transistor MN7.

Here, when the size of the first and fifth NMOS transistors MN1 and MN5 is larger than the second and seventh NMOS transistors MN2 and MN7, the voltage at the output terminal CREF may be greater than that of the global bit line. It can be enlarged in proportion to the size difference.

On the contrary, when the size of the first and sixth NMOS transistors MN1 and MN6 is smaller than the second and seventh NMOS transistors MN2 and MN7, the voltage of the output terminal CREF is larger than the global bit line. It can be made small in proportion to.

If the size of the first and second NMOS transistors MN1 and MN2 and the size of the second and seventh NMOS transistors MN2 and MN7 are the same, the voltage at the output terminal may be equal to the voltage of the global bit line. can do.

Here, the operation of the level shifter when the sizes of the first and sixth NMOS transistors MN1 and MN6 and the second and seventh NMOS transistors MN2 and MN7 are the same will be described below.

First, when the voltage of the global bit line is greater than the output terminal CREF, the voltage of the node N2 is reduced by the first and second NMOS transistors MN1 and MN2 and the voltage of the node N3 is amplified to be large.

The increased voltage of the node N3 is fed back to the fourth NMOS transistor MN4 to reduce the on resistance of the fourth NMOS transistor MN4, thereby increasing the amount of current flowing into the output terminal CREF. Raise the voltage.

Thereafter, the voltage of the node N5 is reduced and the voltage of the node N6 is amplified by the sixth and seventh NMOS transistors MN6MN7.

Since the voltage of the small node N5 is fed back to the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 to reduce the on resistance of the fifth NMOS transistor MN5, a current flows into the output terminal. The amount increases, resulting in an increase in the output voltage.

Therefore, the voltage rise occurs quickly by the fourth NMOS transistor MN4 and the fifth PMOS transistor MP5.

If the voltage of the global bit line is smaller than the voltage of the output terminal CREF, the voltage of the node N2 is increased and the voltage of the node N3 is small by the first NMOS transistor MN1 and the second NMOS transistor MN2. Amplify to lose.

The smaller node N3 is fed back to the fourth NMOS transistor MN4 to increase the on resistance of the fourth NMOS transistor MN4, thereby reducing the amount of current flowing into the output terminal CREF.

Therefore, the voltage at the output terminal CREF is reduced.

Thereafter, the voltage of the node 5 is increased by the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 so that the voltage of the node 6 is reduced.

The increased voltage of the node N5 is fed back to the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 to reduce the on resistance of the fifth NMOS transistor MN5, thereby reducing the fifth PMOS transistor ( Increase the On resistance of MP5).

Therefore, the amount of current flowing into the output terminal CREF decreases, and as a result, the voltage of the output terminal decreases.

As a result, the voltage drop occurs quickly by the fifth NMOS transistor MN5.

Meanwhile, FIG. 17B shows a second embodiment of the level shifter of the present invention.

As shown in FIG. 17B, a first PMOS transistor MP1 controlled by an enable signal LSEN for enabling a level shifter and a source connected to a power supply terminal Vcc, and the first PMOS transistor ( The second PMOS transistor MP2 and the third PMOS transistor MP3 branched from the drain of the MP1 and the signal BLRG_2 of the reference global bit line are controlled by the second PMOS transistor MP2. The first NMOS transistor MN1 and a source are connected to the drain of the first NMOS transistor MN1 in common, and between the first NMOS transistor MN1 and the third PMOS transistor MP3. A third NMOS transistor MN2 connected between the first NMOS transistor source and the ground terminal Vss and controlled by a drain voltage of the second PMOS transistor MP2; A fourth PMOS transistor MP4 and a fifth PMOS transistor MP5 having a source transistor MN3, a source connected to a drain of the first PMOS transistor MP1, and gates commonly connected to each other; The fourth NMOS transistor MN4, which is controlled by the reference global bit line BLRG_2 signal and whose drain is connected to the drain of the fourth PMOS transistor MP4, and is controlled by the voltage of the output terminal (node 1) and is drained. A fifth NMOS transistor MN5 and a fifth NMOS transistor MN5 connected to a drain of the fifth PMOS transistor MP5 and connected to a source of the fourth NMOS transistor MN4 in common. And the sixth NMOS transistor MN6, which is controlled by the drain voltage of the N MOS transistor MN4 and MN5, connected between the source and the ground terminal Vss of the fourth and fifth NMOS transistors MN4 and MN5. A sixth PMOS transistor MP6 controlled by a reference voltage control signal REFCON and having a source connected to the drain of the first PMOS transistor MP1, and a source having a drain of the sixth PMOS transistor MP6. A seventh NMOS transistor MN7 connected to and controlled by the drain voltage of the third PMOS transistor MP3, and controlled by the drain voltage of the fourth NMOS transistor MN4 and the third PMOS An eighth NMOS transistor MN8 connected between the drain of the transistor MP3 and the drain of the seventh NMOS transistor MN7 and the reference voltage control signal REFCON and controlled by the seventh NMOS transistor The ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 connected in series between the MN7 and the ground terminal Vss, and the drain of the fourth NMOS transistor MN4. The seventh NMOS transistor MP7 is controlled by the phosphorus voltage and the source is branched from the drain of the first PMOS transistor MP1, and the drain is connected to the output terminal (node 1).

18 illustrates in detail the sense amplifier according to the present invention.

First, as shown in FIG. 7, which is implemented as the above-described configuration of FIG. 6 is repeated, the main bit line control unit 67 is configured between two main cell array units 61.

Therefore, the sense amplifier constituting the main bit line control unit 65 is preferably configured to sense data of both the upper main cell array unit 61 and the lower main cell array unit 61.

That is, the upper main cell array unit and the lower main cell array unit are configured to share one bit line control unit.

In the figure, BLGT is a main global bit line connected to an upper cell array unit, and BLGB is a main global bit line connected to a lower cell array unit.

CREF is a reference global bit line connected to the upper reference cell and CREFB is a reference global bit line connected to the lower reference cell.

According to the configuration, a first NMOS transistor MN1 having a source connected to the BLGT and BLGB, a second source connected to the CREF and CREFB and a gate connected to the gate of the first NMOS transistor MN1 in common. NMOS transistor MN2, a third NMOS transistor MN3 that amplifies the BLGT or BLGB signal that enters through the first NMOS transistor MN1, and a CREF that enters through the second NMOS transistor MN2. Alternatively, the fourth NMOS transistor MN4 for amplifying the CREFB signal, a source are respectively connected to the power supply terminal Vcc, and a drain thereof is an output terminal of the first NMOS transistor MN1 and an output terminal of the second NMOS transistor MN2. A first PMOS transistor MP1 and a second PMOS transistor MP2 respectively connected to the drain (the drain of the first PMOS transistor is connected to a gate of the second PMOS transistor, and the second PMOS transistor The drain of the transistor is connected to the gate of the first PMOS transistor.) The output terminal of the first NMOS transistor MN1 and the output terminal of the second NMOS transistor MN2 are equalized by a sense amplifier equalizer signal SAEQ. And a third PMOS transistor MP3.

Here, a fifth NMOS transistor MN5 is formed between the source of the first NMOS transistor MN1 and the BLGT, and a sixth NMOS between the source of the first NMOS transistor MN1 and the BLGB. The transistor MN6 is further configured.

Further, a seventh NMOS transistor MN7 is configured between the source and CREF of the second NMOS transistor MN2, and an eighth NMOS transistor (MN7) is disposed between the source and CREFB of the second NMOS transistor MN2. MN8) is further configured.

The ninth NMOS transistor MN9 for selectively switching the output terminals of the data bus and the sense amplifier and the output terminals of the data bar bus and the sense amplifier are switched by the column selection signal COLSEL. The tenth NMOS transistor MN10 is further configured.

Here, the fifth NMOS transistor MN5 is responsible for switching between the sense amplifier and BLGT, and the sixth NMOS transistor MN6 is responsible for switching between the sense amplifier and BLGB.

The seventh NMOS transistor MN7 is responsible for switching between the sense amplifier and CREF, and the eighth NMOS transistor MN8 is responsible for switching between the sense amplifier and CREFB.

The operation of the first embodiment of the sense amplifier configured as described above is as follows.

The operation description according to the first embodiment of the sense amplifier to be described below corresponds to the case of sensing data stored in the upper main cell.

That is, as illustrated in FIG. 18, the fifth and seventh signals are activated by the activation signal BSEL for activating the fifth NMOS transistor MN5 and the activation signal RSEL for activating the seventh NMOS transistor MN7. When the NMOS transistors MN5 and MN7 are activated, the sixth and eighth NMOS transistors MN6 and MN8 become inactive.

In contrast, when the sixth and eighth NMOS transistors MN6 and MN8 are activated, the fifth and seventh NMOS transistors MN5 and MN7 are inactivated.

The sense amplifier is inactivated by the column select signal COLSEL between the initial amplifiers, so that the external data bus and the internal node of the sense amplifier are disconnected.

At this time, in order to activate the sense amplifier, the node SN3 and the node SN4 are equipotentialized by the sense amplifier equalizer signal SAEQ.

Initially, the first NMOS transistor MN1 and the second NMOS transistor MN2 are in an inactive state. Thereafter, when the nodes SN3 and SN4 become equipotential, data of the main cell is transferred to the upper global bitline BLGT.

The data is transferred to the node SN1 through the fifth NMOS transistor MN5.

The reference voltage is transferred to CREF, and then to the node SN2 through the seventh NMOS transistor MN7.

After the data of the main cell and the reference voltage are sufficiently transmitted to the nodes SN1 and SN2, the reference voltage of the sense amplifier is shifted to the ground voltage.

As a result, the gate voltages of the nodes SN1 and SN2, which are input voltages, are different. Therefore, the currents flowing through the third NMOS transistor MN3 and the fourth NMOS transistor MN4 also differ, and amplification starts in this state. The amplified voltage appears as a voltage difference at nodes SN3 and SN4.

Each voltage induced at the nodes SN3 and SN4 is amplified again by the first PMOS transistor MP1 and the second PMOS transistor MP2.

After sufficiently amplifying the first PMOS transistor MP1 and the second PMOS transistor MP2, the fifth and seventh NMOS transistors MN5 and MN7 are inactivated.

In addition, the first and second NMOS transistors MN1 and MN2 are activated to feed back the amplification voltages of the nodes SN3 and SN4 to SN1 and SN2 to maintain amplification.

At this time, when the feedback loop is completed, the ninth and tenth NMOS transistors MN9 and MN10 are activated to transmit data to an external data bus and a data bus and a sense amplifier.

In addition, the fifth NMOS transistor MN5 is reactivated to transfer the voltage of the node SN1 to the BLGT so as to be fed back to the main cell and restored.

According to the operation of the sense amplifier as described above, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 form the first amplifier 100, and the first PMOS transistor MP1 and the second PMOS transistor. The MOS transistor MP2 forms the second amplifier 103.

Here, reference numeral SEN denotes a sense amplifier activation signal, which is a low active signal, and the SALE signal, which activates the first NMOS transistor MN1 and the second NMOS transistor MN2, is a high active signal.

Fig. 19 shows a second embodiment of the sense amplifier of the present invention.

Compared with the sense amplifier according to the first embodiment, the second amplifier 103 is different from each other.

That is, the second amplifier 103 according to the first embodiment is composed of first and second transistors of PMOS, the drain of the first transistor is connected to the gate of the second transistor, and the drain of the second transistor is It has a configuration connected to the gate of the first transistor.

On the contrary, the second amplifier 103 according to the second embodiment is constituted by a latch circuit.

That is, the first inverter 103a and the second inverter 103b including PMOS and NMOS are formed, and the common gate of the PMOS and NMOS transistors constituting the first inverter 103a is the second. It is connected to the drain of the PMOS transistor which comprises the inverter 103b.

The common gates of the PMOS and NMOS transistors constituting the second inverter 103b are connected to the drains of the PMOS transistors constituting the first inverter 103a.

In addition, in the sense amplifier according to the first embodiment, the NMOS transistor of the first inverter 103a and the NMOS transistor of the second inverter 103b are commonly connected to the ground terminal Vss. It is connected to the enable signal SEN input terminal.

According to the second embodiment of the sense amplifier of the present invention, the second amplifier 103 is composed of two inverters, and the NMOS transistors of the first and second inverters 103a and 103b are sensed. Since it is the same as the configuration of the sense amplifier according to the first embodiment except that it is connected to the amplifier enable signal SEN input terminal, it will be omitted below.

20 is an operation timing diagram of the first embodiment of such a sense amplifier.

21 is an operation timing diagram of the sense amplifier in the read mode, and FIG. 22 is an operation timing diagram of the sense amplifier in the write mode.

As shown in FIG. 20, when the word line W / L and the plate line P / L simultaneously transition to high, the sense amplifier enable signal SEN is activated low.

In addition, when the signal SALE for activating the first and second NMOS transistors MN1 and MN2 shown in FIG. 18 is activated at a high level, the column selection signal transitions to high.

Here, as shown in FIG. 21, the operation of the sense amplifier in the read mode is performed in the section in which the word line W / L and the plate line P / L are both high. When the signal SALE for activating the first and second NMOS transistors MN1 and MN2 transitions to a high level, the column selection signal transitions to a high level sequentially.

Here, the transition operation of the column selection signal is sequentially performed up to the section t10.

Unlike the read mode as described above, in the write mode, as shown in FIG. 22, the transition operation of the column selection signal is t6 during the period in which both the word line (W / L) and the plate line (P / W) are high. It is executed sequentially only within the ~ t7 section.

That is, the column select signals COLSEL1, COLSEL2, COLSEL3, ... COLSELn activate the first and second NMOS transistors MN1 and MN2 shown in FIG. 18 during a period in which both the word line and the plate line are high. When the signal SALE transitions to a high level, the signal SALE transitions sequentially within the t6 to t7 period.

As described above, after the column selection signals are all sequentially shifted, the word line W / L is shifted low, and when the word line W / L transitions again from low to high, the plate line P / L) transitions to low.

23A is an operation timing diagram according to the second embodiment of the sense amplifier of the present invention.

As shown in FIG. 23A, it can be seen that the sense amplifier enable signal SEN is activated at the same time as the word line W / L and the plate line P / L transition high.

That is, the sensing speed can be improved by activating the sense amplifier enable signal SEN faster than the above-described SALE signal.

23B is an operation timing diagram showing a comparison between a REFCON signal used in the second embodiment of the level shifter according to the present invention and a signal used in the sense amplifier.

As shown in FIG. 23B, it can be seen that the control signal REFCON for stabilizing the output stage level of the level shifter goes low while the sense amplifier enable signal SEN is activated low.

That is, before the SALE signal is activated to high, the level change of the output stage of the level shifter is compensated for by the REFCON signal in advance, so that the sense amplifier receiving the reference voltage CREF from the level shifter can perform a stable sensing operation.

24 is a configuration diagram of a cell array of the nonvolatile ferroelectric memory device according to the second embodiment of the present invention.

When the cell array shown in FIG. 24 is compared with FIG. 6, it can be seen that the main bit line control unit or the reference bit line control unit is configured not only on the lower side but also on the upper side.

This is to use the layout more efficiently.

That is, as shown in FIG. 24, the main cell array unit 201, the first main bit line control unit 203a and the second main bit line control formed on the upper side and the lower side of the main cell array unit 201, respectively. The word line driver 205 formed on one side of the main cell array unit 201, the plate line driver 207 formed on the other side of the main cell array unit 201, and the first and second portions 203b. The first reference bit line control unit 209a and the second reference bit line control unit 209b formed on one side of the main bit line control units 203a and 203b are configured.

FIG. 25 illustrates the above configuration in more detail around the main cell array unit.

As shown in FIG. 25, of the main global bit lines configured in the main cell array unit 201, the odd-numbered main global bit lines BLK_n, Blg_n + 2, Blg_n + 4, ... are arranged in the second main side. The bit line controller 203b is connected, and the even-numbered main global bit lines Blg_n + 1, Blg_n + 3, Blg_n + 5, ... are connected to the main bitline controller 203a configured at the upper side.

The reference global bit lines BLRG_1 and BLRG_2 are connected to reference bit line control units 209a and 209b formed at the upper and lower sides of the main cell array unit 201, and the reference bit line control units 209a and 209b are connected to each other. It accepts two reference global bit lines BLRG_1 and BLRG_2.

In addition, as described above, the main cell array unit 201 includes a plurality of sub cell array units 201_1, 201_2,...

Each sub cell array unit includes a main local bit line corresponding to a main global bit line. For example, a plurality of main local bit lines BLL1_n, BLL2_n, ..., corresponding to the first main global bit line BRG_n. BLLn_n) is configured.

Reference local bit lines are also configured in the reference global bit lines BLRG_1 and BLRG_2. For example, a plurality of reference local bit lines BLLR1_1, BLLR2_1, ..., BLLRn_1 correspond to the first reference global bit lines BLRG_1. This is made up.

Here, the main local bit lines formed in each sub cell array unit are connected or disconnected through the corresponding main global bit lines and the switching devices SW11 to SWnn.

Therefore, as the switching elements are selectively turned on / off, the corresponding main local bit line is connected to the main global bit line.

Here, any of the sub-cell arrangements, for example, of the switching elements SW11, SW12, SW13, ... SW1n in the first sub-cell array 201_1 is turned on for the odd-numbered main global. When connected to the bit line Blg_n or BLG_n + 2 or BLG_n + 4, ..., the data of the corresponding main local bitline is not shown in the main sense amplifier (not shown) in the second main bitline control unit 203b. Is delivered to.

If it is connected to an even-numbered main global bit line (BLG_n + 1 or BLG_n + 3 or BLG_n + 5, ...), a reference sense amplifier (not shown) in the first main bit line control unit 203a is shown. The data is passed through.

FIG. 26 is a diagram illustrating the first main bit line control unit and the first reference bit line control unit in more detail.

As shown in FIG. 26, one reference sense amplifier 204a is configured in the first reference bit line control unit 209a, and an even-numbered main global bit line Blg_n is provided in the first main bit line control unit 203a. The main sense amplifiers 206_n + 1,206_n + 3,206_n + 5 ... are configured for each of +1, Blg_n + 3, Blg_n + 5, ....

The odd-numbered main global bit lines Blg_n, BLG_n + 2, BLG_n + 4, ... are connected to a second main bit line controller (not shown), so that the second main bit line controller may be A sense amplifier (not shown) is constructed.

In addition, bit line precharge circuit units 208a_1, 208a_2,... Are arranged between adjacent main global bit lines as in the first embodiment of the present invention shown in FIG. 13.

The bit line precharge circuit 210a is also configured between the last main global bit line among the main global bit lines and the reference global bit line BLRG_2 connected to the reference sense amplifier 204a.

Here, the first reference bit line control unit 207a accommodates two reference global bit lines BLRG_1 and BLRG_2, one of which is connected to the reference sense amplifier 204a and the other of which is a constant voltage. ) Is applied.

In addition, the main sense amplifiers 206_n + 1,206_ in the first main bit line control unit 203a.

n + 3, ...) is commonly applied with a reference voltage CREF provided from the reference sense amplifier 204a.

FIG. 27 illustrates the second main bit line control unit and the second reference bit line control unit in more detail.

As shown in FIG. 27, the configuration of the second main bit line control unit 203b or the second reference bit line control unit 209b may include the first main bit line control unit 203a and the second reference bit. It is the same as the structure of the line control part 209a.

That is, one reference sense amplifier 204b is configured in the second reference bit line controller 209b, and the odd main global bit lines Blg_n, Blg_n + 2, and the second main bit line controller 203b are configured. The main sense amplifiers 206_n and 206_n + 2 are configured for each.

One reference global bit line BLRG_2 is connected to the reference sense amplifier 204b, and a constant voltage is applied to the reference sense amplifier 204b.

Bit line precharge circuits 208b_1, 208b_2,... Are formed between adjacent main global bit lines, and the main sense amplifiers 206_n, 206_n + 2, ... are connected by the reference sense amplifier 204b. The reference voltage CREF provided is commonly applied.

Although not shown in the drawings, the detailed configuration of the sub-cell array unit according to the second embodiment of the present invention is the same as in FIG. 10 described in the first embodiment of the present invention, and will be omitted below.

The structures of the sense amplifier, the level shifter and the bit line precharge level supply unit according to the nonvolatile memory device of the second embodiment of the present invention are the same as those of the first embodiment of the present invention described above.

As described above, the driving circuit of the nonvolatile ferroelectric memory device according to the first and second embodiments of the present invention has the following effects.

Since the main cell is accessed once when the reference cell is accessed once, the reference cell and the main cell are accessed the same time.

Therefore, unlike the prior art in which the reference cell is excessively accessed compared to the main cell, the induced voltage by the reference cell and the induced voltage by the main cell can be kept the same, thereby extending the life of the device.

In addition, since the reference voltage of the stable sense amplifier can be supplied in the sensing operation, the stable sensing operation can be performed.

Claims (17)

A plurality of sub cell arrays, a plurality of main global bit lines and at least one pair of reference global bit lines formed in a direction crossing the sub cell arrays, and each of the main global bit lines and the reference global bit lines. A main cell array unit including correspondingly formed main local bit lines and reference local bit lines, and switching elements configured between the local bit lines and the corresponding global bit lines; A reference bit line control unit formed at a lower portion or an upper portion of the main cell array unit and configured as a reference sense amplifier configured to sense a signal applied through one bit line among the pair of reference global bit lines and output a reference voltage; A main bit line control unit formed at one side of the reference bit line control unit and configured to include a plurality of main sense amplifiers connected to each of the main global bit lines to receive the reference voltage and sense a signal applied through the corresponding global bit line; A word line driver formed on one side of the main cell array unit and outputting a driving signal for cell selection; And And a plate line driver formed on the other side of the main cell array unit to output a drive signal for cell selection together with a drive signal of the word line driver. The method of claim 1, wherein the sub cell array unit Word line pairs in which a plurality of pairs are formed in a direction in which a word line and a plate line form a pair to cross the global bit line; Local bit lines formed corresponding to the global bit lines; And a plurality of unit cells connected to the local bit line based on the local bit line and the word line pair as a basic unit. The method of claim 2, wherein the first unit cells Non-volatile ferroelectric memory device, characterized in that the gate terminal is connected to the word line (W / L), the source terminal is connected to the local bit line, the ferroelectric capacitor (FC1) configured between the drain terminal and the plate line . The method of claim 1, wherein the main bit line control unit And a bit line precharge circuit unit for precharging the adjacent global bit lines to a predetermined level from each other. The nonvolatile ferroelectric memory device of claim 1, wherein a constant voltage is applied to one of the reference global bit lines that is not connected to the reference sense amplifier. The method of claim 1, wherein the reference bit line control unit And a bit line precharge circuit unit formed between the reference global bit line connected to the reference sense amplifier and the last main global bit line of the main global bit lines. The method of claim 6, wherein the bit line precharge circuit unit A plurality of global bitlines, A bit line equalization switch unit configured between each global bit line, And a plurality of bit line precharge switch units for switching precharge signals for precharging the bit lines to the respective global bit lines. 8. The nonvolatile ferroelectric memory device of claim 7, wherein the level of the bit line precharge signal is equal to or slightly higher than the threshold voltage of the NMOS transistor. 8. The PMOS transistor of claim 7, wherein the precharge signal comprises: a first PMOS transistor MP1 whose source is connected to a power supply terminal Vcc and controlled by an activation signal BQLEN for activating a bit line precharge level supply; A second PMOS transistor MP2 and a third PMOS transistor MP3 having a source branched to a drain of the first PMOS transistor MP1 and having a gate connected in common, and the third PMOS transistor ( A first NMOS transistor MN1 controlled by the drain voltage of MP3 and selectively outputting the ground voltage, and connected between the second PMOS transistor MP2 and the first NMOS transistor NM1; A connection between the second NMOS transistor MN2 and the third PMOS transistor MP3 and the first NMOS transistor MN1 controlled by an external reference voltage REF_IN. And a third NMOS transistor MN3 controlled by an output terminal (node 1) voltage, a fourth PMOS transistor MP5 branched to a drain of the first PMOS transistor MP1 and commonly connected to a gate thereof. A fourth NMOS transistor MN4 that is controlled by a fifth PMOS transistor MP5 and gate voltages of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 and selectively outputs a ground voltage. And a fifth NMOS transistor MN5 connected to a drain of the first PMOS transistor MP1 and controlled by the drain voltage of the fifth PMOS transistor MP5, and the fifth NMOS. A sixth NMOS transistor MN6 connected between the gate and the drain of the transistor MN5 and controlled by the drain voltage of the second NMOS transistor MN2, and the third PMOS transistor MP3. A seventh NMOS transistor MN7 and a drain of the second NMOS transistor MN2 that are controlled by a drain voltage and connected between the fourth PMOS transistor MP4 and the fourth NMOS transistor NM4. The eighth NMOS transistor NM8 and the drain voltage of the second NMOS transistor MN2 are controlled by a voltage and connected between the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4. A ninth NMOS transistor NM9 controlled and having a drain connected to the output terminal (node 1), a source and a ground terminal Vss of the ninth NMOS transistor NM9, and a gate and a drain are common. By an activation signal BQLEN branched between the connected tenth transistor NM10 and the power supply terminal Vcc and the first PMOS transistor MP1 to activate the bit line precharge level supply. A seventh PMOS transistor MP7 and an eleventh NMOS transistor MN11 connected in series between a sixth PMOS transistor MP6 to be trolled and a ground terminal Vss of the sixth PMOS transistor MP6. Non-volatile ferroelectric memory device, characterized in that supplied from the bit line precharge level supply configured to include. 10. The nonvolatile ferroelectric memory device of claim 9, wherein the gate of the eleventh NMOS transistor (MN11) is connected to a drain in common and applied to the gate of the second NMOS transistor (MN2). The level shifter of claim 1, wherein the reference sense amplifier comprises a level shifter for shifting a level of a signal applied through a reference global bit line, and a pull-down control unit for pulling down the reference global bit line. Is branched from the drain of the first PMOS transistor MP1 and the first PMOS transistor MP1 controlled by the enable signal LSEN that enables the level shifter and whose source is connected to the power supply terminal Vcc. The first PMOS transistor MP2 and the third PMOS transistor MP3 and the first NMOS transistor connected to the second PMOS transistor MP2 and controlled by the signal BLRG_2 of the reference global bit line. MN1 and a source are commonly connected to the drain of the first NMOS transistor MN1 and the first NMOS transistor MN1 and the third PMOS transistor. The second NMOS transistor MN2 connected between the jitter MP3 and the first and second NMOS transistor sources and the ground terminal Vss and connected to the drain voltage of the second PMOS transistor MP2. A third PMOS transistor MPN and a fifth PMOS transistor, in which a third NMOS transistor MN3 and a source are commonly connected to a drain of the first PMOS transistor MP1, and gates are commonly connected. A fourth NMOS transistor MN4 controlled by the reference global bit line BLRG_2 signal and having a drain connected to the drain of the fourth PMOS transistor MP4 and an output terminal (node 1). A fifth NMOS transistor controlled by a voltage and having a drain connected to the drain of the fifth PMOS transistor MP5 and a source connected in common to the source of the fourth NMOS transistor MN4 And the sixth connected to the source and ground terminal Vss of the fourth and fifth NMOS transistors MN4 and MN5, respectively, controlled by the drain MN5 and the drain voltage of the fifth NMOS transistor MN5. The NMOS transistor MN6 and the sixth PMOS transistor MP6 controlled by an external reference voltage control signal REFCON and whose source is connected to the drain of the first PMOS transistor MP1, and a source. Is connected to the drain of the sixth PMOS transistor MP6 and is controlled by the drain voltage of the third PMOS transistor MP3, and the fourth NMOS transistor MN7 and the fourth NMOS transistor MN4. An eighth NMOS transistor MN8 controlled by the drain voltage of the third PMOS transistor MP3 and connected between the drain of the third PMOS transistor MP3 and the drain of the seventh NMOS transistor MN7, and the reference voltage control. A ninth NMOS transistor MN9 and a tenth NMOS transistor MN10 controlled by an arc REFCON and serially connected between the seventh NMOS transistor MN7 and the ground terminal Vss, and the fourth NMOS transistor MN7 and the fourth NMOS transistor MN10; The seventh NMOS transistor MP7 is controlled by the drain voltage of the NMOS transistor MN4, the source is branched from the drain of the first PMOS transistor MP1, and the drain is connected to the output terminal (node 1). Nonvolatile ferroelectric memory device characterized in that it comprises a. The method of claim 1, wherein the main sense amplifier A first NMOS transistor having a source connected to a global bit line connected to the upper main cell and a global bit line connected to the lower main cell, a reference global bit line connected to the upper reference cell and a lower reference cell A second NMOS transistor having a source connected to a reference global bit line and having a gate commonly connected to a gate of the first NMOS transistor, a third NMOS transistor amplifying a signal voltage received through the first NMOS transistor; A second NMOS transistor configured to amplify the reference voltage input through the second NMOS transistor, and a second amplification circuit configured to secondly amplify the voltage amplified by the third and fourth NMOS transistors. A nonvolatile ferroelectric memory device comprising a portion. 13. The latch circuit of claim 12, wherein the latch circuit comprises a first inverter and a second inverter including PMOS and NMOS, and a common gate of the PMOS and NMOS transistors constituting the first inverter is the second inverter. Is connected to the drain of the PMOS transistor constituting the second inverter, and the common gate of the PMOS and NMOS transistor constituting the second inverter is connected to the drain of the PMOS transistor constituting the first inverter. A nonvolatile ferroelectric memory device. The nonvolatile ferroelectric memory device of claim 13, wherein the NMOS transistor of the first inverter and the drain of the NMOS transistor of the second inverter are connected in common and are connected to a sense amplifier enable signal input terminal. The semiconductor device of claim 12, further comprising a fifth NMOS transistor between a source of the first NMOS transistor and a global bit line connected to the upper main cell, wherein the source of the first NMOS transistor and the main of the lower portion are further configured. A sixth NMOS transistor is further configured between a global bit line connected to a cell, a seventh NMOS transistor is configured between a source of the second NMOS transistor and a reference global bit line connected to the upper reference cell, And an eighth NMOS transistor between the source of the second NMOS transistor and a global bit line connected to the lower main cell. 13. The output terminal of the sense amplifier further comprises a ninth NMOS transistor for selectively switching with the data bus by a column select signal, and a tenth NMOS transistor for selectively switching with the data barbus. A nonvolatile ferroelectric memory device. A plurality of sub cell arrays, a plurality of main global bit lines and at least one pair of reference global bit lines formed in a direction crossing the sub cell arrays, and each of the main global bit lines and the reference global bit lines. A main cell array unit including correspondingly formed main local bit lines and reference local bit lines, and switching elements configured between the local bit lines and the corresponding global bit lines; A first reference bit line control formed on the main cell array unit and configured as a first reference sense amplifier configured to sense a signal applied through one bit line among the pair of reference global bit lines and output a first reference voltage. part; A second reference bit line control unit formed under the main cell array unit and configured of a second reference sense amplifier configured to output a voltage equal to a first reference voltage; A main sense formed on one side of the first reference bit line control unit and connected to an even-numbered main global bit line among the plurality of main global bit lines, and receiving the first reference voltage and sensing a signal applied through the corresponding global bit line; A first main bit line control unit configured of amplifiers; A main sense formed on one side of the second reference bit line control unit and connected to an odd-numbered main global bit line among the plurality of main global bit lines, and receiving a second reference voltage to sense a signal applied through the corresponding global bit line; A second main bit line control unit configured of amplifiers; A word line driver formed on one side of the main cell array unit and outputting a driving signal for cell selection; And a plate line driver formed on the other side of the main cell array unit to output a drive signal for cell selection together with a drive signal output from the word line driver.