KR100289779B1 - Silicide forming method of semiconductor devices - Google Patents
Silicide forming method of semiconductor devices Download PDFInfo
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- KR100289779B1 KR100289779B1 KR1019990016817A KR19990016817A KR100289779B1 KR 100289779 B1 KR100289779 B1 KR 100289779B1 KR 1019990016817 A KR1019990016817 A KR 1019990016817A KR 19990016817 A KR19990016817 A KR 19990016817A KR 100289779 B1 KR100289779 B1 KR 100289779B1
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- silicon wafer
- plasma
- titanium
- thin film
- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title abstract description 19
- 229910021332 silicide Inorganic materials 0.000 title description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims abstract description 18
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 18
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 238000009832 plasma treatment Methods 0.000 claims abstract description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 6
- 238000000992 sputter etching Methods 0.000 claims abstract description 5
- 229910052786 argon Inorganic materials 0.000 claims abstract description 4
- 125000006850 spacer group Chemical group 0.000 claims abstract description 4
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- 238000007872 degassing Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 238000000427 thin-film deposition Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 239000010408 film Substances 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000010406 interfacial reaction Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
PAI에서와 같은 부가적인 장비의 사용과 복잡한 공정없이 간단한 방법에 의한 초집적 반도체 소자에 필요한 균일하고 낮은 저항을 갖는 티타늄 실리사이드를 형성하기 위하여, 실리콘웨이퍼의 소자 영역에 소스/드레인의 접합과 측벽 스페이서를 포함하는 게이트 전극을 형성하고, 실리콘웨이퍼를 습식 세정 및 디개스한다. 그리고, 실리콘웨이퍼 전면을 티타늄 박막 증착을 위한 스퍼터 시스템 내의 스퍼터 식각 챔버에서 아르곤 고주파 플라즈마로, 125W 내지 225W의 전력, 30초 내지 80초의 처리 시간 조건에서 플라즈마 처리한다. 이후, 실리콘웨이퍼 전면에 스퍼터링에 의해 티타늄 박막을 증착하고, 빠른 열처리하여 게이트 전극 상부 및 접합 상부에 균일하고 낮은 저항의 티타늄 실리사이드를 형성한다. 이와 같이 고가의 이온 주입 장비가 필요한 PAI를 하지 않고, 티타늄 박막 증착을 위한 스퍼터 시스템에서 플라즈마 처리를 하므로 공정이 간단하고 경제적이며, 동일 스퍼터 시스템에서 인 시투로 디개스, 플라즈마 처리, 티타늄 박막 증착을 진행할 수 있어 생산성을 향상시킨다.Source / drain junctions and sidewall spacers in the device area of the silicon wafer to form titanium silicides with uniform and low resistances required for super-integrated semiconductor devices by simple methods without the use of additional equipment and complicated processes, such as in PAI. Forming a gate electrode comprising a, and wet cleaning and degass the silicon wafer. The front surface of the silicon wafer is plasma treated with argon high frequency plasma in a sputter etching chamber in a sputter system for depositing a titanium thin film, at a power of 125 W to 225 W and a processing time of 30 to 80 seconds. Subsequently, a titanium thin film is deposited by sputtering on the entire surface of the silicon wafer and rapidly heat-treated to form a uniform and low-resistance titanium silicide on the gate electrode and the junction. As the plasma treatment is performed in the sputtering system for titanium thin film deposition without the need for expensive ion implantation equipment, the process is simple and economical. Proceed to increase productivity.
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 소자의 콘택(contact)에서의 접촉 저항을 감소시키기 위한 실리사이드를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method for forming silicide for reducing contact resistance at a contact of a semiconductor device.
일반적으로 현재 모스 구조의 전계 효과 트랜지스터에서는, 트랜지스터 구동 회로의 콘택(contact) 접촉 저항을 낮추기 위하여 티타늄 실리사이드 형성 기술을 이용하고 있다.In general, the field effect transistor of the MOS structure currently uses a titanium silicide formation technique in order to lower the contact contact resistance of the transistor driving circuit.
그러나 반도체 소자의 미세화에 따른 폴리 배선 선폭(critical dimension, CD)과 콘택부의 면적 감소 특히, 폴리 배선 선폭이 0.25미크론(㎛) 이하의 초집적 반도체 소자에서는 티타늄 실리사이드의 형성이 무척 어렵게 된다. 즉, 티타늄 실리사이드는 높은 저항의 C49 상(phase)과 낮은 저항의 C54 상이 있는 데, 게이트 선폭이 0.25미크론 이하로 좁아질 경우 열처리에 의한 C49 상에서 C54 상으로의 상 전환이 일어날 수 있는 확률이 적어져서 저항이 높은 영역이 많이 존재하게 된다.However, it is very difficult to form titanium silicide in a highly integrated semiconductor device having a poly wiring line width (CD) and a contact area, particularly a poly wiring line width of 0.25 micron or less, due to the miniaturization of semiconductor devices. That is, titanium silicide has a high resistance C49 phase and a low resistance C54 phase, and when the gate line width is narrowed to 0.25 microns or less, there is little possibility that phase transition from C49 to C54 phase by heat treatment occurs. There are many areas with high resistance.
따라서, 이러한 초집적 반도체 소자에서의 티타늄 실리사이드의 문제점을 해결하기 위하여, 최근에는 티타늄 박막의 증착 이전에 폴리 실리콘에 몰리브덴(Mo), 비소(As) 등의 무거운 원소로 이온 주입 공정을 하여 폴리 실리콘 그레인 사이즈를 줄이는 PAI(pre-amorphization implant) 기술이 이용되고 있다.Therefore, in order to solve the problem of titanium silicide in such an integrated semiconductor device, recently, polysilicon is subjected to an ion implantation process using a heavy element such as molybdenum (Mo) or arsenic (As) on polysilicon before deposition of the titanium thin film. Pre-amorphization implant (PAI) technology is used to reduce grain size.
그러면 첨부된 도 1a와 도 1b를 참조하여 종래 PAI를 이용한 반도체 소자의 티타늄 실리사이드를 형성하는 방법을 개략적으로 설명한다.Next, a method of forming titanium silicide of a semiconductor device using a conventional PAI will be described with reference to FIGS. 1A and 1B.
먼저 도 1a에 도시한 바와 같이, 소자 분리 영역(2)이 정의된 실리콘웨이퍼(1)에 게이트 산화막과 폴리 실리콘으로 이루어지며, 그 측벽에 측벽 스페이서(S)를 가지는 0.25미크론 이하의 선폭인 게이트 전극(G)과 게이트 전극(G)의 양측 하부 실리콘웨이퍼(1)에 소스/드레인의 접합(J)을 형성하여 실리콘웨이퍼(1)의 소자 영역에 트랜지스터를 형성한다. 그리고, 실리콘웨이퍼(1)를 이온 주입 장치에 장입한 후, 실리콘웨이퍼(1) 전면(접합 영역의 실리콘과 게이트 영역의 폴리 실리콘 전 영역)에 몰리브덴, 비소 등의 무거운 원소를 이온 주입(PAI)하여 게이트(G) 상부의 폴리 실리콘 및 접합(J)의 실리콘 그레인 사이즈를 줄인다.First, as shown in FIG. 1A, a gate oxide film and polysilicon are formed in a silicon wafer 1 having a device isolation region 2 defined therein, and a gate width of 0.25 microns or less having sidewall spacers S on its sidewalls. A transistor J is formed in the device region of the silicon wafer 1 by forming a junction J of the source / drain in the lower silicon wafer 1 on both sides of the electrode G and the gate electrode G. FIG. After the silicon wafer 1 is charged into the ion implantation apparatus, heavy elements such as molybdenum and arsenic are ion-implanted (PAI) onto the entire surface of the silicon wafer 1 (the entire area of silicon in the junction region and polysilicon in the gate region). Therefore, the size of the polysilicon on the gate G and the silicon grain size of the junction J are reduced.
그 다음 도 1b에 도시한 바와 같이, 실리콘웨이퍼(1) 전면을 불산(HF)으로 습식 세정(wet cleaning)하여 실리콘 및 폴리 실리콘 표면에 존재하는 자연 산화막을 제거하고, 실리콘웨이퍼(1)를 스퍼터(sputter) 시스템 내의 디개스 챔버(degas chamber)에 장입하여 디개스를 실시하여 실리콘 및 폴리 실리콘 표면에서 수분을 포함하는 불순물을 제거한다. 그리고, 스퍼터 시스템 내의 스퍼터 챔버에서 티타늄을 실리콘웨이퍼(1) 전면에 스퍼터링하여 티타늄 박막(3)을 형성한 후, 실리콘웨이퍼(1)를 빠른 열처리(rapid thermal process, RTP) 장비에 장입하여 빠른 열처리함으로써, 접합(J) 영역의 실리콘 및 게이트(G) 영역의 폴리 실리콘과 티타늄 박막(3)의 계면 반응에 의해 균일한 티타늄 실리사이드(4)를 형성한다.Then, as shown in FIG. 1B, wet cleaning of the entire surface of the silicon wafer 1 with hydrofluoric acid (HF) removes the native oxide film present on the silicon and polysilicon surfaces, and the silicon wafer 1 is sputtered. The degas chamber is loaded into a degas chamber in a sputter system to remove impurities including moisture from the silicon and polysilicon surfaces. Then, titanium is sputtered on the front surface of the silicon wafer 1 in the sputter chamber in the sputtering system to form a titanium thin film 3, and then the silicon wafer 1 is charged into a rapid thermal process (RTP) apparatus for rapid heat treatment. As a result, a uniform titanium silicide 4 is formed by the interfacial reaction between the silicon in the junction J region and the polysilicon in the gate G region and the titanium thin film 3.
그 다음, 티타늄 실리사이드 형성에 이용되지 않고 남은 티타늄 금속 박막을 제거한 후, 재차 실리콘웨이퍼를 빠른 열처리한다.Then, after removing the remaining titanium metal thin film not used to form the titanium silicide, the silicon wafer is rapidly heat treated again.
이와 같이 PAI를 이용하면 선폭이 0.25미크론 이하로 좁은 게이트를 갖는 초집적 반도체 소자에서도 균일하고 낮은 저항의 티타늄 실리사이드를 형성할 수 있지만, PAI를 실시하기 위해서는 별도로 고가의 이온 주입 장치가 있어야 하며, 이온 주입시 공정 변수가 많아 최적의 조건을 찾아내는 것이 어려울 뿐만 아니라 이온 주입 공정을 하기 때문에 반도체 소자에 손상(damage)을 줄 수 있다. 또한, 추가적인 이온 주입 장치에서 PAI를 실시하므로 생산성이 크게 떨어지게 된다.In this way, PAI can form uniform and low-resistance titanium silicide even in super-integrated semiconductor devices having a narrow gate width of 0.25 microns or less, but in order to perform PAI, an expensive ion implantation device must be separately provided. Due to the large number of process variables at the time of implantation, it is difficult to find the optimal conditions and damage to the semiconductor device may be caused by the ion implantation process. In addition, since PAI is performed in an additional ion implantation device, the productivity is greatly reduced.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 PAI에서와 같은 부가적인 장비의 사용과 복잡한 공정없이 간단한 방법에 의해 초집적 반도체 소자에 필요한 균일하고 낮은 저항을 갖는 티타늄 실리사이드를 형성하는 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object thereof is a method of forming a titanium silicide having uniform and low resistance required for a super integrated semiconductor device by a simple method without the use of additional equipment and complicated processes such as in PAI. To provide.
도 1a와 도 1b는 종래 PAI을 이용한 반도체 소자의 실리사이드 형성 방법을 개략적으로 도시한 실리콘웨이퍼의 단면도이고,1A and 1B are cross-sectional views of a silicon wafer schematically illustrating a method of forming silicide of a semiconductor device using a conventional PAI,
도 2a 내지 도 2e는 본 발명에 따라 반도체 소자의 실리사이드를 형성하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이고,2A through 2E are cross-sectional views of silicon wafers schematically illustrating a process of forming silicides of semiconductor devices according to the present invention;
도 3은 좁은 N-폴리 실리사이드를 본 발명과 종래 기술에 의해 형성하였을 때의 표면 저항을 비교 측정하여 도시한 것이고,Figure 3 shows a comparative measurement of the surface resistance when the narrow N-poly silicide is formed by the present invention and the prior art,
도 4는 좁은 P-폴리 실리사이드를 본 발명과 종래 기술에 의해 형성하였을 때의 표면 저항을 비교 측정하여 도시한 것이다.4 shows a comparative measurement of the surface resistance when a narrow P-poly silicide is formed by the present invention and the prior art.
상기와 같은 목적을 달성하기 위하여, 본 발명은 티타늄 박막 증착 이전에 PAI 대신 실리콘웨이퍼 전면을 플라즈마 처리하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that the front surface of the silicon wafer instead of PAI plasma treatment before the deposition of titanium thin film.
이때, 플라즈마 처리는 티타늄 박막 증착을 위한 스퍼터 시스템 내의 스퍼터 식각 챔버에서 실시하며, 플라즈마 소스로 아르곤 고주파 플라즈마를 이용한다.At this time, the plasma treatment is performed in the sputter etching chamber in the sputter system for the deposition of titanium thin film, using argon high frequency plasma as a plasma source.
그리고, 플라즈마 처리는 125W 내지 225W의 고주파 플라즈마 전력, 30초 내지 80초의 처리 시간 조건에서 실시하며, 플라즈마 처리시, 챔버 벽에 400KHz의 고주파로 200W의 전력을 추가한다.The plasma treatment is performed at a high frequency plasma power of 125W to 225W, and a processing time of 30 seconds to 80 seconds, and adds 200W of power at a high frequency of 400KHz to the chamber wall during the plasma processing.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따라 반도체 소자의 실리사이드를 형성하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이다.2A through 2E are cross-sectional views of silicon wafers schematically illustrating a process of forming silicides of semiconductor devices according to the present invention.
먼저 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11)에 소자 분리 영역(12)을 정의하고, 실리콘웨이퍼(11)를 열산화하여 정의된 소자 영역에 게이트 산화막을 형성한다. 그리고, 실리콘웨이퍼(11) 전면에 P형 또는 N형 도펀트(dopant)가 도핑된 폴리 실리콘을 증착하고 패터닝(patterning)하여 선폭이 0.25미크론 이하인 게이트 전극(G)을 형성한다. 이후, 게이트 전극(G)을 마스크로 P형 또는 N형 불순물을 이온 주입하고 어닐링(annealing)하여 소스/드레인의 접합(J)을 형성하고, 질화막 등의 절연막을 증착하여 이방성 식각함으로써 게이트 전극(G)의 측벽에 측벽 스페이서(S)를 형성한다. 이때, 소스/드레인 접합(J)은 일반적인 반도체 소자 제조 공정에 따라 LDD(lightly doped drain) 형태로 형성할 수도 있다.First, as shown in FIG. 2A, the device isolation region 12 is defined in the silicon wafer 11, and the gate oxide film is formed in the defined device region by thermally oxidizing the silicon wafer 11. Then, the silicon wafer 11 is deposited on the entire surface of the silicon wafer 11 doped with P-type or N-type dopant and patterned to form a gate electrode G having a line width of 0.25 micron or less. Thereafter, P-type or N-type impurities are ion implanted using the gate electrode G as a mask and annealed to form a junction J of the source / drain, and anisotropic etching is performed by depositing an insulating film such as a nitride film to form the gate electrode ( Side wall spacers S are formed in the side wall of G). In this case, the source / drain junction J may be formed in a lightly doped drain (LDD) form according to a general semiconductor device manufacturing process.
그 다음 도 2b에 도시한 바와 같이, 실리콘웨이퍼(11)를 불산으로 습식 세정하여 실리콘 및 폴리 실리콘 표면에 존재하는 자연 산화막을 제거한다. 이후, 실리콘웨이퍼(11)를 스퍼터 시스템, 바람직하게는 표준 스퍼터 시스템 내의 디개스 챔버에 장입하여 100℃ 정도의 낮은 온도로 디개스하여 자연 산화막의 형성을 억제한다. 그리고, 실리콘웨이퍼(11)를 비아(via) 베리어(barrier) 금속막을 증착하기 전에 작은 비아 홀 내의 불순물을 식각해 내기 위한 챔버로 거의 모든 스퍼터 시스템에 장착되어 있는 스퍼터 식각 챔버에 장입하여 플라즈마 처리를 한다. 이때, 바람직하게는 플라즈마 소스로 아르곤(Ar) 고주파(radio frequency, RF) 플라즈마를 사용하며, 125W 내지 225W 정도의 고주파 전력(power)으로 30초 내지 80초 정도로 플라즈마 처리한다. 또한, 챔버 벽에 400KHz의 고주파로 200W의 전력을 추가한다. 여기서 플라즈마 처리는 음 전압이 가하여지는 전극에 실리콘웨이퍼를 놓고 스퍼터 식각과 같은 방법의 공정을 진행하는 것이다. 그러면, 실리콘웨이퍼(11)에서는 100Å 내지 200Å 정도의 열 산화막이 제거되는 수준의 물질들이 제거되며, 운동량 전달 방식에 의한 스퍼터로 게이트 전극(G) 상부의 폴리 실리콘 및 접합(J) 영역의 실리콘 그레인 사이즈가 줄어든다. 따라서, 종래 PAI를 실시한 것과 동일한 효과를 얻을 수 있다.Then, as shown in FIG. 2B, the silicon wafer 11 is wet-cleaned with hydrofluoric acid to remove the native oxide film present on the silicon and polysilicon surfaces. Thereafter, the silicon wafer 11 is charged into a degas chamber in a sputter system, preferably a standard sputter system, and degassed at a temperature as low as 100 ° C. to suppress the formation of a native oxide film. Then, the silicon wafer 11 is charged into a sputter etching chamber installed in almost all sputter systems as a chamber for etching impurities in the small via holes before the via barrier metal film is deposited. do. At this time, preferably, argon (Ar) radio frequency (RF) plasma is used as the plasma source, and plasma treatment is performed at about 30 seconds to about 80 seconds at a high frequency power of about 125W to 225W. It also adds 200W of power to the chamber wall at a high frequency of 400KHz. In the plasma treatment, a silicon wafer is placed on an electrode to which a negative voltage is applied, and a process such as sputter etching is performed. Then, in the silicon wafer 11, materials having a level at which the thermal oxide film of about 100 kPa to 200 kPa is removed are removed, and polysilicon on the gate electrode G and silicon grains in the junction J region are sputtered by a momentum transfer method. The size is reduced. Therefore, the same effect as that of the conventional PAI can be obtained.
그 다음 도 2c에 도시한 바와 같이, 실리콘웨이퍼(11)를 스퍼터 시스템 내의 스퍼터 챔버에 장입하여, 실리콘웨이퍼(11) 전면에 티타늄을 스퍼터링하여 티타늄 박막(13)을 증착한다. 이때, 바람직하게는 히터 블록(heater block)의 온도를 100℃ 정도로 하여 티타늄 박막(13)을 증착한다.Then, as shown in FIG. 2C, a silicon wafer 11 is charged into the sputter chamber in the sputter system, and titanium is sputtered onto the silicon wafer 11 to deposit the titanium thin film 13. At this time, preferably, the titanium thin film 13 is deposited at a temperature of a heater block of about 100 ° C.
그 다음 도 2d에 도시한 바와 같이, 실리콘웨이퍼(11)를 빠른 열처리 장치에 장입하여, 바람직하게는 750℃의 온도로 30초간 열처리한다. 그러면, 티타늄 박막(13)과 게이트 전극(G) 상부의 폴리 실리콘 및 접합(J) 영역의 실리콘에서의 계면 반응에 의해 티타늄 실리사이드(14)가 형성된다.Then, as shown in FIG. 2D, the silicon wafer 11 is charged into a rapid heat treatment apparatus, and preferably heat treated at a temperature of 750 ° C for 30 seconds. Then, titanium silicide 14 is formed by the interfacial reaction in the titanium thin film 13 and polysilicon on the gate electrode G and in the silicon in the junction J region.
그 다음 도 2e에 도시한 바와 같이, 습식 장비에서 티타늄 실리사이드 형성에 이용되지 않고 남아 있는 실리콘웨이퍼(11) 상부의 티타늄 박막을 제거한 후, 재차 실리콘웨이퍼(11)를 열처리, 바람직하게는 910℃ 정도의 온도로 10초 정도 열처리한다.Next, as shown in FIG. 2E, after removing the titanium thin film on the upper portion of the silicon wafer 11 that is not used to form the titanium silicide in the wet equipment, the silicon wafer 11 is heat-treated again, preferably about 910 ° C. The heat treatment is performed at a temperature of about 10 seconds.
도 3은 좁은 N-폴리 실리사이드를 본 발명과 종래 기술에 의해 형성하였을 때의 표면 저항을 비교 측정하여 도시한 것이고, 도 4는 좁은 P-폴리 실리사이드를 본 발명과 종래 기술에 의해 형성하였을 때의 표면 저항을 비교 측정하여 도시한 것이다.FIG. 3 shows a comparative measurement of surface resistance when a narrow N-poly silicide is formed by the present invention and the prior art, and FIG. 4 shows a narrow P-poly silicide formed by the present invention and the prior art. The surface resistance is compared and measured.
도 3과 도 4에서 세로축은 0.25 미크론 이하의 선폭의 게이트 폴리에서의 폴리 실리사이드(폴리사이드)의 표면 저항(Ω/sq)이고, 가로축은 플라즈마 처리 공정이다. 그리고, 종래 기술은 PAI를 하지 않고 티타늄 실리사이드를 형성하였을 경우의 폴리사이드 표면 저항이다.3 and 4, the vertical axis represents the surface resistance (kPa / sq) of polysilicide (polyside) in the gate poly having a line width of 0.25 microns or less, and the horizontal axis represents a plasma treatment process. In addition, the prior art is polyside surface resistance when titanium silicide is formed without PAI.
도 3과 도 4에서 알 수 있는 바와 같이, PAI나 플라즈마 처리를 하지 않은 종래 기술에서는 티타늄 실리사이드의 표면 저항이 초집적 반도체 소자의 제작이 불가능 할 정도로 높은 표면 저항을 보이고 있지만, 플라즈마 처리를 125W 내지 225W의 고주파 전력에서 30초 내지 80초의 처리 시간으로 진행한 모든 조건에서 초집적 반도체 소자의 제조가 가능한 정도의 표면 저항을 나타냄을 알 수 있다.As can be seen in FIGS. 3 and 4, in the prior art without PAI or plasma treatment, the surface resistance of titanium silicide shows a high surface resistance such that it is impossible to manufacture a super integrated semiconductor device. It can be seen that the surface resistance to the extent that the super integrated semiconductor device can be manufactured under all conditions proceeded with a processing time of 30 seconds to 80 seconds at a high frequency power of 225 W.
이와 같이 본 발명은 초집적 반도체 소자에서의 균일하고 낮은 저항의 티타늄 실리사이드를 형성하기 위하여 고가의 이온 주입 장비가 필요한 PAI를 하지 않고, 티타늄 박막 증착을 위한 스퍼터 시스템에서 플라즈마 처리를 하므로 공정이 간단하고 경제적이며, 이온 주입을 하지 않으므로 반도체 소자의 손상을 방지할 수있을 뿐만 아니라 특히, 동일 스퍼터 시스템에서 인 시투(in-situ)로 디개스, 플라즈마 처리, 티타늄 박막 증착을 진행할 수 있어 생산성이 향상되고, 불순물에 노출되는 시간이 감소하므로 생산 수율을 향상시킬 수 있다.As described above, the present invention is simple because the plasma treatment is performed in the sputtering system for the deposition of titanium thin film without PAI, which requires expensive ion implantation equipment to form uniform and low-resistance titanium silicide in the super integrated semiconductor device. It is economical and prevents damage of semiconductor device because it does not implant ion, and in particular, degas, plasma treatment, and titanium thin film deposition can be performed in-situ in the same sputtering system to improve productivity. As a result, the exposure time to impurities can be reduced, thereby improving production yield.
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| KR101004808B1 (en) * | 2003-08-18 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for forming silicide of semiconductor device |
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| KR101004808B1 (en) * | 2003-08-18 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for forming silicide of semiconductor device |
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