KR100269636B1 - Solid state image pick-up device - Google Patents

Abstract

PURPOSE: A solid state image device is provided to improve the sensitivity of the output voltage by maximizing a depletion layer between a BCCD(buried charge coupled device) and an N+ of a n-type region and a p-well of a p-type region in a floating diffusion(FD) region so as to decrease the junction capacitance of an FD region. CONSTITUTION: A p-well is formed on an n-type substrate(N-SUB). The second p-well(2P-WELL) is formed on the FD region of the substrate(N-SUB), and the first p-well(1P-WELL) is formed the other region of the substrate(N-SUB). A BCCD is formed on the first p-well(1P-WELL) and the second p-well(2P-WELL), an N+ region that is an impurity region of n-type is formed within the BCCD on the second p-well(2P-WELL). A sensing amplifier is connected to the N+ region of the FD region, a reset gate(RG) and a reset drain(RD) are formed on the BCCD of a drain region. The depth of the second p-well(2P-WELL) is shallower than that of the first p-well(1P-WELL).

Description

Solid state imaging device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state image pickup device, and more particularly, to a floating diffusion region (FD) of a signal detection unit.

1 shows a plan view of a general solid state image pickup device.

A solid state image pickup device is an apparatus for generating electrons by light, arranging charge-coupled devices in a directional manner, and detecting signal charges transmitted thereby. In other words, it is a device that transfers charges excited by light through a directional CCD array and then amplifies this signal to obtain a predetermined output signal. As such, the solid-state imaging device, which converts an image signal into an electrical signal, includes a unit cell including a PD (Photo Diode), which is a light receiving area, and a VCCD (Vertical Charge Coupled Device) for receiving signal charges generated and accumulated in the PD. The pixel array unit includes a horizontal array, a horizontal charge coupled device, and a signal detector. The signal charges accumulated in the PD are sequentially transferred to the VCCD and the HCCD and output through the signal detection unit.

The operation of a general solid state image pickup device will be briefly described as follows. When the light focused through the microlens reaches the light receiving unit PD, the charge generated by the photoelectric effect accumulates in the potential well under the PD. This collected charge is transferred to the charge transfer path VCCD by the change of potential caused by the voltage across the transfer gate. The transmitted charges move in sequence through the VCCD and then move along a wider path called HCCD, which eventually collects in the FD area. The charge collected in the FD region is sensed by using the point that the potential of the FD changes up and down according to the amount of charge, and then is discharged to the drain.

FIG. 2 schematically illustrates a peripheral portion of the conventional solid state image pickup device based on the FD region of the signal detection unit.

As shown in a general solid state image pickup device, a charge transfer region "HCCD region", a "FD region" for storing charge to sense the transferred charge, and a "sensing AMP region for detecting the charge stored in the FD region as an output voltage "And a" drain region "for releasing charge in the sensed FD region. The HCCD region, the FD region and the drain region are electrically connected by BCCD which is an n-type impurity region.

In the HCCD region, a first transfer gate G1 and a second transfer gate G2 are alternately arranged for charge transfer, and an output gate OG formed of a first transfer gate forming material is formed at an end thereof. The FD region forms an N + region for the contact in the BCCD, and the N + region is connected to the sensing AMP gate by the second connection line ML2. The sensing AMP shown in the figure shows a two-stage Fowler sensing AMP (two-stage source follower sensing amp) consisting of four transistors. The signal charge is connected to an external connection terminal via four transistors while changing the potential of N + in the FD region and detected as an output signal. In the drain region, a reset gate RG and a reset drain RD, which is an N + region, are formed so that electric charges of the FD region can be emitted to the outside. The reset gate RG is connected to the first connection line ML1 for applying a pulse. The reset drain electrode VRD is connected to the reset drain RD, and an electrode pulse is applied thereon to discharge the charge transferred to the drain region to the outside.

3 is a cross-sectional view taken along the AA ′ cutting line of the solid state image pickup device shown in FIG. 2.

The P well P-WELL is formed on the N-type substrate N-SUB, and the N-type BCCD is formed on the P well P-WELL again. The first transfer gate G1 and the second transfer gate G2 are alternately arranged on the BCCD in the HCCD region, and the output gate OG is formed at the end thereof. In the BCCD of the FD region, there is an N + region formed at a higher concentration than the BCCD in order to collect charges transferred through the HCCD. The sensing AMP is connected to the N + region of the FD region. The reset gate RG is formed on the BCCD of the drain region, and the reset drain RD formed of the N + region is formed in the BCCD.

Referring to FIGS. 2 and 3, the charge detection function of the conventional solid state image pickup device will be described below.

First, signal charges transmitted through the BCCD by the first transfer gate G1 and the second transfer gate G2 are collected in the N + region of the FD region by the voltage applied to the output gate OG. Thereafter, the signal charge in the N + region of the FD region is converted into a voltage by the total capacitance of the FD region.

At this time, the degree of conversion can be calculated from the equation of Q = CV. That is, the magnitude of the voltage changed per one signal charge is determined by the total capacitance of the FD region, and the change of the voltage is transferred to the gate of the sensing AMP and is represented as a result of the final output.

The signal charge in the sensed FD region is transferred to the reset drain RD under the operation of the reset gate RG, and the potential of the FD region is in the original state, which is the potential state before the signal charge passes through the output gate OG. The state is reset.

Thereafter, the above operation of receiving and detecting the next charge signal is repeated.

In the prior art, as shown in the figure, a depletion layer is formed by the junction between BCCD, which is the N-type region of the FD region, and P well, which is the N + and P-type region. This depletion layer becomes the capacitance of the FD region and affects the conversion of signal charges into voltages. However, in the above structure, the depth of the P well does not completely deplete the FD region. Therefore, there is a problem that the capacitive capacitance of the P well and the FD region becomes large, resulting in a limit in improving the sensitivity.

The present invention is intended to form the P well of the FD region to have a smaller depth or a smaller concentration than the P well of other portions so as to maximize the depletion layer between the BCCD and N + regions of the FD region and the P well. That is, the present invention is intended to improve the sensitivity of the output voltage by minimizing the capacitive capacitance of the FD region by maximizing the depletion of BCCD and the N + and P wells of the P-type region.

To this end, the present invention provides a semiconductor device comprising: a first conductive semiconductor substrate, a second conductive first well formed on the semiconductor substrate, a second conductive second well formed on a portion of the semiconductor substrate that is not the first well; A first conductivity type BCCD region formed on the first well and the second well of the semiconductor substrate, a first conductivity type high concentration impurity region formed on the BCCD above the second well, and formed on the BCCD An insulating film, an HCCD transfer gate formed to actively transfer signal charges of the BCCD region on the insulating layer, and an output gate positioned on the insulating layer, between the transfer gate at the end of the HCCD and the high concentration impurity region; And a plurality of gates formed to sense and output the signal charges of the high concentration impurity region, wherein the second conductivity type second well is positioned above the second well. It is characterized in that it is formed to maximize the depletion of the first conductivity type BCCD region and the high concentration impurity region.

1 is a plan view of a solid state imaging device

2 is a schematic diagram of a solid state image pickup device according to the related art.

3 is a cross-sectional view of the solid state image pickup device taken along the AA ′ cutting line of FIG. 2.

4 is a schematic diagram of a solid state image pickup device according to an embodiment of the present invention;

FIG. 5 is a cross-sectional view of the solid state image pickup device taken along the line BB ′ of FIG. 4.

6 is a driving timing for the operation of the solid state image pickup device according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of the potential profile between BB ′ based on the driving timing of FIG. 6; FIG.

4 schematically illustrates a peripheral portion of the solid state image pickup device according to the present invention, centering on the FD region of the signal detection unit.

As shown in a general solid state image pickup device, a charge transfer region "HCCD region", a "FD region" for storing charge to sense the transferred charge, and a "sensing AMP region for detecting the charge stored in the FD region as an output voltage "And a" drain region "for releasing charge in the sensed FD region. The HCCD region, the FD region and the drain region are electrically connected by BCCD which is an N-type impurity region.

In the “HCCD region”, a first transfer gate G1 and a second transfer gate G2 are alternately arranged for charge transfer, and an output gate OG formed of a first transfer gate forming material is formed at an end thereof. The FD region forms an N + region for the contact in the BCCD, and the N + region of the FD region is connected to the gate of the sensing AMP by the connection line ML1.

The portion indicated by reference numeral 40 in the “FD region” refers to the second P-type well, which is a characteristic configuration of the present invention, and will be described in detail below with reference to Fig. 5, which is a cross-sectional view. The two-stage Fowler sensing AMP (2-Stage Source Follower Sensing Amp) is shown, and the signal charge is detected as an output signal connected to an external connection terminal through four transistors while changing the potential of the N + region of the FD region. .

In the “drain region”, a reset gate RG and a reset drain RD formed of the N + region are formed so as to emit signal charges from the N + region of the FD region to the outside. It can be made using silicon, and a contact is made on polysilicon and a metal ML2 for applying an electrode pulse thereon is connected to the reset drain RD, and a reset drain electrode VRD is connected to the electrode. A pulse was applied to allow the charge transferred to the reset drain RD to be discharged to the outside.

FIG. 5 is a cross-sectional view taken along the line BB ′ of the solid state image pickup device shown in FIG. 4.

The P-well is located on the N-substrate (N-SUB), but the second P-well (2P-WELL) is formed at the portion having the FD region thereon, and the first P is formed at the other portion. A mold well 1P-WELL is formed. An N-type BCCD is formed on these P-type wells, and an N + region, which is an N-type impurity region, is formed in BCCD on the second P-type well (2P-WELL). A sensing AMP is connected to the N + region of the FD region, and a reset gate RG and a reset drain RD, which is an N + region, are formed on the BCCD of the drain region.

In this case, the second P-well (2P-WELL) is formed to have a much smaller depth than the first P-well (1P-WELL) (shown in the drawing), or much lower concentration than the first P-well (1P-WELL). As a result, the formation of the depletion layer of the BCCD and N + regions of the FD region and the P-type wells ie, the second P-type WELL of the vicinity thereof is maximized. If necessary, a P-type well that overlaps the third P-type well, that is, the FD region, is formed to form a P-type well having a different concentration or junction depth from the surrounding first P-type well and the second P-type well, thereby facilitating transfer of signal charges to the FD region. It can be done.

The first P type well 1P-WELL and the second P type well 2P-WELL may be formed using a process of blocking only a desired portion by a photomask in a conventional solid state imaging device manufacturing process. That is, in the process of injecting P-type impurities into the semiconductor substrate in order to form the P-type well, instead of implanting the entire surface of the semiconductor substrate, the portion to form the second P-type well (2P-WELL) is blocked with a photosensitive film, and then P After implanting the type impurity to form the first P-well (1P-WELL), the photoresist film is removed, and then the P-type impurity is implanted to form the second P-well (2P-WELL). At this time, in the process of injecting the P-type impurities for forming the second P-type well (2P-WELL), the second P-type well (2P-WELL) is the first P-type well (adjustment) by appropriately adjusting the injection energy and the injection concentration. 1P-WELL) to form a smaller junction depth or to form a smaller concentration of impurities.

Hereinafter, the signal charge detection function of the solid state image pickup device according to the present invention will be described with reference to FIGS. 4 and 5 showing the structure of the solid state image pickup device, and FIG. As follows.

First, when t = t1, the pulse shapes of (Hφ1, Hφ2, φRG) become (H, L, L), and the potential profile at each position can be represented by the solid line in FIG. Signal charge transmitted through the HCCD is transmitted to the end of the HCCD.

Then, when t = t2, the pulse shape of (Hφ1, Hφ2, φRG) becomes (L, H, H) so that the potential profile at each position can be represented by the dotted line in FIG. As the signal charge at the end of the HCCD becomes higher than the output gate OG, the signal charge at the end of the HCCD is transferred to the N + region of the FD region. At this time, the pulse of the output gate is applied to LOW to facilitate the transfer of charges.

As described above, when Hφ1 is LOW, when the signal charge is transferred to the FD region through the output gate, the capacitance is converted to the voltage by the capacitance of the FD region. The degree of conversion can be calculated from the relationship of Q = CV. That is, the magnitude of the voltage converted per one signal charge is determined by the total capacitance of the FD region. At this time, the depletion of the P-type well is maximized by a bias applied to the N-type substrate and the N + region of the FD region by the characteristic P-type well structure of the present invention. That is, formation of a depletion layer between BCCD, which is an N-type region, and a second P-type well, which is an N-type region and a P-type region, 2P-WELL in the FD region is maximized. Therefore, the capacitance of the FD is minimized, so that the voltage conversion rate of the electrons is large, and eventually the sensitivity is increased. This change in voltage is propagated toward the gate of the sensing AMP, resulting in the final output.

At this time, when the second P-type well 2P-WELL is formed to extend toward the output gate OG, the potential of the channel at the end of the HCCD may be increased. Therefore, the effect of increasing the Fringing Field, which causes the signal charge of HCCD to flow into the FD region, can be obtained. Therefore, the capacitance of the FD region can be arbitrarily designed by freely setting the second P-type well.

Next, when t = t3, the pulse shape of (Hφ1, Hφ2, φRG) becomes (H, L, H) so that the profile at each position can be represented by the solid line in FIG. 6 except for the reset gate portion. have. At this time, the potential of the reset gate RG is lowered as indicated by the first stage solid line, and the signal charge of the FD region where sensing is completed is sent to the reset drain RD under the operation of the reset gate, and emitted to the outside. The potential of the FD region is reset to its original state, which is the potential state before the signal charge is passed through the output gate OG.

Thereafter, the above operation of receiving and detecting the next charge signal is repeated.

The present invention can maximize the depletion of the FD region and the P-type well by adjusting the concentration or depth of the second P-type well, which can significantly reduce the junction capacitance in the FD region. Therefore, the sensitivity in the sensing Amp can be greatly increased. In addition, the capacitance of the FD region can be arbitrarily designed by freely setting the second P-type well. In addition, when the second P-type well is formed to extend toward the output gate, it has the effect of increasing the potential of the channel at the end of the HCCD, thereby facilitating transmission of the signal charge to the FD region. ,

Claims (4)

A first conductivity type semiconductor substrate, a second conductivity type first well formed on the semiconductor substrate, a second conductivity type second well formed on a portion of the semiconductor substrate other than the first well, and the semiconductor substrate. A first conductive type BCCD region formed on the first well and a second well, a first conductive type high concentration impurity region formed on the BCCD above the second well, an insulating film formed on the BCCD, and the insulating film An HCCD transfer gate formed to actively transfer signal charges of the BCCD region on the substrate; an output gate positioned between the transfer gate at the end of the HCCD and the high concentration impurity region; A solid state image pickup device comprising a plurality of gates configured to sense and output a signal charge of an area, And the second conductivity type second well is formed to maximize depletion between the first conductivity type BCCD region and the high concentration impurity region located above the second well. The method according to claim 1, And the second well has a smaller junction depth than the first well. The method according to claim 1, And said second well has a smaller conductivity type concentration than said first well. The method according to claim 1, And the second well is formed to extend to the output gate region.