KR100256246B1 - Method of forming gate electrode in semiconductor device - Google Patents
Method of forming gate electrode in semiconductor device Download PDFInfo
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- KR100256246B1 KR100256246B1 KR1019930030830A KR930030830A KR100256246B1 KR 100256246 B1 KR100256246 B1 KR 100256246B1 KR 1019930030830 A KR1019930030830 A KR 1019930030830A KR 930030830 A KR930030830 A KR 930030830A KR 100256246 B1 KR100256246 B1 KR 100256246B1
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- South Korea
- Prior art keywords
- silicon layer
- layer
- gate oxide
- film
- gate electrode
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- -1 oxygen ion Chemical class 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910018557 Si O Inorganic materials 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000010408 film Substances 0.000 description 25
- 229920005591 polysilicon Polymers 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
제1a도 내지 제1d도는 본 발명에 따른 게이트 전극 형성 공정도.1a to 1d is a process diagram of the gate electrode formation according to the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
1 : 반도체 기판 2 : 게이트 산화막1 semiconductor substrate 2 gate oxide film
3 : 비정질실리콘막 3' : 다결정 실리콘막3: amorphous silicon film 3 ': polycrystalline silicon film
4 : 이온주입 5 : 실리사이드막4 ion implantation 5 silicide film
본 발명은 반도체 제조공정중 게이트 전극 형성 방법에 관한것으로, 특히 실리사이드 구조를 갖는 반도체 소자의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode during a semiconductor manufacturing process, and more particularly to a method of forming a gate electrode of a semiconductor device having a silicide structure.
종래에는 일반적으로, 실리사이드 구조의 게이트 전극을 형성할때 게이트 산화막이 형성된 반도체기판 상에 비정질실리콘막을 저압화학증착(LPCVP)방법으로 증착하고, PoCl3반응소오스(Source)를 이용하여 도핑(Doping)을 실시한 후(이때 비정질실리콘은 다결정실리몰으로 됨) 박막을 화학기상증착(CVD)방법으로 증착한 상태에서 웨이퍼를 고온에서 열처리 하였다.Conventionally, when forming a gate electrode having a silicide structure, an amorphous silicon film is deposited on a semiconductor substrate on which a gate oxide film is formed by low pressure chemical vapor deposition (LPCVP), and doped using a PoCl 3 reaction source. After performing the process (at this time, the amorphous silicon becomes polycrystalline silicon), the wafer was heat-treated at high temperature in a state in which the thin film was deposited by chemical vapor deposition (CVD).
이때, 텅스텐 실리사이드 증착시 사용되는 반응 가스에서 불소(F)성분이 함유되어 있는데 열처리 공정중, 이 불소가 하부층인 폴리실리콘막의 그레인 바운더리(Grain Boundary)를 따라 빠르게 확산하여 게이트 산화막쪽으로 침투하게 된다.At this time, the fluorine (F) component is contained in the reaction gas used for the deposition of tungsten silicide. During the heat treatment process, the fluorine diffuses rapidly along the grain boundary of the polysilicon layer, which is the lower layer, and penetrates toward the gate oxide layer.
따라서 확산된 불소에 의해 산화막의 두께가 증가하고 게이트 산화막의 특성이 떨어지므로써 소자의 신뢰성을 떨어뜨리는 문제점이 있었다.Therefore, the thickness of the oxide film is increased by the diffused fluorine and the characteristics of the gate oxide film are deteriorated, thereby reducing the reliability of the device.
상기 문제점을 해결하기 위하여 안출된 본 발명은 비정질 상태로 증착된 실리콘막 상에 산소이온을 이온주입한 이후 실리사이드막을 증착하는 반도체 소자의 게이트 전극 형성 방법을 제공함을 그 목적으로 한다.An object of the present invention is to provide a method of forming a gate electrode of a semiconductor device for depositing a silicide film after ion implantation of oxygen ions on a silicon film deposited in an amorphous state.
상기 목적을 달성하기 위하여 본 발명은 실리사이드 구조를 갖는 반도체 소자의 게이트 전극 형성 방법에 있어서, 반도체 기판상에 게이트 산화막을 형성하는 단계, 상기 게이트 산화막상에 비정질실리콘막을 증착하는 단계, 상기 비정질 실리콘막에 산소이온을 주입하는 단계, 상기 비정질 실리콘막에 불순물 도핑(Doping) 및 열처리 하여 다결정 실리콘막을 형성하는 단계, 상기 다결정실리콘막상에 실리사이드막을 형성하는 단계, 마스크 및 식각 공정을 통해 상기 실리사이드막, 다결정 실리콘막, 게이트 산화막의 소정부위를 차례로 식각하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a gate electrode of a semiconductor device having a silicide structure, the method comprising: forming a gate oxide film on a semiconductor substrate, depositing an amorphous silicon film on the gate oxide film, and the amorphous silicon film Implanting oxygen ions into the polysilicon layer, forming a polycrystalline silicon layer by doping and thermally treating the amorphous silicon layer, forming a silicide layer on the polysilicon layer, and performing a mask and etching process. And etching a predetermined portion of the silicon film and the gate oxide film in sequence.
이하, 첨부된 도면 제1a도 내지 제1d도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings 1A to 1D.
먼저, 제1a도는 반도체기판(1)상에 게이트산화막(2)을 형성한 후, 550℃ 이하의 온도에서 비정질실리콘막(3)을 증착한 다음에 산소이온을 게이트 산화막(2)에 손상을 주지 않을 정도로 이온주입(4)하는 상태의 단면도이다.First, in FIG. 1A, after the gate oxide film 2 is formed on the semiconductor substrate 1, the amorphous silicon film 3 is deposited at a temperature of 550 ° C. or lower, and then oxygen ions are damaged to the gate oxide film 2. It is sectional drawing of the state which ion-implanted 4 so that it may not give.
그리고, 제1b도는 PoCl3도핑 공정으로 상기 비정질 실리콘막(3)을 다결정 실리콘막(3')으로 형성한 상태로서, 이때 다결정실리콘막(3') 내부에는 그레인 바운더리가 생기고, 이곳으로 이온주입되었던 산소이온들이 모이게 되면서 Si과 결합하여 Si-O 결합을 형성되게 된다. 이어서, 제1c도와 같이 텅스텐 실리사이드 박막(5)을 증착하는데, 이때 상기 다결정실리콘막(3')내에 형성된 Si-O 결합이 반응가스에 포함되어 있는 불소가 하부층인 게이트 산화막(2) 내로 확산하는 것을 방지하게 된다.1B is a state in which the amorphous silicon film 3 is formed of a polycrystalline silicon film 3 'by a PoCl 3 doping process, in which grain boundaries are formed inside the polysilicon film 3', and ion implantation is performed therein. As the oxygen ions are collected, they combine with Si to form a Si-O bond. Subsequently, a tungsten silicide thin film 5 is deposited as shown in FIG. Will be prevented.
계속되는 이후의 일반적인 마스크 및 식각공정으로 제1d도와 같은 실리사이드 구조를 갖는 게이트 전극 패턴을 형성한다.Subsequent general mask and etching processes are performed to form a gate electrode pattern having a silicide structure as shown in FIG. 1d.
상기 설명과 같이 이루어지는 본 발명은 소자의 접촉저항을 향상시키고자 하는 목적으로 텅스텐 실리사이드 박막을 형성할시 게이트 산화막 내부로의 불순물이 확산되는 것을 방지하여 산화막의 특성을 향상시켜 신뢰성 향상 및 수율증가를 가져오는 효과가 있다.The present invention made as described above improves the characteristics of the oxide film by improving the characteristics of the oxide film by preventing impurities from diffusing into the gate oxide film when forming the tungsten silicide thin film for the purpose of improving the contact resistance of the device. It has an effect.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930030830A KR100256246B1 (en) | 1993-12-29 | 1993-12-29 | Method of forming gate electrode in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930030830A KR100256246B1 (en) | 1993-12-29 | 1993-12-29 | Method of forming gate electrode in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021113A KR950021113A (en) | 1995-07-26 |
| KR100256246B1 true KR100256246B1 (en) | 2000-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930030830A KR100256246B1 (en) | 1993-12-29 | 1993-12-29 | Method of forming gate electrode in semiconductor device |
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| Country | Link |
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| KR (1) | KR100256246B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100362190B1 (en) * | 1995-12-16 | 2003-03-06 | 주식회사 하이닉스반도체 | Method for forming polycide electrode |
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- 1993-12-29 KR KR1019930030830A patent/KR100256246B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR950021113A (en) | 1995-07-26 |
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