KR100238239B1 - Boosted voltage generator of semicondutor memory device - Google Patents

Abstract

A boosted voltage generator for a semiconductor memory device having a plurality of bank structures is disclosed. The boosted voltage generator of the semiconductor memory device has one boosted voltage detector and one pulse generator shared by a plurality of banks. In addition, a detection enable signal generator, a signal sampler, a pulse generator, a plurality of bank selectors, and a plurality of active kickers are included. The detection enable signal generator generates a detection enable signal that is activated when an access to any one of the plurality of bank memories is performed, and applies the detection enable signal to the boost detector. The signal sampler is triggered when the detection signal output from the boost detector is activated, and outputs a pulse generator control signal that is triggered and activated by both the pulse signal which is active and the output of the pulse generator and the detection enable signal are inactive. Each of the bank selectors generates an active kicker enable pulse AKE0, AKE1, AKE2, and AKE3 that is activated when the pulse signal is active and access to the corresponding bank is performed, and applies the active kicker to the corresponding active kicker. The boosted voltage generator of the semiconductor memory device has the advantage of low power consumption, reduced layout area, and stable operation.

Description

Step-up Voltage Generators for Semiconductor Memory Devices

The present invention relates to a boosted voltage generator of a semiconductor memory device, and more particularly to a boosted voltage generator (VPP generator) that can be employed in a synchronous dynamic random access memory having a plurality of banks.

The boosted voltage generator generates a voltage having a level higher than a normal power supply voltage, which is adopted for the weakening of the signal due to the high load generated as the chip size of the semiconductor memory device increases and the shortening of the access time. That is, when the chip size of the semiconductor device increases, there is a problem that the signal is lost due to the voltage drop (IR drop) caused by the resistance component before the signal reaches the necessary place in the chip. In particular, as the load of the word line increases, the time required for the word line enable increases. In addition, since the word line is driven and thus the bit line and the inverted bit line are charged sharing according to the data stored in the memory cell, the time required for the level transition to occur accordingly increases. Accordingly, a boosted voltage is required to shorten the time required for driving the word line, and the boosted voltage generator generates such a boosted voltage.

On the other hand, in the conventional asynchronous DRAM, since the memory operation is composed of a single bank, the internal boost voltage generator is also configured in a single manner, and the control method thereof is simple. More specifically, the boosted voltage detector included in the boosted voltage generator is configured to be activated based on the row address strobe signal RAS. In contrast, in a synchronous DRAM having a multi-bank structure, by activating a plurality of banks in an interleaved manner and inputting / outputting data, the access time of the memory is shortened and high bandwidth is realized. In such a multi-bank structure, as described above, the word line must be driven by a boosted voltage VPP that is higher than or equal to the threshold voltage of the cell access transistor than the normal internal power supply voltage internal VCC.

1 is a block diagram of a boost voltage generator in a synchronous DRAM having a multiple bank structure according to the prior art. Referring to FIG. 1, the boosted voltage generator includes a plurality of unit boosted voltage generators 110, 120, 130, and 140. The unit boosted voltage generators 110, 120, 130, and 140 may respectively include boosted voltage detectors 112, 122, 132, and 142, pulse generators 114, 124, 134, and 144, and active kickers 116, 126, and 136, respectively. 146). Reference numerals PR0, PR1, PR2, PR3 denote bank active master signals, and VPP0, VPP1, VPP2, VPP3 denote boost voltages.

In the unit boosted voltage generator 110, the boosted voltage detector 112 detects whether the level of the boosted voltage VPP0 is equal to or less than a predetermined level when the bank active master signal PR0 is active. If the boosted voltage VPP0 is equal to or lower than the target voltage level, the boosted voltage detector 112 outputs a detection signal that is activated at the "high" level. The pulse generator 114 outputs a pulse signal which is triggered when the detection signal is activated and becomes active for a certain period of time. In other words, when the detection signal is " high " level active, the pulse generator outputs a pulse signal that is triggered at the rising edge of the detection signal and is active for a certain period of time. The active kicker 116 boosts the level of the boosted voltage VPP0 during the period in which the pulse signal output from the pulse generator 114 is active. The remaining unit boosted voltage generators operate in the same manner.

However, the boosted voltage generator of the conventional semiconductor memory device has a disadvantage in that the required lay-out area is large because the boosted voltage detector and the pulse generators must be provided for each bank. That is, it becomes a barrier to chip size reduction. In addition, since the boosted voltage detectors must be provided as many as the number of banks, current consumption is high, and there is a problem in that the probability of malfunction of the circuit due to process variation or a change in detection level according to a position disposed in the circuit board is increased.

Accordingly, it is an object of the present invention to provide a boosted voltage generator of a semiconductor memory device which can operate efficiently in a synchronous dynamic semiconductor memory device having a plurality of bank structures.

Another object of the present invention is to provide a boosted voltage generator of a semiconductor memory device capable of reducing chip size and realizing low power operation.

1 illustrates a boosted voltage generator of a semiconductor memory device having a plurality of bank structures according to the related art.

2 illustrates a boosted voltage generator of a semiconductor memory device having a plurality of bank structures according to an exemplary embodiment of the present invention.

3 illustrates a boosted voltage generator of a semiconductor memory device having a plurality of bank structures according to another exemplary embodiment of the present invention.

4 is a detailed circuit diagram of the detection enable signal generator shown in FIGS. 2 and 3.

FIG. 5 is a detailed circuit diagram of the signal sampler shown in FIG. 3.

FIG. 6 is a detailed circuit diagram of the bank selector shown in FIGS. 2 and 3.

FIG. 7 is a timing diagram for describing an operation of a boosted voltage generator of the semiconductor memory device illustrated in FIGS. 3 to 6.

<Explanation of symbols for main parts of the drawings>

200 ... detection enable signal generator 112 ... step-up voltage detector

300 ... Signal Sampler 114 ... Pulse Generator

400, 410.420, 430 ... bank selector

116, 126, 136, 146 ... active kicker

DETE ... detection enable signal DET ... detection signal

DETP ... pulse generator control signal AKE ... pulse signal

AKE0, AKE1, AKE2, AKE3 ... Active kicker enable pulse

VPPE0, VPPE1, VPPE2, VPPE3 ... bank access signals

VPP0, VPP1, VPP2, VPP3 ... step-up voltage

In order to achieve the above objects, a boosted voltage generator of a semiconductor memory device according to the present invention includes a plurality of bank memories, in which an access to at least one of the plurality of bank memories is performed. A detection enable signal generator for generating an active detection enable signal; A boosted voltage detector configured to generate a detection signal DET that is activated when a level of the boost power supply is lower than a predetermined level when the detection enable signal DETE is active; A pulse generator triggering the rising edge of the detection signal DET to generate a pulse signal AKE that is activated for a predetermined period of time; A plurality of bank selectors for generating active kicker enable pulses (AKE0, AKE1, AKE2, and AKE3) that are activated when the pulse signal (AKE) is active and access to the corresponding bank is performed; And a plurality of active kickers for boosting a boosted voltage corresponding to a period during which the corresponding active kicker enable pulse is active. A signal sampler that is triggered when the detection signal DET is activated and is active and generates a pulse generator control signal DETP that is triggered when both the pulse signal AKE and the detection enable signal DETE are nonactive is generated. Also provided.

According to an embodiment, each of the detection enable signal generators may activate the bank access signals VPPE0, VPPE1, VPPE2, and VPPE3 that are activated from the time point at which access to the corresponding bank is started until bit line sense amplification of the corresponding bank is performed. A plurality of bank access signal generators; A first logic unit 240 for outputting an active signal when any one of the plurality of bank active master signals PR0, PR1, PR2, and PR3 is active; A second logic unit 250 for ORing the plurality of bank access signals; And a third logic unit 260 for generating a detection enable signal DETE that is activated when the output of the first logic unit is non-active or the output of the second logic unit is active. The plurality of bank access signal generators may include a plurality of inverters for delaying and inverting the corresponding bit line sense amplifier driving signals PPS0, PPS1, PPS2, and PPS3, respectively; And an AND gate for ANDing the final output of the inverters and the corresponding bank active master signals PR0, PR1, PR2, and PR3.

The signal sampler includes a latch unit 310; A first logic gate 320 for outputting an active signal when any one of the detection enable signal DETE and the pulse signal AKE is active; And a second logic gate 330 for generating the pulse generator control signal DETP that is activated when the output of the latch unit and the output of the first logic gate are both active, and the latch unit controls the pulse generator. If the signal DETP is active, the power supply voltage is output. Otherwise, the detection signal DET is output. The second logic gate 330 may include a NAND gate 332 for inputting an output of the latch unit 310 and an output of the first logic gate 320; And a first inverter 334 for inverting the output of the NAND gate, and the latch unit 310 includes a second inverter 312 for inverting the output of the NAND gate 322; A transmission gate 314 controlled by an output of the NAND gate and an output of the second inverter, for passing the detection signal DET when the output of the NAND gate is at a "high" level; And a PMOS transistor 316 having its own drain-source path connected between a power supply voltage VCC and an output of the transfer gate and its own gate connected to the output of the NAND gate 332. do.

The plurality of bank selectors may include a first inverter 402 for inverting corresponding bank active master signals, respectively; A first NAND gate for logically inverting a signal different from the pulse signal AKE; A second NAND gate logically inverting an output of the first inverter and an output of the first NAND gate and applying the output as another signal of the first NAND gate; And a second inverter 408 which inverts the output of the first NAND gate to generate corresponding active kicker enable pulses AKE0, AKE1, AKE2, and AKE3.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a boosted voltage generator of a semiconductor memory device having a plurality of bank structures according to an exemplary embodiment of the present invention. Referring to FIG. 2, the boosted voltage generator of the semiconductor memory device may include a detection enable signal generator 200, a boosted voltage detector 112, a pulse generator 114, and a plurality of bank selectors 400, 410, 420, and 430. ) And a plurality of active kickers 116, 126, 136, 146. The detection enable signal generator 200 generates a detection enable signal DETE that is activated when access to at least one of the plurality of bank memories is performed. The boosted voltage detector 112 generates a detection signal DET that is activated when the detection enable signal DETE is active and the level of the boosted voltage is below a predetermined level. The pulse generator 114 is triggered when the detection signal DET is activated to generate a pulse signal AKE that is activated for a predetermined period of time. Here, the period during which the pulse signal is active may be determined based on the amount of charge consumed in the circuit in which the boosted voltage to be driven is used. That is, the period during which the pulse signal AKE is active is determined corresponding to the period during which the boosting operation is performed. Each of the plurality of bank selectors 400, 410, 420, and 430 has an active kicker enable pulse AKE0, AKE1, AKE2, and AKE3 that are activated when the pulse signal AKE is active and access to the corresponding bank is performed. Will occur). Each of the plurality of active kickers 116, 126, 136, and 146 boosts a boosted voltage corresponding to a period in which the corresponding active kicker enable pulses AKE0, AKE1, AKE2, and AKE3 are active.

3 is a diagram illustrating a boosted voltage generator of a semiconductor memory device having a multi-bank structure according to another embodiment of the present invention. Compared with the boosted voltage generator of the semiconductor memory device shown in FIG. 2, the signal sampler 300 is further added. Equipped.

In FIG. 3, the signal sampler 300 is triggered when the detection signal DET is activated, is activated, and is triggered by the non-active pulse signal AKE, which is the output of the pulse generator 114, and is inactive. (DETP) occurs. In addition, the pulse generator 114 is triggered when the pulse generator control signal DETP is activated to generate a pulse signal AKE that is activated for a predetermined period of time.

4 is a detailed circuit diagram of the detection enable signal generator shown in FIGS. 2 and 3. In FIG. 4, the detection enable signal generator 200 includes a plurality of bank access signal generators 201, 211, 221, and 231, a logic unit 240, a logic sum gate 250, and a logic unit 260. do. The plurality of bank access signal generators 201, 211, 221, and 231 include a plurality of inverters and an AND gate. In the bank access signal generator 201, the bit line sense amplifier driving signal PPS0 is delayed and inverted by the inverters 202, 204, and 206. The AND gate 208 logically multiplies the output of the inverter 206 by the bank active master signal PR0 to output the bank access signal VPPE0. Similarly, in the bank access signal generator 211, the bit line sense amplifier driving signal PPS1 is delayed and inverted by the inverters 212, 214, and 216, and the AND gate 218 of the inverter 216 is inverted. The bank access signal VPPE1 is output by ANDing the output and the bank active master signal PR1. In the bank access signal generator 221, the bit line sense amplifier driving signal PPS2 is delayed and inverted by the inverters 222, 224, and 226. The AND gate 228 logically multiplies the output of the inverter 226 by the bank active master signal PR2 to output the bank access signal VPPE2. In the bank access signal generator 231, the bit line sense amplifier driving signal PPS3 is delayed and inverted by the inverters 232, 234, and 236, and the AND gate 238 is connected to the output of the inverter 236. The bank active master signal PR3 is ANDed to output the bank access signal VPPE3. Accordingly, the bank access signals VPPE0, VPPE1, VPPE2, and VPPE3 that are outputs of the bank access signal generators 201, 211, 221, and 231 may be represented by Equation 1 below.

[Equation 1]

In Equation 1, "D (signal name)" indicates that the signal is delayed, "overline" indicates inversion, and "," indicates logical product.

Here, the bank active master signals PR0, PR1, PR2, and PR3 are each at the "high" level when the corresponding bank is activated, and are non-active at the "low" level when the corresponding bank is precharged. . The bit line sense amplifier driving signals PPS0, PPS1, PPS2, and PPS3 are activated to a “high” level when the bit line sense amplifier operation is performed in a corresponding bank. Accordingly, the bank access signals VPPE0, VPPE1, VPPE2, and VPPE3 are each active until a slight time delay occurs when a corresponding bank is active and a sense amplifier operation on the corresponding bit line is performed.

The OR gate 250 outputs a signal that is activated when any one of the bank access signals VPPE0, VPPE1, VPPE2, and VPPE3 is active at the “high” level. Therefore, the output of the OR gate 250 may be expressed as Equation 2 below.

[Equation 2]

The logic unit 240 includes a logic sum gate 242 and an inverter 244, and the output of the inverter 244 may be represented by Equation 3 below.

[Equation 3]

Therefore, the output of the logic unit 240 becomes a "high" level when low active is performed on any one of the plurality of banks.

The logic unit 260 includes an inverter 262 and an OR gate 264. The inverter 262 inverts the output of the logic unit 240 and the OR gate 264 is a "high" level when either the output of the OR gate 250 and the output of the inverter 262 are "HIGH" levels. The detection enable signal DETE is outputted. Accordingly, the detection enable signal DETE may be represented by Equation 4 below.

[Equation 4]

In Equation 4, "N1" represents the output of the OR gate 250, "∧" represents an AND, and "∨" represents an OR. Accordingly, the detection enable signal DETE is activated to a "high" level at a time slightly delayed from when one bank is activated and the bit line sense amplifier operation starts, and a precharge operation to the bank is performed or another bank is performed. If is active, it is inactive to the "low" level. Here, the time point when the detection enable signal DETE becomes the "high" level is essentially the time point at which the word line needs to be boosted. In the embodiment shown in FIG. 4, the bit line sense amplifier driving signals PPS0, PPS1, PPS2, and PPS3 are used as inputs. Thus, the detection enable signal DETE is activated after a slight delay after the bit line sense amplifier operation is started. This is because when the bit line sense amplifier operation is performed after charge sharing after the word line is activated, there is a need for boosting the word line. However, unlike in FIG. 4, it is also possible to apply signals other than the bit line sense amplifier driving signals PPS0, PPS1, PPS2, and PPS3 as inputs. Here, the signals that can be used as inputs instead of the bit line sense amplifier driving signals PPS0, PPS1, PPS2, and PPS3 should be signals containing information on when it is necessary to boost the word line.

FIG. 5 is a detailed circuit diagram of the signal sampler illustrated in FIG. 3, and the signal sampler includes a latch unit 310, a logic gate gate 320, and a logic unit 330. The logic unit 330 is composed of a NAND gate 332 and an inverter 334.

The OR gate 320 outputs a signal having a "high" level when one of the detection enable signal DETE and the pulse signal AKE is "high" level active. The logic unit 330 outputs a pulse generator control signal DETP that is activated at the "high" level when both the signal of the node N2 and the output of the OR gate 320 are at the "high" level.

The latch unit 310 is composed of an inverter 312, a transfer gate 314, and a PMOS transistor 316, and inputs a detection signal DET. In addition, the latch unit 310 feeds back the output of the NAND gate 332 and is input as a control signal. In the latch unit 310, the operation of the transfer gate 314 is controlled according to the output of the NAND gate 332 in the previous state. That is, when the output of the NAND gate 332 in the previous state is at the "high" level, the detection signal DET passes through the detection signal. ). The PMOS transistor 316 is turned off when the output of the NAND gate 332 in the previous state is at the "high" level and turned on when the output of the NAND gate 332 in the previous state is at the "low" level. . When the PMOS transistor 316 is turned on, the node N2 is at the power supply voltage VCC level. Here, the output of the NAND gate 332 in the previous state has a phase opposite to that of the pulse generator control signal DETP in the previous state. Accordingly, the latch unit 310 outputs a power supply voltage when the pulse generator control signal DETP of the previous state is "high" level active and the non-active level of the pulse generator control signal DETP of the previous state to the "low" level. In the case of, the detection signal DET is output. Table 1 below summarizes the operation of the signal sampler shown in FIG.

TABLE 1

DET DETE AKE P_DETP DETP L L L × L L L H H H L L H L L L H L H H L H L L L L H H H H L H H L L H H × × H

In Table 1 above, P_DETP represents a pulse generator control signal of a previous state, and "x" represents don't care.

Referring to Table 1, when the detection signal DET, the detection enable signal DETE, and the pulse signal AKE are all non-active at the "low" level, the pulse generator control signal DETP is at the "low" level. If the detection signal DET is at the "low" level and either the detection enable signal DETE or the pulse signal AKE is at the "high" level, the phase of the pulse generator control signal DETP is not changed. If the detection signal DET is at the "high" level, the pulse generator control signal DETP is activated to the "high" level.

Here, the detection signal DET is activated at the "high" level only when the detection enable signal DETE is active at the "high" level. In addition, the pulse signal AKE is generated by the pulse generator 114 (see FIG. 3) and is generated in response to the pulse generator control signal DETP.

Accordingly, the pulse generator control signal DETP is activated to the "high" level when the detection signal DET is at the "high" level, and then the detection enable signal DETE, the detection signal DET, and the pulse signal AKE. Are all at a "low" level when the "low" level is non-active. Therefore, the period during which the pulse generator control signal DETP is active can be secured sufficiently to stabilize the operation.

FIG. 6 is a detailed circuit diagram of the bank selector 400 shown in FIGS. 2 and 3, and includes inverters 402 and 408 and NAND gates 404 and 406. NAND gates 404 and 406 have a latch structure. The NAND gate 404 inputs the pulse signal AKE which is the output of the pulse generator 114 and the output of the NAND gate 406. The inverter 402 inverts the bank active master signal PR0. The NAND gate 406 inputs the output of the NAND gate 404 and the output of the inverter 402. The inverter 408 inverts the output of the NAND gate 404 to output the active kicker enable pulse AKE0. The other bank selectors shown in Figs. 2 and 3 have the same structure.

Table 2 summarizes the operation of the bank selector shown in FIG. 6, where PRi represents a bank active master signal and AKEi represents an active kicker enable pulse.

TABLE 2

AKE PRi P_AKEi AKEi L × × L H L H H H L L L H H × H

In Table 2 above, "x" represents no concern, and P_AKEi represents an active kicker enable pulse of a previous state. Referring to Table 2, the active kicker enable pulse AKEi is active at the "high" level when the bank active master signal PRi is active at the "high" level, and the pulse signal AKE is active at the "high" level. do. If the pulse signal AKE is at the "low" level, the active kicker enable pulse AKEi is non-active at the "low" level. In other cases, the state is maintained.

Therefore, when the active kicker enable pulse AKEi is activated to the "high" level, the active kicker enable pulse AKEi remains intact even when the bank active master signal PRi is non-active to the "low" level. And become non-active at the "low" level only when the pulse signal AKE is at the "low" level.

FIG. 7 is a timing diagram for describing an operation of a boosted voltage generator of the semiconductor memory device illustrated in FIGS. 3 to 6. In particular, FIG. 7 illustrates a case where bank 0 is activated in a 4-bank synchronous DRAM, precharged before VPP pumping is completed, and bank 2 is activated after a certain time, and bank 1 is activated and thus VPP pumping is performed. It is shown. That is, the case where bank 1 and bank 2 are activated at the same time is shown.

In FIG. 7, when the bank active master signal PR0 is activated to the "high" level, the output PRM of the inverter 244 becomes the "high" level in FIG. The bank access signal VPPE0 is also at the "high" level. The bank access signal VPPE0 is "low" when the bit line sense amplifier is driven in bank 1 (i.e., when the bit line sense amplifier drive signal PPS0 is slightly delayed after being activated to the "high" level, see FIG. 4). "Non-active to the level. The detection enable signal DETE is triggered when the bank access signal VPPE0 is at the "low" level to become the "high" level and "low" in response to the bank active master signal PR0 being at the "low" level. It becomes a level. The detection signal DET is active for a predetermined period of time according to the boosted voltage VPP level during the period when the detection enable signal DETE is at the "high" level, and the pulse generator control signal DETP is at the rising edge of the detection signal DET. Is triggered at " high " level, and pulse signal AKE is triggered at the rising edge of pulse generator control signal DETP to become " high " level. The period in which the pulse signal AKE is at the "high" level is kept constant. The pulse generator control signal DETP is at the "low" level in response to the falling edge of the pulse signal AKE. The active kicker enable pulse AKE0 is activated in response to the pulse signal AKE, thereby pumping up the boosted voltage VPP.

Next, a case in which bank 1 is activated, bank 2 is activated, and then bank 1 and bank 2 are simultaneously activated will be described.

Referring to FIG. 7, when the bank active master signal PR1 reaches the "high" level, the output PRM and the bank access signal VPPE1 of the inverter 244 in FIG. 4 become the "high" level in response thereto. . The bank access signal VPPE1 is at " low " level in response to the bit line sense amplifier drive signal PPS1. On the other hand, when bank 2 is activated while the bank active master signal PR1 is active (that is, when the bank active master signal PR2 is at the "high" level), it responds to the rising edge of the bank active master signal PR2. The detection enable signal DETE becomes the "low" level in response to the bank access signal VPPE2 being at the "high" level and the bank access signal VPPE2 at the "high" level. The bank access signal VPPE2 also becomes a "low" level in response to the bit line sense amplifier drive signal PPS2 becoming a "high" level. When the bank access signal VPPE2 becomes a "low" level, detection is enabled. The signal DETE goes back to the "high" level. In FIG. 4, the output PRM of the inverter 244 becomes a "low" level when all the bank active master signals PR0, PR1, PR2, and PR3 are all at "low" levels, and is on the falling edge of the PRM signal. In response, the detection enable signal DETE becomes a " low " level. The detection signal DET is activated when the boost voltage is less than the target level during the period when the detection enable signal DETE is active at the "high" level, and the pulse signal AKE is triggered on the rising edge of the detection signal DET. It becomes the "high" level. The pulse generator control signal DETP is at " low " level in response to the falling edge of the detection enable signal DETE, unlike when active for bank zero. This is because the falling edge of the pulse signal AKE occurs earlier than the falling edge of the detection enable signal DETE. Since the bank active master signal PR1 is active, the active kicker enable pulse AKE1 is activated by the pulse signal AKE.

Looking at the case where bank 2 is active (that is, when bank 1 and bank 2 are activated at the same time), the pulse generator control signal DETP becomes a "high" level in response to the rising edge of the detection signal DET and the pulse signal ( In response to the falling edge of AKE). Since the active kicker enable pulses AKE1 and AKE2 are active in the bank active master signals PR1 and PR2, the active kicker enable pulses AKE1 and AKE2 are activated at a "high" level in response to the pulse signal AKE, thereby performing a boost voltage pumping operation. do.

The present invention is not limited to these embodiments, and many variations are possible by those skilled in the art within the spirit of the invention. In particular, the boosted voltage generator of the semiconductor memory device according to the present invention can be applied not only to the four bank structure but also to the semiconductor memory device having a plurality of banks as described in the embodiment.

As described above, the synchronous semiconductor memory device having a plurality of bank structures has an advantage of reducing power consumed when the boosted voltage VPP is internally generated. In addition, since the layout area can be reduced, chip size can be reduced, and a single VPP detector can be used to detect and maintain a constant VPP level.

Claims (11)

A semiconductor memory device comprising a plurality of bank memories, the semiconductor memory device comprising: A detection enable signal generation unit for generating a detection enable signal that is activated when at least one of the plurality of bank memories is accessed; A boosted voltage detector configured to generate a detection signal DET that is activated when a level of the boost power supply is lower than a predetermined level when the detection enable signal DETE is active; A pulse generator which is triggered when the detection signal DET is activated and generates a pulse signal that is activated for a predetermined period of time; A plurality of bank selectors for generating active kicker enable pulses (AKE0, AKE1, AKE2, and AKE3) that are activated when the pulse signal (AKE) is active and access to the corresponding bank is performed; And And a plurality of active kickers for boosting a boosted voltage corresponding to an active period of the active kicker enable pulse, respectively. The method of claim 1, wherein the detection enable signal generation unit A plurality of bank access signal generators that generate bank access signals VPPE0, VPPE1, VPPE2, and VPPE3 that are activated from the time point at which access to the corresponding bank is started until bit line sense amplification is performed for the corresponding bank; A first logic unit 240 for outputting an active signal when any one of the plurality of bank active master signals PR0, PR1, PR2, and PR3 is active; A second logic unit 250 for ORing the plurality of bank access signals; And And a third logic unit configured to generate a detection enable signal DETE that is activated when the output of the first logic unit is non-active or the output of the second logic unit is active. . The method of claim 2, wherein the plurality of bank access signal generators, respectively A plurality of inverters for delaying and inverting the corresponding bit line sense amplifier driving signals PPS0, PPS1, PPS2, and PPS3; And And an AND gate for ANDing the final output of the inverters and the corresponding bank active master signal (PR0, PR1, PR2, PR3). The method of claim 1, wherein the plurality of bank selectors are respectively A first inverter 402 for inverting the corresponding bank active master signal; A first NAND gate for logically inverting a signal different from the pulse signal AKE; A second NAND gate logically inverting an output of the first inverter and an output of the first NAND gate and applying the output as another signal of the first NAND gate; And And a second inverter (408) for inverting the output of the first NAND gate to generate corresponding active kicker enable pulses (AKE0, AKE1, AKE2, and AKE3). A semiconductor memory device comprising a plurality of bank memories, the semiconductor memory device comprising: A detection enable signal generation unit for generating a detection enable signal that is activated when at least one of the plurality of bank memories is accessed; A boosted voltage detector configured to generate a detection signal DET that is activated when a level of the boost power supply is lower than a predetermined level when the detection enable signal DETE is active; A signal that generates a pulse generator control signal DETP that is active in response to the detection signal DET being activated and is inactive in response to both the pulse signal AKE and the detection enable signal DETE being nonactive. Sampler; A pulse generator that is triggered when the pulse generator control signal DETP is activated and generates a pulse signal that is activated for a predetermined period of time; A plurality of bank selectors for generating active kicker enable pulses (AKE0, AKE1, AKE2, and AKE3) that are activated when the pulse signal (AKE) is active and access to the corresponding bank is performed; And And a plurality of active kickers for boosting a boosted voltage corresponding to an active period of the active kicker enable pulse, respectively. The method of claim 5, wherein the detection enable signal generation unit A plurality of bank access signal generators that generate bank access signals VPPE0, VPPE1, VPPE2, and VPPE3 that are activated from the time point at which access to the corresponding bank is started until bit line sense amplification is performed for the corresponding bank; A first logic unit 240 for outputting an active signal when any one of the plurality of bank active master signals PR0, PR1, PR2, and PR3 is active; A second logic unit 250 for ORing the plurality of bank access signals; And And a third logic unit configured to generate a detection enable signal DETE that is activated when the output of the first logic unit is non-active or the output of the second logic unit is active. . The method of claim 6, wherein the plurality of bank access signal generators, respectively A plurality of inverters for delaying and inverting the corresponding bit line sense amplifier driving signals PPS0, PPS1, PPS2, and PPS3; And And an AND gate for ANDing the final output of the inverters and the corresponding bank active master signal (PR0, PR1, PR2, PR3). 6. The signal sampler of claim 5, wherein the signal sampler is Latch unit 310; A first logic gate 320 for outputting an active signal when any one of the detection enable signal DETE and the pulse signal AKE is active; And A second logic gate 330 for generating the pulse generator control signal DETP that is activated when both the output of the latch unit and the output of the first logic gate are active, And the latch unit outputs a power supply voltage when the pulse generator control signal DETP is active, and outputs the detection signal DET when the pulse generator control signal DETP is active. The method of claim 8, wherein the second logic gate is A NAND gate 332 for inputting an output of the latch unit and an output of the first logic gate 320; And And a first inverter (334) for inverting the output of the NAND gate. The method of claim 9, wherein the latch unit A second inverter 312 inverting the output of the NAND gate; A transmission gate 314 controlled by an output of the NAND gate and an output of the second inverter, for passing the detection signal DET when the output of the NAND gate is at a "high" level; And Its own drain-source path having a PMOS transistor 316 connected between a supply voltage VCC and an output of the transfer gate, and its own gate connected to an output of the NAND gate 332. A boosted voltage generator of a semiconductor memory device, characterized in that. The method of claim 5, wherein the plurality of bank selectors are respectively A first inverter 402 for inverting the corresponding bank active master signal; A first NAND gate for logically inverting a signal different from the pulse signal AKE; A second NAND gate logically inverting an output of the first inverter and an output of the first NAND gate and applying the output as another signal of the first NAND gate; And And a second inverter (408) for inverting the output of the first NAND gate to generate corresponding active kicker enable pulses (AKE0, AKE1, AKE2, and AKE3).

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