KR100237465B1 - Alarm circuits for telephone network access subsystem - Google Patents

Abstract

The present invention relates to an alarm processing circuit of a telephone network matching device (TNAS) for processing alarms of boards constituting a telephone network matching device of a mass communication processing system.

The present invention includes buffers 416 and 418 which store the open alarms and malfunction alarms of the trunk interface and subscriber modem connections, and output alarm data on the data bus when a chip enable signal is input; A decoder (414) for generating a chip enable signal for enabling the buffer when a predetermined address is input; And an alarm processing circuit including a central processing unit 412 that outputs a predetermined address at predetermined time intervals, reads alarm data, and delivers the read data to the service processing unit. Alarm status of target boards can be monitored.

Description

Circuit for processing alarms in the telephone network access subsystem of information communication processing system

The present invention relates to a telephone network matching device of a large-capacity communication processing system, and more particularly, to an alarm processing circuit of a telephone network matching device (TNAS) for processing alarms of boards constituting the telephone network matching device. .

In general, a public telephone network is a communication network for transmitting voice signals to other subscribers in a network by performing circuit switching according to call requests of telephone subscribers, and a packet switching network is a communication network for transmitting digital data between computers through packet switching. Although these networks tend to be integrated with each other as the B-ISDN is promoted, they are still composed of individual networks, so the procedures for exchanging services between networks have been very complicated.

Almost all households and companies are subscribed to the public telephone network and are used most widely, but the service is mainly voice-based telephone service. However, as the information society progresses, data transmission between computers is widely required, and various information providers are on the rise and the demand for access to packet networks is rapidly increasing. Therefore, the type of service connected to the packet switching network has been increased by using the telephone line used in general homes, and for this purpose, an information communication processing system has been introduced into the connection between the public telephone network and the packet network.

In the conventional communication processing system, as the network evolves, a wide variety of networks, such as an ISDN network, a frame relay network, an ATM network, and the Internet, have been newly established. In order to connect them integrally and to further increase processing capacity, FIG. As shown, it has been improved with a large capacity communication processing system.

1 is a block diagram illustrating a general mass communication processing system, wherein the mass communication processing system 100 includes a telephone network matching device (TNAS) 110 for connecting to a public telephone network 101, an ISDN network 102, and the like. ISDN matching device (INAS: 130) for connection, packet network matching device (PNAS: 120) for connection with packet communication network 103, ATM network matching device (ANAS :) for connection with high speed (ATM) communication network 104 140), frame network matching device (FNAS: 150) for connection with frame relay network 105, internet matching device (KNAS: 160) for connection with internet 106, high speed switch for connecting each matching device with each other Module (HSSF: 170), unit system management device for network management (LOAMS: 180), etc. to connect subscribers (PC or hightel terminals) connected to public telephone networks or ISDN to information providers (IP) connected to other networks. give.

Referring to FIG. 1, a telephone network matching device (TNAS) 110 is a high speed switch module 170 for matching a trunk signal with a digital relay line (E1 or T1) of an electronic switchgear, a number system and a signaling method used in a telephone network. ) To connect subscribers connected to the public telephone network (101) to other subscribers such as the packet network (103) by performing the function of connecting the public telephone network (101), collecting statistics and delivering billing information about the user's service use It is a device that connects to the database of the information provider (IP) connected to the network. The conventional telephone network matching device is configured as shown in FIG. 2 so that one telephone network matching device can accommodate 96 channels, and one entire system can accommodate 10 telephone network matching devices to accommodate 960 channels in total. It is supposed to be.

2. Description of the Related Art A conventional telephone network matching device includes a trunk interface module (TNIF: 210), a subscriber modem connection (TDLA; 220, 221), a high data processing assembly (HDPA; 230, 231), as shown in FIG. , A text service processor assembly (TSPA; 250), and a high speed network adapter (HSNA; 241), the trunk interface module 210 includes a digital T1 trunk interface assembly (Extended T1 trunk Interface Assembly) Extended CEPT trunk Interface Assembly: ETIA / ECIA; 211), Concentration Board (T1 clock Generation & switch Interface / CEPT clock Generation & switch Interface Assembly: TGIA / CGIA; 212), Signal Processing Board (Text Signal Transition Assemply: STA; 213), Universal Signaling Transciever Assembly (USTA; 214), Telephone Network Processor Assembly (TNPA; 215), Alarm Access Control Assembly (AACA) 21 6) to link the users connected to the telephone network of the large capacity communication processing system with the information providers built on the packet network.

Referring to FIG. 2, the service processing unit (TSPA) 250 is duplexed into two boards, and the high speed switching interface unit HSNA 240 and 241 and the plurality of subscribers for interworking with the high speed switching fabric HSHS 170. It is responsible for controlling the modem connection unit (TDLA: 220, 221) and the data processing unit (HDPA: 230, 231). That is, the main functions of the service processing unit (TSPA) 250 provide a telephone network subscriber interface and management, data processing of subscribers and information providers, high speed switch interface (HSNA) interworking, and service control and self maintenance.

The signal of the public telephone network subscriber is designated by the trunk matching module (TNIF: 210), and is transmitted to the data processing unit (HDPA: 230, 231) at the RS-232C level through the corresponding modem of the subscriber modem connection (TDLA: 220, 221). In this case, one subscriber modem connection unit (TDLA) accommodates 16 channels, so two boards are connected to each other in order to process one subhighway (32 channels), and one board is connected to 32 channels for one data processing unit (HDPA). I can accept it. Therefore, six subscriber modem connections (TDLA) and three data processing units (HDPA) are required to process 96 channels (three subhighways).

The data processor (HDPA: 230, 231) transmits and receives data in units of 32 channels / PBA, and transmits X.3 parameters to the received data to the service processor (TSPA: 250) through the transmission and reception queues, which are determined in 132 byte units, respectively. do. The service processing unit (TSPA) 250 transmits packet related information to the high speed switch interface unit (HSNA: 240, 241), and the high speed switch interface unit (HSNA: 240, 241) transmits this data to the high speed switch module (HSSF: 170 of FIG. 1). Through the packet network matching device (PNAS: 120 of Figure 1) through.

Motorola's MC68030 / 50MHz is used as the main processor of the service processor (TSPA: 250) and Motorola's MC68360, an IPC (Inter Processor Communication) dedicated communication processor, is used for data communication with the data processor (HDPA: 230,231). Data is transmitted in an interrupt manner through 1M bytes of common memory. The data processor (HDPA: 230, 231) uses Motorola's MC68360 as the main processor and controls four slave processors. The main processor of the data processor (HDPA: 230, 231) transmits and receives data in 2 Mbps serial communication between the slave and the service processor (TSPA: 250).

In FIG. 2, the digital relay line matching board (ETIA / ECIA: 211) matches 4T1 or 3E1. When the 4T1 is matched, the “ETIA” board is used and when the 3E1 is matched, the “ECIA” board is used. The aggregation board (TGIA / CGIA: 212)) receives the reference clock to generate the system clock, handles the subhighway switching function, and the signal service board (USTA: 214) is an R2 MFC and DTMF known as a standard for inter-station relay. It handles tones and performs services related to tones. The alarm access control unit (AACA: 216) collects hardware alarms, determines a status, reports the maintenance alarm, and performs a matching function with the maintenance processor. The telephone network matching processor (TNPA: 215) communicates with the service processor (TSPA) 250 and controls each device.

In Figure 2, the telephone network matching module (TNIF: 210) provides access to the public telephone network 101 through a PCM transmission line of 1.544 Mbps T1 or 2.048 Mbps E1, collects outgoing subscriber numbers by R2 MFC signaling, and subscriber information. Is transmitted to the service processing unit (TSPA) 250. When the reception of the service processing unit TSPA 250 is confirmed, the service processing unit TSPA is connected to the information provider IP connected to the packet network matching device 120 via the high speed switch module HSSF 170. That is, the telephone network matching device 200-1 to 200-10 connects modems in response to various modems of telephone subscribers, multiplexing function of digital data, communication protocol processing function, raw charging data collection function, Handle each of the subsystem maintenance itself.

In the conventional telephone network matching device, a circuit for processing alarms of the boards constituting the telephone network matching device is conventionally separate as a separate board (alarm access control board), as shown in FIG. There was a problem that the manufacturing cost increases. That is, in FIG. 2, the alarm control access board is configured as an independent board, and the alarms of the boards are collected and transferred to the upper processor in charge of maintenance.

Accordingly, the present invention has been proposed to solve the above problems, and provides an alarm processing circuit with improved hardware to implement an alarm processing function in a processor interface board (TPIA) in a telephone network matching device of a large capacity communication processing system. There is a purpose.

In order to achieve the above object, the apparatus of the present invention is connected to a digital trunk of a public telephone network, transmits / receives a predetermined number of E1 data, extracts a clock from data received from the trunk, and provides a network synchronizer clock. A trunk interface for processing R2 MFC signaling and switching E1 data and subhighway (SHW) data; A processor interface unit for exchanging subhighway data with the trunk interface unit, processing non-blocking digital switching, and communicating control information with the trunk interface via an L-bus; One board has 16 codecs, 16 modem chips, and 16 RS-232C interfaces to handle 16 channels of DS0 levels, and two boards are grouped to transmit the processor interface and one subhighway data. A plurality of subscriber modem connections for receiving / processing and communicating control information with the processor interface via an L-bus; A plurality of data processing units for multiplexing and demultiplexing by transmitting / receiving 32 sets of RS-232C data to and from the subscriber modem access unit and outputting the multiplexed data through a serial bus; Transmit and receive data through the serial bus with the plurality of data processing units, transfer data through the VME bus, exchange call processing related control information through the S-bus with the processor interface unit, and maintain the telephone network matching device. Service processing unit for processing; And a high speed switch interface unit connected to the service processor through a VME bus and connected through a high speed switch module and a TAXI bus, wherein the telephone network matching device of the trunk communication unit and the subscriber modem connection unit are open alarms. A buffer for storing a malfunction alarm and outputting the alarm data on a data bus when a chip enable signal is input; A decoder configured to generate the chip enable signal for enabling the buffer when a predetermined address is input; And an alarm processing circuit configured to output a predetermined address at predetermined time intervals, read the alarm data, and transmit the read alarm data to the service processor.

1 is a block diagram showing the overall configuration of a large capacity communication processing system;

2 is a block diagram showing a conventional telephone network matching device in a mass communication processing system;

3 is a block diagram showing a telephone network matching device to which the present invention is applied;

4 is a block diagram showing an alarm processing circuit of the telephone network matching device according to the present invention;

5 is a diagram illustrating a format of alarm data according to the present invention;

6A and 6B are flowcharts illustrating an alarm processing procedure according to the present invention.

* Explanation of symbols for main parts of the drawings

101: public telephone network (PSTN) 301: L-bus

302: S-bus 303: RS-232C

304: serial bus 305: VME bus

306a, 306b: TAXI bus 310: trunk interface (TNIA)

312: processor interface (TPIA) 314: subscriber modem connection (TDIA)

316: data processing unit (HDPA) 318: service processing unit (TSPA)

319a and 319b: high speed switch interface unit 401: upper processor

410: alarm processing circuit 412: central processing unit

414: decoder 416: first buffer

418: 2nd buffer 420-1-420-8: Monitoring target board

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the telephone network matching device to which the present invention is applied includes a trunk interface unit (TNIA; 310) that is directly connected to the public telephone network 101 and accommodates 4E1. Telephone Processing Interface Assembly (TPIA; 312), Subscriber Modem Interface (Text Data Interface Assembly: TDIA; 314), Highly Data Processing Assembly (HDPA: 316), Text Service Processor Assembly (TSPA; 318), High Speed Network Adapter (HSNA; 319a, 319b).

Comparing FIG. 3 with FIG. 2, it can be seen that the alarm processing circuit according to the present invention is implemented in the processor interface unit 312 so that the conventional alarm access control board 216 can be removed, which is a very compact structure. Here, two subscriber modem access boards 314 capable of accommodating 16 channels can be processed in a group to process one subhighway (SHW: 32 channels), so 2x4 = 8 boards are required to process 4E1. The data processor 316 correspondingly requires four boards (32 channels / board). The service processor 318 is redundant to improve reliability, and the high speed switch interface units 319a and 319b may also be duplicated.

Referring to FIG. 3, a trunk interface unit (TNIA) 310 may be connected to a public telephone network 101 to accommodate 4E1, and switch four time slots SHW to the processor interface unit 312 by switching time slots. It performs the digital trunk interface (TLI) function and link signal matching (LSI) function. The trunk interface unit (TNIA: 310) is connected to the processor interface unit 312 through the L bus 301 and is controlled by the processor interface unit (TPIA: 312) using a public telephone network (PSTN: 101) using the CEPT method. It is matched with relay circuit between stations and transmits / receives signal information of relay line using tone and R2 signal system. At this time, the transmission speed of the CEPT method (E1) is "2.048Mbps", and the line code "HDB3" is used.

The trunk interface (TNIA: 310) also accepts R2 signals, provides a ring back tone, and incorporates a network synchronizer to synchronize the transmission bits of the trunk line. The 2.048 MHz clock extracted from is used, and the local clock generated by the network synchronization circuit of the trunk interface 310 is 16.384 MHz. That is, the trunk interface unit 310 is provided with a network synchronization circuit to generate 16.384 MHz synchronized with 2.048 MHz extracted from the trunk line, and then divides it and is required by the processor interface unit 312 and the subscriber modem connection unit 314. Various clocks (4M, 2M, 8KHz clock) are provided.

Looking at the transmission operation is performed through the trunk interface 310, four sub-highway (SHW0 to SHW3) data consisting of 32 time slots input from the digital switch of the processor interface (TPIA: 312) is the trunk interface unit Channel matching is performed at the digital switch MT8980 of step 310 and input to the CEPT framer. The CEPT framer of the trunk interface unit 310 formats the subhighway data (SHW Data) and the signal data (Signalling Data) to the CEPT format, and performs HDB3 line coding at the line interface unit and then converts the unipolar-bipolar (U / B) into Output to CEPT type PCM trunk line.

On the contrary, the reception process receives the CEPT format data from the PCM relay line, switches the time slots in the trunk interface 310 to access the subhighway data, and processes various alarms, error detection, and signaling. The frame synchronization (FS: 8KHz) clock and the 4MHz clock required are generated by the network synchronization circuit of the trunk interface 310.

Meanwhile, the link signaling matching (LSI) function of the trunk interface unit (TNIA) 310 is an R2 MFC signal transmission / reception and a tone supply function. When the trunk interface unit 310 receives a scissors request from the trunk line, the trunk interface unit 310 transmits the scissors request information to the processor interface unit TPIA: 312, and the processor interface unit TPIA: 312 receives the request from the trunk. The input data channel is connected to the R2 signal receiving processor of the trunk interface unit. The trunk interface unit (TNIA) 310 receives a signal input from the trunk line, translates the signal, and transmits the signal to the processor interface unit (TPIA: 312). The trunk interface unit (TNIA) 310 provides forward and backward signals required by the R2 signaling method. In addition, the trunk interface 310 performs a tone providing function. Since only a ring back tone is required due to system characteristics, the trunk interface unit 310 continuously allocates a tone channel.

In FIG. 3, the processor interface unit TPIA 312 processes control processing through the L-bus 301 for various events occurring at the trunk interface unit TNIA 310 and the subscriber modem connection unit TDIA 314. It has a function of collecting various alarms of a device that it controls.

In addition, a call-related communication is performed through the S bus 302 with a service processor (TSPA) 318, which is an upper processor. The processor interface unit TPIA 312 employs a Motorola multi-protocol processor (MC68302 IMP) to reduce and simplify circuit, power, and component density. Motorola's MC68302 is a high-performance processor that has a variety of peripheral devices that require a control structure in the existing 68000 CPU, and basically provides various interfaces required by a conventional processor.

The subscriber modem connection unit (TDIA: 314) includes 16 codecs, a modem, and an RS-232C interface unit on one board to accommodate 16 channels, and two boards are grouped into one subhighway (32 channels). ). Eight boards are required to handle 4E1. The subscriber modem connection unit 314 is a text data line interface board for matching an information retrieval terminal connected to the public telephone network 101. The subscriber modem connection unit 314 is a subscriber unit and a data processing unit of the telephone network via the trunk interface unit TNIA 310. HDPA: 316). In addition, it provides a mode that can automatically detect the modulation method of the information search terminal. The board accommodates 16 channels, and is connected to the trunk interface 310 and the processor interface 312 through the L-bus 301. The subscriber modem access unit (TDIA: 314) modulates the digital data inputted from the data processing unit (HDPA: 316), filters the signal, and converts the digital data into a digital code signal by the PCM method to condense them into multiple communication paths. On the contrary, the PCM signal is demodulated and then transmitted to the data processing unit (HDPA) 316.

Referring to FIG. 3, the service processor TSPA 318 controls the high speed switch interface units HSNA 319a and 319b and the data processor HDPA 316 for interworking with the high speed switch module HSSF 170 of FIG. 1. In charge of the function. The main functions of the service processing unit (TSPA) 318 provide the interface and management of subscribers of the telephone network, data processing of subscribers and information providers, interworking with the HSNA, and service control and self-maintenance functions.

The data processor (HDPA: 316) transmits and receives data in units of 32 channels / board, and assigns X.3 parameters to the received data and transmits them to the service processor (TSPA: 318) through the transmission and reception queues defined in units of 132 bytes. do. The service processing unit (TSPA) 318 transmits the packet related information to the high speed switch interface unit (HSNA: 319a, 319b) via the VME bus 305, and the high speed switch interface unit (HSNA: 319a, 319b) transmits this data. The high speed switch module (HSSF: 170 of FIG. 1) is transferred to the corresponding packet network matching device (PNAS: 120 of FIG. 1).

Motorola's MC68030 / 50MHz is used as the main processor of the service processor (TSPA: 318) and Motorola's MC68360, an IPC dedicated communication processor, is used for data communication with the data processor (HDPA: 316). Data is transmitted in an interrupt manner through 1M bytes of common memory. The data processor (HDPA: 316) uses Motorola's MC68360 / 25MHz as the main processor and controls four slave processors. The main processor of the data processing unit (HDPA: 316) transmits / receives data with the slave and the service processing unit (TSPA: 318) in 2 Mbps serial communication.

In FIG. 3, the trunk interface unit 310, the processor interface unit 312, and the subscriber modem connection unit 314 are connected by the L-bus 301, and the processor interface unit 312 and the service processor 318 are connected to each other. The bus 302 is connected, and the data processor 316 and the service processor 318 are connected to the serial bus 304. The service processing unit 318 and the high speed switch interface unit 319a and 319b are connected through the VME bus 305, and the subscriber modem connection unit 314 and the data processing unit 316 are connected to a plurality of RS-232Cs 303. The high speed switch interface units 319a and 319b are connected to the high speed switch module HSSF through the TAXI bus (100Mbps: 306a, 306b).

4 is a block diagram showing an alarm processing circuit of the telephone network matching device according to the present invention, FIG. 5 is a diagram showing the format of alarm data according to the present invention, and FIGS. 6A and 6B are alarm processing according to the present invention. A flowchart illustrating the procedure.

Referring to FIG. 4, the alarm processing circuit of the present invention monitors up to eight target boards including a central processing unit (CPU) 412, a decoder 414, a first buffer 416, and a second buffer 418. As a result, the data is transmitted to the upper processor 401. This alarm processing circuit of the present invention is preferably implemented in the processor interface 312 shown in Figure 3, the control target board is six subscriber modem access boards (TDIA) and one trunk interface board (TNIA).

In FIG. 4, the central processing unit 412 is implemented as, for example, Motorola's MC68302 Integrated Multi-protocol Processor (IMP) to communicate with the upper processor 401 through a serial communication port, and includes an address bus, a data bus, and a control. It provides a bus and handles the alarm by performing the procedure shown in Figure 6B.

The decoder 414 generates a chip select signal and outputs the chip selection signal to the first buffer 416 and the second buffer 418 when the specific address is input through the address bus as the address decoder. Each of the first buffer 416 and the second buffer 418 is an 8-bit buffer and stores information related to the alert in the format shown in FIG. 5.

The first buffer 416 receives and stores alarm data from the first to fourth boards, which are the monitoring target boards. In the embodiment of the present invention, the alarm contents of each monitoring target board are “open” indicating mounting and dismounting of the boards. Open Alarm (OA) "and" Function Fail Alarm (FF) "to indicate when the board malfunctions.

The second buffer 418 receives and stores alarm data from the fifth to eighth boards that are the monitoring target boards. In this case, the alarm content of each monitoring target board is an open alarm (OA) indicating mounting and dismounting of the board, and a function fail alarm (FF) indicating when the board malfunctions.

When the board is mounted, the first monitoring target board 420-1 grounds the "OA1" signal low when the board is mounted so that bit 0 of FIG. 5 is low, and when the board is mounted, the ground is removed and "OA1" is removed. Let the signal go high. Accordingly, when the first monitoring target board 420-1 is removed, bit 0 of FIG. 5 becomes high to display an alarm. In a similar manner, the "FF1" signal is set low when the first board operates normally, and the "FF1" signal is set high when the operation of the first board is interrupted. As described above, the first monitoring target board 420-1 displays its alarm state in bits 0 and 1 of the first buffer 416 according to the flow shown in FIG. 6A. Referring to FIG. 6A, in step 601, each of the monitoring target boards writes its alarm related information to the first buffer or the second buffer.

In the same manner, the second supervised board 420-2 transmits the OA2 signal to bit 2 in the format of FIG. 5, writes the FF2 signal to bit 3, and the third supervised board 420-3 is bit 4 Transmits the OA3 signal and writes the FF2 signal to bit 5. Similarly, bits 6 and 7 of FIG. 5 are assigned the fourth monitoring target board 420-4, bits 8 and 9 are assigned the fifth monitoring target board 420-5, and bits 14 and 15 are assigned to the fourth monitoring target board 420-4. The eighth monitoring target board 420-8 is assigned. In the embodiment of the present invention, subscriber modem access boards (TDIA) 0 to 5 are used as the first to sixth monitoring target boards, respectively, and a trunk interface board (TNIA) is used as the seventh monitoring target board.

Referring to FIG. 6B, if an interrupt occurs at a predetermined time interval (8 mm sec in the embodiment of the present invention) in step 611, the central processing unit outputs a predetermined address (e.g., 230000H) in step 612. FIG. When the predetermined address is output, the decoder 414 decodes the chip enable signal to generate the chip enable signal. When the chip enable signal is input in step 613, the first buffer 416 and the second buffer 418 are stored in step 614. Output alarm information on the data bus. The CPU 401 reads the alarm information on the data bus, takes an appropriate action when an error occurs, and delivers it to the upper processor 401 at step 615.

The alarm information may be displayed by using the alarm information read by the central processing unit 412 between steps 614 and 615. However, in the embodiment of the present invention, the alarm information collected by the upper processor 401 is transmitted as it is. And perform all maintenance related functions on the upper processor.

As described above, the telephone network matching device of the high-capacity communication processing system to which the present invention is applied can simplify the hardware configuration by adding the alarm processing circuit to the processor interface board TPIA without dividing the alarm processing circuit into a separate board. And the alarm processing circuit of the present invention is composed of a very simple circuit has the effect of monitoring the alarm state of a plurality of monitoring target board.

Claims (3)

It is connected to a digital trunk of a public telephone network and transmits / receives a predetermined number of E1 data, extracts a clock from the data received from the trunk, provides a network synchronizer clock, processes R2 MFC signaling, and handles E1 data and subhighway ( SHW) trunk interface unit 310 for switching data; A processor interface unit 312 for exchanging sub-highway data with the trunk interface unit, processing non-blocking digital switching, and communicating control information with the trunk interface via an L-bus; One board has 16 codecs, 16 modem chips, and 16 RS-232C interfaces to handle 16 channels of DS0 levels, and two boards are grouped to transmit the processor interface and one subhighway data. A plurality of subscriber modem connections 314 for receiving and processing and communicating control information with the processor interface via an L-bus; A plurality of data processing units 316 for multiplexing and demultiplexing by transmitting / receiving 32 sets of RS-232C data with a set of subscriber modem accessing units and outputting the multiplexed data through a serial bus; Transmit and receive data through the serial bus with the plurality of data processing units, transfer data through the VME bus, exchange call processing related control information through the S-bus with the processor interface unit, and maintain the telephone network matching device. Service processing unit 318 for processing; And a high speed switch interface unit (319a, 319b) connected to the service processor through a VME bus and connected through a high speed switch module and a TAXI bus. Buffers (416, 418) for storing the open alarms and malfunction alarms of the trunk interface and subscriber modem connections and outputting the alarm data on a data bus when a chip enable signal is input; A decoder (414) for generating the chip enable signal for enabling the buffer when a predetermined address is input; And An alarm processing circuit comprising a central processing unit 412 which outputs a predetermined address at predetermined time intervals, reads the alarm data, and then delivers the read data to the service processor. And an alarm processing circuit in a telephone network matching device of a large capacity communication processing system, characterized in that it is provided in said processor interface (TPIA). 2. The alarm processing circuit according to claim 1, wherein the decoder (412) provides a chip enable signal when a 230000H address is input. The alarm processing circuit according to claim 1, wherein the central processing unit (412) is implemented by Motorola MC68302 IMP to read alarm data at 8 msec intervals.

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