KR100234362B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device including a data bus connection for a read operation capable of preventing a malfunction is disclosed. The semiconductor memory device includes a plurality of memory banks, and includes a plurality of bank data buses, a shared data bus, and a plurality of data bus connections for read operations. Each of the bank data buses is connected to a corresponding memory bank, and each of the plurality of bank data busses includes at least one bank data line and a bank inverted data line, and the shared data bus is applied to or outputted from the outside of the semiconductor memory device. The data and inversion data signals to be transmitted are composed of at least one shared data line and shared inversion data lines. Data bus connections for a read operation are respectively connected between the bank data bus and the shared data bus, which are turned on if the read operation is selected and the bank is selected, otherwise it is turned off. Thus, there is an advantage that data contention on the shared data bus is prevented and data read / write operations are stably performed.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a plurality of banks, the semiconductor memory device including a data bus connection for a read operation for preventing a malfunction due to data contention on a shared data bus. It is about.

The semiconductor memory device employs a plurality of memory bank structures in order to realize high bandwidth operation. The memory banks are accessible independently of each other, and either one is selectively accessed by the bank address. That is, the entire memory is divided into a plurality of memory banks, and at any time, any one memory bank is selectively accessed to perform a read / write operation and the remaining memory banks are not accessed. Here, the inaccessible memory banks are accessed at the previous time point or at the next time point, and control for this is performed. Therefore, since the semiconductor memory device including the plurality of memory banks can perform the access operation and the control operation in different memory banks, the semiconductor memory device can operate in a high band. Such data read / write operations and control operations are performed in the synchronous DRAM (Synchronous Dynamic Random Access Memory) based on the row address strobe signal (RAS) signal.

A semiconductor memory device having a plurality of memory banks having such a function includes bank data buses on which data read from each memory bank and data to be written are loaded. Each bank data bus contains twice as many signal lines as the number of memory cells in which read / write operations are performed at one time.

That is, when four data read / write operations can be performed at a time, each bank data bus includes four bank data lines and four bank inverted data lines. On the other hand, as the integration of semiconductor memory devices is performed, the size of the memory cell array included in one bank also increases, so that one memory bank is divided into a plurality of blocks.

FIG. 1 illustrates a semiconductor memory device including two memory banks (A memory bank and a B memory bank), each of which consists of a plurality of blocks. Referring to FIG. 1, the A memory bank 100A includes a plurality of cell array blocks 101A, 102A, ..., and the B memory bank 100B includes a plurality of cell array blocks 101B, 102B, ...) is included. The cell array blocks 101A, 102A, ..., 101B, 102B, ... include corresponding bit line sense amplifiers 171A, 172A, ..., 171B, 172B, .... In addition, the bank data buses 141A, 142A, ..., 141B, 142B, ... correspond to the cell array blocks 101A, 102A, ..., 101B, 102B, ... Working data bus connections 111A, 112A, ..., 111B, 112B, ..., data bus connections 121A, 122A, ..., 121B, 122B, ... for read operations and gates ( 161A, 162A, ..., 161B, 162B, ...) are provided.

The cell array block includes a plurality of word lines, a plurality of bit lines / inverting bit lines, memory cells in addition to a bit line sense amplifier. In the cell array block, data written to or read from each memory cell is carried on the bit line and the inverting bit line, and the voltage difference between the bit line and the inverting bit line is amplified by the bit line sense amplifier. Also, some of the plurality of bit lines and the plurality of inverted bit lines are selectively connected to the local data lines and the local inverted data lines based on externally applied column address information. In FIG. 1, the cell array block also includes four local data lines and four local inverted data lines. Referring to the cell array block 101A, a gate portion 161A is connected between the local data lines / local inverted data lines and the bank data bus 141A. The gate unit 161A includes eight NMOS transistors, and a bank select gate signal CSL_A is applied to gates of the NMOS transistors. Thus, when the bank select gate signal CSL_A is activated to the "high" level, the bank data lines and the banks of the bank data bus 141A are turned on so that the local data lines and the local inverted data lines correspond to them. Each of the inversion data lines is electrically coupled. The remaining gate portions 162A, ..., 161B, 162B, ... also operate in this manner. Here, only one of the bank select gate signals CSL_A and CSL_B is activated to a "high" level.

Therefore, when the NMOS transistors included in the gate parts 161A, 162A, ... are turned on, the NMOS transistors included in the gate parts 161B, 162B, ... are kept turned off. When the NMOS transistors included in the gate parts 161B, 162B, ... are turned on, the NMOS transistors included in the gate parts 161A, 162A, ... are kept turned off.

The data bus connection 111A for a write operation is connected between the bank data bus 141A and the shared data bus 150 and transfers data loaded on the shared data bus 150 to the bank data bus 141A during a write operation. To pass. Other data bus connections for write operations operate in the same way. Here, the data bus connections for the write operation are independently controlled so that signals of the shared data bus are transferred to the selected bank data bus without being affected by the bank data bus belonging to the other bank.

The data bus connection 121A for a read operation is connected between the bank data bus 141A and the shared data bus 150 and transfers signals carried on the bank data bus 141A to the shared data bus 150 during the read operation. To pass. At this time, the signals appearing on the bank data bus 141A are not full swings, but have a small value, and thus must be converted to values swinging through the sense amplifiers. Such a sense amplifier may be included in the data bus connection for the read operation, or may be provided on the shared data bus 150. The data bus connection for the rest of the read operation works as well.

FIG. 2 illustrates in detail the data bus connection for the read operation shown in FIG. 1. In FIG. 2, the precharger 210 is composed of a plurality of NMOS transistors. NMOS transistors 211 and 212 are connected in series between the bank data line IO3 and the bank inversion data line IO3B, and the drain / source of the NMOS transistor 213 is connected to the bank data line IO3 and the bank inversion. It is connected between the data lines IO3B.

The gates of the NMOS transistors 211, 212, and 213 are commonly connected, and the block select signal BLSij is inverted and applied. The block selection signal BLSij is generated based on a row address applied from the outside of the semiconductor memory device. When the block is selected, the block selection signal BLSij is set to a "high" level. The inverter 270 inverts the block select signal BLSij and applies the gates of the NMOS transistors included in the precharger 210. The precharge voltage VBL is applied to the connection points of the NMOS transistors 211 and 212, and the precharge voltage VBL has a value of about 1/2 of the power supply voltage VDD. Therefore, when the block selection signal BLSij becomes "low" because no corresponding block is selected, the bank data lines IO0, IO1, IO2, and IO3 and the bank inversion data lines IO0B, IO1B, IO2B, and IO3B. Are all precharged to the precharge voltage VBL. That is, when the corresponding block is not selected, the bank data lines and the bank inversion data lines are precharged with the precharge voltage.

Equalizer 230 is composed of a plurality of PMOS transistors. The PMOS transistors 231 and 232 have a drain / source path connected in series between the bank data line IO3 and the bank inversion data line IO3B, and the PMOS transistors 233 are connected to the bank data line IO3. The drain / source path is connected between the bank inversion data lines IO3B. In addition, the output of the NAND gate 274 is applied to the gates of the PMOS transistors 231, 232, and 233. Inverter 272 inverts equalizer control signal IOPRB. The equalizer control signal IOPRB is for equalizing the bank data lines and the inverted data lines when the data read / write operation is not performed and is a "low" level active signal. The equalizer control signal IOPRB is triggered when the column address strobe signal CASB applied from the outside of the semiconductor memory device is activated to the "low" level, and transitions to the "high" level. Here, a read / write operation is performed for the column address strobe signal CASB to be at the "low" level and the column address applied from the outside.

Therefore, the equalizer control signal IOPRB is at the "high" level when the read / write operation is performed and at the "low" level otherwise.

The NAND gate 274 inputs the block select signal BLSij and the output of the inverter 272. Thus, the output of the NAND gate 274 is activated to the "low" level when the block select signal BLSij is at the "high" level and the equalizer control signal IOPRB is at the "low" level.

That is, the PMOS transistors included in the equalizer 230 are turned on when the corresponding block is selected but no read / write operation is performed to equalize the bank data lines and the bank inverted data lines.

The read / write division signal PWR becomes a "low" level in the case of a read operation and a "high" level in the case of a write operation. The inverter 276 inverts the read / write division signal PWR, and the NAND gate 278 inputs the block select signal BLSij and the output of the inverter 276. Thus, the output PWD of the NAND gate 278 is activated to the "low" level when the block select signal BLSij is at the "high" level and the read / write division signal PWR is at the "low" level. That is, when the corresponding block is selected and the read operation is performed, the output of the NAND gate 278 is activated to a "low" level, and the PMOS transistors included in the switching unit 250 are turned on. Thus, data signals and inverted data signals carried on the bank data lines IO0, IO1, IO2, and IO3 and the bank inverted data lines IO0B, IO1B, IO2B, and IO3B are shared data lines DIO0, DIO1, and DIO2. , DIO3) and shared inversion data lines DIO0B, DIO1B, DIO2B, and DIO3B.

3 illustrates signal waveforms appearing in bank data lines and shared data lines in a read operation in the semiconductor memory device having such a configuration. In Figure 3, when a read operation is performed (i.e., when the PWR signal is at the "low" level), the data bus connection for the read operation of the selected block, regardless of the bank, is turned on. Thus, not only are the bank data buses belonging to the selected bank and the selected block electrically coupled to the shared data bus, but also the bank data buses belonging to the unselected bank but belonging to the block selected by the same block selection signal are also connected to the shared data bus. Electrically coupled. Thus, there is a problem that the shared data bus is affected by the unselected bank data bus and data is not transferred properly.

In FIG. 3, the DIO shows signal waveforms of the shared data line and the shared inverted data line included in the shared data bus.

In other words, the shared data bus should transmit only the signal indicated on the selected bank data bus. The data bus connection for read operation, which should not be turned on, is turned on, causing a malfunction. Here, the bank data lines and the bank inverted data lines belonging to the unselected block are equalized to the power supply level VDD. Therefore, the signal level is weakened because the equalized signals are transmitted to the shared data bus in addition to the signals carried on the selected bank data bus, and thus data is incompletely transmitted.

Accordingly, an object of the present invention is to provide a semiconductor memory device in which data signals read from a plurality of banks can be stably transmitted to a shared data bus without interfering with each other.

1 is a diagram for describing a configuration of data busses in a semiconductor memory device having a plurality of banks.

2 is a detailed circuit diagram of a data bus connection unit for a read operation included in a semiconductor memory device according to the related art.

3 is a signal waveform diagram of a semiconductor memory device including a data bus connection unit for a read operation shown in FIG. 2.

4 is a detailed circuit diagram illustrating an embodiment of a data bus connection unit for a read operation included in a semiconductor memory device according to the present invention.

5 is a diagram illustrating a gate enable signal generator according to another exemplary embodiment of the present invention.

FIG. 6 is a signal waveform diagram of a semiconductor memory device including a data bus connection for a read operation shown in FIG. 4.

<Explanation of symbols for main parts of drawing>

210 ... Precharger 220 ... Lighter

250 ... switching part 310 ... gate enable signal generator

In order to achieve the above object, the semiconductor memory device according to the present invention is a semiconductor memory device including a plurality of memory banks, each connected to a corresponding memory bank, each of at least one bank data line and bank inversion data A plurality of bank data buses composed of lines; A shared data bus to which data and inverted data signals applied to or output from the outside of the semiconductor memory device are transmitted and composed of at least one shared data lines and shared inverted data lines; And a plurality of data bus connections for read operations, each connected between the bank data bus and the shared data bus, the read operation being turned on if the corresponding bank is selected and otherwise turned off. It features. In example embodiments, each of the plurality of data bus connection units for a read operation may include a switching unit, and the switching unit may include the plurality of bank data lines / inverted bank data lines and corresponding shared data lines / inverted shared data. A plurality of switching elements connected between the lines and controlled by a gate enable signal activated when a corresponding bank is selected and in a read operation are provided. The switching element may be composed of a PMOS transistor to which the gate enable signal is applied to its own gate. Each of the plurality of read operation data bus connections is further provided with a gate enable signal generator configured to generate an active signal when a bank signal BANKi is active and the read / write split signal PWR indicates a read operation. do. Each of the plurality of read operation data bus connectors may include: a precharger configured to precharge the plurality of bank data lines and the plurality of bank inverted data lines corresponding thereto with a predetermined voltage; And an equalizer for equalizing the plurality of bank data lines and the plurality of bank inverted data lines corresponding thereto.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates a data bus connection unit for a read operation according to the present invention, which is included in the semiconductor memory device as shown in FIG. 1. In FIG. 4, the data bus connection for the read operation includes a precharger 210, an equalizer 220, and a switching unit 250. In FIG. 4, the same parts as in FIG. 2 have the same reference numerals, and description thereof will be omitted.

The switching unit 250 is composed of a plurality of PMOS transistors. The drain-source path of the PMOS transistor 251 is connected between the bank data line IO3 and the shared data line DIO3, and the gate is applied with the output of the NAND gate 320. In the PMOS transistor 252, the drain-source path is connected between the bank inversion data line IO3B and the shared inversion data line DIO3B, and the gate is applied with the output of the NAND gate 320. Thus, when the output of the NAND gate 320 is active to the "low" level, the PMOS transistors 251 and 252 are turned on so that the bank data line IO3 is electrically coupled to the shared data line DIO3. The bank inversion data line IO3B is electrically coupled to the shared inversion data line DIO3B. The remaining PMOS transistors belonging to the switching unit 250 operate in this manner.

The gate enable signal generator 310 includes a plurality of inverters 311, 312, 314, 315, and 316 and a NAND gate 313. The bank select signal BANKi is active at the "high" level when the bank is the bank selected for the data read / write operation, and maintains the non-active state at the "low" level. Therefore, N banks are included in the semiconductor memory device, and there are N different bank select signals BANK1, BANK2, ... BANKN, and only the bank select signal corresponding to the bank accessed therein is "high". Level and the remaining bank select signals remain at the "low" level. The read / write division signal PWR becomes a "high" level in the case of a write operation and a "low" level in the case of a read operation.

The bank select signal BANKi driven by the inverters 311 and 312 is applied to the NAND gate 313. The read / write division signal PWR is also inverted by the inverter 314 and then applied to the NAND gate 313. Thus, the NAND gate 313 is activated to the "low" level only when the bank select signal BANKi is at the "high" level and the read / write division signal PWR is at the "low" level. The output of the NAND gate 313 is driven by the inverters 315 and 316 and output as the gate enable signal PWRD. The gate enable signal PWRD is a signal in which both bank information and read / write information are included therein. The gate enable signal PWRD is activated at a low level only when a corresponding bank is selected and read.

When one bank is composed of only one block, the gate enable signal PWRD may be applied to the gates of the PMOS transistors belonging to the switching unit 250 as they are.

However, when the bank is composed of a plurality of blocks in one as shown in FIG. 1, as shown in FIG. 4, the gate enable signal PWRD is inverted by the inverter 330, and the inverter 330 is inverted. The output and the block select signal BLSij are logically inverted at the NAND gate 320 and applied to the gates of the PMOS transistors belonging to the switching unit 250. Here, the output of the NAND gate 320 outputs a signal that is activated at the "low" level only when the gate enable signal PWRD is at the "low" level and the block select signal BLSij is at the "high" level. Thus, even if controlled by the same block selection signal, the switching unit belonging to the data bus connection unit for the read operation belonging to the different banks is kept in the turn-off state.

Thus, the equalized signals are not delivered to the shared data buses, thereby avoiding the problem as in the prior art.

FIG. 5 illustrates a gate enable signal generator when a semiconductor memory device includes two banks, that is, an A bank and a B bank. In Fig. 5, when the A bank is accessed, the bank select signal BANK_A, which is activated at the "high" level, is buffered by the inverters 411 and 412 and then applied to the NAND gate 413. Likewise, when the B bank is accessed, the bank select signal BANK_B, which is activated to the "high" level, is buffered by the inverters 417 and 418 and then applied to the NAND gate 419. The read / write division signal PWR is inverted by the inverter 416 and then applied to the NAND gates 413 and 419. The output of the NAND gate 413 is at the "low" level only when the A bank is selected and the read / write split signal PWR indicates a read operation (i.e., the "low" level), and the NAND gate 419 The output of is at the "low" level only when the B bank is selected and the read / write split signal PWR indicates a read operation (i.e., a "low" level). The output of NAND gate 413 is buffered by inverters 414 and 415 and the output of NAND gate 419 is buffered by inverters 420 and 421. The gate enable signals PWRD_A and PWRD_B generated as described above are inverted by the inverter 330, respectively, as shown in FIG. 4, and then logic by the NAND gate 320 together with the block selection signal BLSij. The product is inverted.

FIG. 6 is a signal waveform diagram of a semiconductor memory device having a data bus connection for a read operation shown in FIG. 4.

Referring to FIG. 6, a voltage level of a bank data line IO and a bank inverted data line IOB belonging to a selected block of a corresponding bank is converted according to data read from a memory cell. In contrast, bank data lines IO and bank inverted data lines IOB belonging to unselected banks (that is, other banks) are equalized. However, unlike in FIG. 3, the gate enable signal PWRD depends on the bank information.

That is, while the gate enable signal PWRD of the corresponding bank is activated at the "low" level, the gate enable signal PWRD of the other bank maintains the non-active state of the "high" level. Thus, the shared data line DIO and the shared inverted data line DIOB are transmitted only with the signals of the bank data line and the bank inverted data line belonging to the selected bank, and are not affected by the bank data lines belonging to other banks. do.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the present invention transfers data read to a shared data bus commonly used by a plurality of banks in a data read operation so that signals belonging to different bank data buses are competitively loaded on the shared data bus. There is an advantage of preventing malfunctions that may occur by doing so. Thus, there is an effect that the semiconductor memory device operates stably.

Claims (8)

In a semiconductor memory device including a plurality of memory banks, A plurality of bank data buses each connected to a corresponding memory bank, each bank comprising at least one bank data line and bank inverted data lines; A shared data bus to which data and inverted data signals applied to or output from the outside of the semiconductor memory device are transmitted and composed of at least one shared data lines and shared inverted data lines; And A plurality of data bus connections respectively connected between the bank data bus and the shared data bus, each read operation being turned on if the bank is selected and turned off if the bank is selected; A semiconductor memory device. The data bus connection unit of claim 1, wherein each of the plurality of data bus connection units for read operations includes a switching unit. The switching unit is connected between the plurality of bank data lines / inverted bank data lines and the shared data lines / inverted shared data lines corresponding thereto and is activated when the corresponding bank is selected and read. And switching elements of the semiconductor memory device. 3. The semiconductor memory device of claim 2, wherein the switching element comprises a PMOS transistor. 3. The data bus connections of claim 2, wherein the plurality of data bus connections for read operations are respectively And a gate enable signal generator for generating an active signal when the bank signal BANKi is active and the read / write division signal PWR indicates a read operation. The method of claim 4, wherein the gate enable signal generator First and second inverters driving the bank signal; A third inverter for inverting the read / write division signal; A first NAND gate configured to input an output of the second inverter and an output of the third inverter; And And fourth and fifth inverters driving an output of the first NAND gate. 6. The data bus connection of claim 5, wherein A sixth inverter for inverting the output of the fifth inverter; And And a second NAND gate configured to input an output of the sixth inverter and a block select signal BLSij. And the switching unit is controlled based on an output of the second NAND gate. 3. The data bus connections of claim 2, wherein the plurality of data bus connections for read operations are respectively A precharger configured to precharge the plurality of bank data lines and the plurality of bank inverted data lines corresponding thereto with a predetermined voltage; And And an equalizer for equalizing the plurality of bank data lines and the plurality of bank inverted data lines corresponding thereto. The semiconductor memory device of claim 2, wherein the semiconductor memory device includes an A bank and a B bank. First and second inverters for driving the A bank select signal; A third inverter for inverting the read / write operation division signal PWR; Fourth and fifth inverters for driving the B bank select signal; A first NAND gate configured to input an output of the second inverter and an output of the third inverter; Sixth and seventh inverters driving an output of the first NAND gate; A second NAND gate configured to input an output of the fifth inverter and an output of the third inverter; And Eighth and ninth inverters for driving the output of the second NAND gate, And the switching unit of the bank A is controlled in response to the output of the seventh inverter and the switching unit of the bank B is controlled in response to the output of the ninth inverter.