KR100227724B1 - Temporary semiconductor package including high density array external contact - Google Patents

Abstract

The present invention provides a temporary package for a semiconductor die. The temporary package has the same outline and external contact configuration as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can be removed from the package and verified with KGD. The package is identified with base, interconnect and power supply. The package base includes land grid arrays (LGAs) and external contacts formed of dense arrays such as pin grid arrays (PGAs), bump grid arrays (BGAs), or parameter arrays. The package base may be formed of ceramic or plastic together with internal conductive lines using a ceramic lamination process, a 3-D molding process or a Cerdip forming process.

Description

Temporary semiconductor package with dense array external contacts

1 is an exploded perspective view of a package constructed in accordance with the present invention.

2 is a bottom view of a package base showing external contacts formed of a dense grid array.

FIG. 2 (a) is a cross sectional view taken along line 2A-2A of FIG. 2 showing external contacts formed like a land pad array in a land grid array (LGA).

FIG. 2 (b) is a cross sectional view taken along line 2B-2B of FIG. 2 showing external contacts formed like pins in a land grid array (LGA).

FIG. 2 (c) is a cross sectional view taken along line 2C-2C of FIG. 2 showing external contacts formed like bumps in a bump grid array (BGA).

Figure 2 (d) is a cross sectional view according to broken line 2D-2D of Figure 2 showing a laminated ceramic layer of a base for a package.

3 is a cross-sectional view of the assembled package.

FIG. 3 (a) is a cross sectional view of FIG. 3 showing a package implemented differently.

4 is a plan view of an interconnect for the package shown in FIG.

5 is a cross sectional view taken along line 5-5 showing a protruding contact member on an interconnect that electrically contacts the device bond pads on a die.

FIG. 5 (a) is a cross sectional view as in FIG. 5 of an alternatively implemented interconnect with a micro bump contact member.

This application is filed on September 21, 1993, filed on September 21, 1993, filed on September 14, 1993, filed on August 14, 1993, which was filed on September 14, 1993, filed on November 10, 1992, filed on 08 / 124,899. Partial application of application 08 / 345,064, filed November 14, 1994, filed November 14, 1994, part of the application filed on March 1, 1995, filed on March 1, 1995, and Patent No. 5,302,891, filed June 4, 1991 Serial application of abandoned application 07 / 709,858.

This application is filed at 07 / 788,065, filed Nov. 5, 1991, filed 07 / 953,750, filed on September 29, 1992, and filed on June 7, 1993, filed 08 / 073,005, 1993. 08 / 073,003, filed June 7, 08 / 120,628, filed September 13, 1993, 07 / 896,297, filed June 10, 1992, filed February 3, 1994 192,391 and 08 / 137,675, filed October 14, 1993.

[Industrial use]

TECHNICAL FIELD The present invention relates to semiconductor manufacturing, and more particularly, to an improved package for temporarily packaging a semiconductor die for testing and another purpose.

[Traditional Technology and Problems]

Conventionally, packaged semiconductor dice have been tested many times during the manufacturing process. Rigorous testing is performed at the wafer level to test the full functionality of the dice. After singulation of the wafer and packaging of individual dice, full functionality and burn-in tests are performed on each packaged die. Typically, these tests are performed using standardized equipment that provides an electrical interface between the external contacts (eg, terminal leads) and the test circuitry in the package.

For example, burn-in ovens are suitable for maintaining multiple packaged dice in a chamber capable of temperature cycling. During the burn-in test, the integrated circuit is electrically tested at different temperatures. Burn-in boards that can be mounted in the chamber include electrical connectors coupled with external leads to the packaged dice to form electrical interconnections between the individually packaged dice and the test circuitry. For packaged dice with male external contacts, such as external leads formed like pins, the burn-in board includes a socket connector. For packaged dice with a female external lead, the burn-in board includes a pogo pin connector.

Since the semiconductor dice are packaged in a standardized arrangement, the burn-in board is also standardized. For example, a conventional semiconductor package for a single die is known as a small outline j-lead package (SOJ). The burn-in board for the SOJ package includes a standardized socket coupled with the J-lead for the package. In addition, the spacing for the sockets is very tightly spaced in an array so that multiple packages can be mounted on a single board.

In addition, the board to be standardized is associated with an automatic handling device that is standardized for a particular package arrangement. Another standardized package for a single die includes a Dual in-line package (DIP) and a Zigjag in-line package (ZIP).

Recently, semiconductor devices have been provided by manufacturers in unpackaged or exposed configurations. Known good die (KGD) is an unpacked die that is tested to the same quality and reliability level as the packaged product. To identify a die such as KGD, the unpacked die must be burned in. This led to the development of test carriers to maintain unpackaged single die for burn-in and another test. Each test carrier houses a die for testing and also provides electrical interconnection between the die and external test circuitry. Examples of test carriers are disclosed in US Pat. Nos. 5,302,891 and 5,408,190 by Wood et al.

A feature of these carriers is that they require specialized test devices such as specialized burn-in boards and handling devices that are different from the devices used to test conventionally packaged dice. In addition, conventional carriers are larger than conventionally packaged dice and require more and larger test equipment to achieve the same throughput. It is effective in providing test carriers for semiconductor dice that can be used in standardized test equipment.

Another feature of conventional carriers for semiconductor die testing is the limitation that external contacts for the carriers can pinout. Typically, the carrier comprises external contacts formed like pins that engage with corresponding sockets on the burn-in board. This type of external contact configuration is not sufficient external contact to accommodate a die having a plurality of tightly spaced bond pads. In general, the bond pads on the semiconductor dice are spaced smaller and more densely. Thus, it is effective to provide a carrier for semiconductor dice having a dense external contact configuration capable of handling dice with multiple bond pads.

It will be appreciated that the present invention may be comprised of a temporary package with external contacts arranged in a standard outline and a dense array.

[Purpose of invention]

The present invention has been invented in view of the above, and an object thereof is to provide a temporary package for a semiconductor die that can be used for testing and another purpose. It is also an object to provide a temporary package for semiconductor dice with output contacts arranged in dense arrays having a high packing rate. It is also an object of the present invention to provide a temporary semiconductor package having a JEDEC standard outline and a JEDEC standard external contact configuration.

[Configuration and Function of Invention]

The present invention for achieving the above object is provided an improved temporary package for a semiconductor die. The temporary package has an outline and external lead configuration that matches a conventional semiconductor package. In addition, the outer lead is formed of a dense array to accommodate a plurality of device bond pads. Suitable dense arrays and lead configurations for external leads include land grid arrays (LGA), pin grid arrays (PGA), ball grid arrays (BGA), and dense perimeter arrays (dense). perimeter arrays). Standard outline and lead configurations of temporary packages are used during standardized burn-in boards and automated package handling devices during the testing process for KGD.

The temporary package includes a base, an interconnect and a power supply. The package base includes an internal conductor in electrical communication with the external contact. The package base may be formed of ceramic or plastic. In the case of ceramics, the package base may be formed using a ceramic lamination process or a ceramic dip formation (Cerdip) process. In addition, the package base may be formed of plastic using a 3-D injection molding process or a ceramic Cedip process in combination with injection molding.

The interconnects for the package are wire bonded to the conductors mounted on the base and formed on the package base. The interconnect may be formed of a protruding contact member of silicon in electrical communication with the bond pad on the die. The interconnect can also be formed of microbump contact members mounted on a plastic film similar to a two-layer TAB tape.

The force supply for the package includes a press plate, a spring and a cover. The force supply functions to securely secure the die in the base and to retain the interconnect and the die in the electrical contacts. The force supply is secured to the base by a latching mechanism.

The package is assembled by optically aligning the die and the interconnect. Prior to the alignment process, the interconnect is mounted and wire bonded in a package base to form an electrical path between the contact member on the interconnect and an external contact on the package base. The force supply and die of the package during the alignment process can be maintained by the assembly tool. Flip chip optical alignment is used to align the bond pads on the die with the contact members on the interconnects. The assembly tool then attaches a force supply to the package base by placing a die on the interconnect.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 shows an exploded perspective view of a temporary package constructed in accordance with the present invention. The package 10 is suitable for holding a semiconductor die and establishing a temporary electrical connection with the die for testing and burn-in. Following the testing process, the die 12 can be removed from the package 10 and used as a KGD.

Typically, the described package 10 includes a package base 14, interconnects 16 and a force supply 18. Interconnect 16 allows electrical communication between package base 14 and die 12. The force supply 18 securely secures the die 12 to the package base 14 and compresses the die 12 in contact with the interconnect 16. The force supply 18 includes a press plate 20, a spring 22 and a cover 24. The package also includes a latching mechanism in the form of clips 26, 28 (FIG. 3) that securely secures the force supply 18 to the package base 14.

The package base 14 is an external contact 38A formed on the bottom surface 31 (second (c) of the package base 14). 38C (FIG. 2)) includes a pattern of the inner conductor 40 in electrical communication. As described above, the conductor 40 has a die 12 and an external contact 38A. A wire bond is made to the interconnect 16 to provide an electrical path between 38C). The package base 14 also has an external contact 38A to the die 12. An indicator pocket 37 (FIG. 1) that can be used to indicate the direction of 38C) (ie, a pin 1 indicator).

In the package 10 assembled as shown in FIG. 3, the die 12 is held in a recess 36 formed in the package base 14, and the interconnect 16 and cover 24 are retained. Sandwiched between In addition, the interconnect 16 is mounted in a recess 34 formed in the package base 14. Further, in the package 10 assembled as shown in FIG. 3, the crimping plate 20 covers the die 12, and the spring 22 crimps the die 12 in contact with the interconnect 16. The plate 20 is compressed.

In addition, as shown in FIG. 3, the clips 26 and 28 are provided with a base to secure the cover 24, the spring 22, the pressing plate 20, and the die 12 to the package base 14. It is attached to openings 30 and 32 corresponding to 14. The clips 26 and 28 may be formed of a flexible material, such as spring steel or plastic, and are formed to exert a retention force on the cover 24. Moreover, in the assembled package, the cover 24 is recessed below the upper surface of the package base 14. Thus, the outer circumference size and outline of the package 10 is substantially determined by the outer circumference size and outline of the package base 14.

Moreover, the cover 24, the spring 22 and the pressing plate 20 shown in FIG. 3 all have a central opening, denoted 48C, 48S and 48P, respectively. As described above, the openings 48C, 48S, 48P are used during assembly and disassembly of the package 10. In particular, the openings 48C, 48S, 48P are such that the die 12 is held by vacuum means (not shown) during optical alignment of the die 12 and the interconnect 16 during assembly of the package 10. do. In the same way, vacuum means (not shown) can be used to disassemble the package 10.

Package 10 actually has the same standard outline as a conventional semiconductor package. In addition, external contacts 38A 38C) is actually formed at the same standard size and spacing as conventional semiconductor packages. As used herein, a conventional semiconductor package relates to a plastic or ceramic package having an outline and outer lead configuration that conforms to the standards of an approved industry standard setting body. These standard setting bodies

EIA / JEDEC-Association of Electronics Industry-Technical Committee for Electronic Devices

JEIDA-Japan Electronic Industry Development Association

PCMCIA-International Association of Personal Computer Memory Cards

It includes.

Standard outline and lead configurations allow the package 10 to be used in standardized burn-in devices for conventional packages. For example, the standardization apparatus includes an AMBYX _™ intelligent burn-in and test system manufactured by Micron Systems Integration Inc.

External contact 38A for package 10 shown in FIG. 38C is formed in a dense grid pattern on the lower surface 31 of the base 14. As shown in FIG. 2A, the external contact 38A may be in the form of a land pad arranged in a land grid array (LGA). In addition, as shown in FIG. 2B, the external contact 38C may be in the form of a pin arranged in a pin grid array PGA. In addition, as shown in FIG. 2C, the external contact 38C may be in the form of bumps arranged in a bump grid array BGA. In addition, external contacts 38A 38C) may be arranged in a dense perimeter pattern (not shown) rather than a grid pattern.

In each of these cases, the external contact 38A 38C is in electrical communication with an internal conductive line 49 integrally formed with the package base 14. The inner conductive line 49 is in electrical communication with the conductor 40 formed on the package base 14. As shown in FIG. 3, the conductor 40 is bounded at the bond shelf 42 and wire bonded to the interconnect 16 using bond wires 44.

The external contacts 38A of the LAN grid array shown in FIG. 2 (a) may be formed of flat land pads in addition to a suitable metal or stack of metals. For example, the metal may include gold, copper, silver, tungsten, tantalum, platinum, palladium and molybdenum or alloys of these metals. For example, the stack may include a gold layer with nickel underplated. In addition, another stack may include another bond of the metal. Metallization processes, such as plating, can be used to form the outer contact 38A as a flat land pad. Such plating processes may include electrolytic and electroless deposition on metal layers by resist coating, exposure, development and selective wet chemical etching. Typically, the exposed surface of outer contact 38A will be an electroplated metal, such as gold.

For example, the diameter of the outer contact 38A is about 50 500 Can be The distance from the centerline to the centerline of the outer contact 38A is about 50 500 Can be Standard thickness for external contacts 38A is 1.25 100 Can be An external contact 38A is suitable, contacted by a mating electrical connector or another connector in electrical communication with external test circuitry on a burn-in board such as a pogo pin, a solder ball.

As shown in FIG. 2 (b), the outer contact 38B is formed using the same process to be outlined above the outer contact 38A, but is formed with a pin solder or sole process on the flat land pad. As shown in FIG. 2 (c), the outer contact 38C is formed using the same process to be outlined above with respect to the outer contact 38A, but the sole paste screen is placed on the flat land pad. It can be formed with a process that is printed, heated and then reflowed into the ball.

The term " dense grid pattern " as described above means that the contact 38A 38C) relates to a contact pattern in which the density of 38C) increases with the entire area occupied by the contact. This relationship is often expressed in terms of "packing rate." In general, the packing rate of the contact pattern is the area occupied by the contact out of all available areas. For example, 12 inches A contact formed in a grid pattern of 144 per square inch block within a 12 inch area yields a packing rate of 1. A pattern of 144 per 1 inch diameter round contact on 144 grids per inch square yields a packing rate of 0.7854. In fact, a packing rate of close to 1 is not possible because the spacing between the contacts is required to minimize shorting between adjacent contacts. For example, contacts formed like bumps (eg, 38C in FIG. 2C) may require some spacing to prevent shorting during reflow. In general, a "dense grid pattern" has a packing rate of 0.25 or more.

As shown in FIG. 2 (d), the package base 14 is a laminated ceramic layer 41A that is exposed to fire such as alumina (Al ₂ O ₃ ). There may be a multilayer block formed of 41E). Such a process is described in US patent application Ser. No. 08 / 398,309, filed March 1, 1995, which is incorporated herein by reference. In short, this process involves forming a metallized circuit in the x, y and z planes. These circuits are formed on a green sheet of ceramic using a suitable metallization process and are interconnected with the filled metal. The green sheets are pressed together and sintered at high temperature to form a unitary structure. Using this process, conductor 40 and external contacts 38A 38C) may be interconnected by forming internal conductive lines 49 after being formed using a suitable metal. Also, the second (a) External contact 38A as shown in FIG. 2 (c) 38C) may be recessed below the outermost ceramic layer 41E.

In addition, the package base 14 may be formed using a 3-D injection molding process in addition to high temperature glass filled plastics, such as FR-4 material. Such a process is described in US Pat. No. 4,985,116 and embodied in US patent application 08 / 398,309. Suitable plastics include polyetherimide (PEI), polyethersulfone (PES), polyarylsulfone (PAS), polyphenylene sulfide (PPS), liquid crystal polymer (LCP) and polyether-ether ketone (PPEK) . An injection molding process with these or another suitable material can be used to form the package base 14 with the desired rectangle and holes as desired. Conductor 40 and external contacts 38A during the next metallization process Various circuit patterns including 38C) may be formed on the package base 14 and interconnected by forming internal conductive lines 49.

In addition, the package base 14 may be formed using a ceramic quenching (Cerdip) process. In general, for the Cerdip process, the mixing of alumina lubricant and fixer is molded and sintered to form a monolithic package base 14. Next, the metal leadframe is bonded to the package base 14 using low temperature glass to form the conductor 40. External contact (38A 38C) may be part of the lead frame or may be formed respectively. Another form of ceramic quenching process uses a plastic body rather than a ceramic body. In other words, this Cerdip process then preforms the plastic base bonded to the leadframe. Conventional semiconductor packages formed using this process are sold by Pennsylvania, Warren, and GTE Product Corporation under the trademark QUAD-PACK _™ .

3A shows a different package 10A. A differently implemented package 10A actually contains the same elements, as described above for the package 10 indicated by the "A" suffix. However, in the different package 10A, the spring 22A is formed as a flat member, and the pressing plate 20 (FIG. 3) is removed. For example, spring 22A may be a flat metal spring (eg, a wave spring) or may be formed of a resilient material such as a silicone elastomer or a polyimide material.

The cover 24A also includes a recess 50 enclosing the spring 22A and the die 12 in a differently packaged package 10A. The cover 24A abuts the bottom surface of the recess 36A in the package base 14A and is held by a pair of sliding clips 26A and 28A. The sliding clips 26A and 28A are mounted to slide on the base 14a, and are formed in an S-shape so that the holding force is exerted on the cover 24A.

The interconnect 16 for the package 10 shown in FIG. 4 is shown separately. The interconnect 16 includes a bonding pad 56 wire bonded to a conductor 40 formed in the package base 14. The interconnect 16 also includes a conductive trace 58 and a protruding contact member 60. As shown in FIG. 5, the protruding contact member 60 is suitable for contacting to establish electrical connection with the device bond pad 62 or another location on the die 12. As shown in FIG. The protruding contact member 60 also includes a pentrating projection 70 formed like an extended blade suitable for penetrating the device bond pad 62 with a self-limiting penetration depth.

Interconnect 16 and protruding contact member 60 are formed by etching silicon substrate 64. The insulating layer 66 and the conductive layer 68 formed on the substrate 64 cover the protruding contact member 60. The conductive layer 68 is in electrical communication with the conductive trace 58 wire bonded to the bond wire 44. Also, instead of wire bonding, electrical connections are made to the conductive traces 58 by sliding contacts 44S.

As described, suitable processes for actually forming the contact member 60 are disclosed in US Pat. Nos. 5,326,428 and 5,419,807, which are incorporated herein by reference. Another suitable process is disclosed in US patent application Ser. No. 08 / 335,267, filed November 7, 1994, incorporated herein by reference.

In FIG. 5 (a), the interconnect 16 is also formed of the conductive trace 58B and the micro bump contact member 60B formed on the plastic film 72. As shown in FIG. The microbump contact member 60B and the plastic film 72 may be similar to a two layer TAB tape such as ASMAT manufactured by Nitto Denko. The plastic film 72 is mounted on the substrate 64B such as silicon using the flexible adhesive layer 74. The flexible adhesive layer is formed of silicone elastomer, epoxy or polyimide material. A method for forming an interconnect with a microbump contact member is described in US Patent Application Serial No. 08 / 398,309, cited above.

Again, the package 10 shown in FIG. 1 can be assembled using optical alignment techniques and aligner bonder tools used in flip chip bonding semiconductor dice. Flip chip bonding relates to a process for placing a semiconductor die on a substrate lower surface, such as a printed circuit board, where a bond pad is bonded to a connection point on the substrate. Tools for flip chip bonding are often referred to as aligner bonders. Optical alignment methods and aligner bonders for flip chip bonding are described in US Pat. No. 4,899,921 to Bendat et al., Entitled " Aligner Bonder. &Quot; The aligner bonder can be used from the inspection apparatus of Piscataway, N.J.

In the present invention, the aligner bonder is modified to provide an assembly device for use in assembling the package 10. The assembly device includes an assembly tool (not shown) suitable for holding the force supply 18 (FIG. 1), the die 12, and the clips 26, 28 (FIG. 3). The components of the force supply 18 include openings 48C, 48S, 48P that allow a vacuum wand (not shown) of the assembly tool to hold the die 12. In the case of the die held by the assembly tool, the bond pads 62 (FIG. 5) on the die 12 are aligned with the contact members 60 (FIG. 5) on the interconnect 16. As shown in FIG. The assembly tool then positions the die 12 in contact with the interconnect 16 and securely secures the clips 26, 28 (FIG. 3) to the openings 30, 32 of the package base 14. .

U.S. Patent No. 08 / 338,345, filed November 14, 1994, incorporated by reference, provides an optical alignment of die 12 and interconnect 16 and a force supply 18 to package base 14. Describe a suitable automation device to ensure a stable fixation.

Following the assembly process, the package 10 can be used to test the die 16. Testing includes full functionality as well as burn-in testing. Following the test process, the package 10 is dispensed using an assembly tool (not shown) to actually remove the clips 26 and 28 and the force distribution device 18, as described above for the assembly process. Can be.

Claims (26)

An interlock having a base for holding a die, including a plurality of external contacts formed on the surface of the base in a dense array, and mounted on the base, the contact member for electrically contacting a contact position on the die; And an electrical path formed between a connector and a contact member on the interconnect and an external contact on the base. 2. The temporary package of claim 1 wherein the dense array is selected from the group consisting of land grid arrays (LGAs), pin grid arrays (PGAs), ball grid arrays (BGAs), and perimeter arrays. 2. The temporary package of claim 1 wherein the base has an outline and an external contact having a configuration consistent with a conventional semiconductor package conforming to the standards of an approved industry standard setting body. 2. The temporary package of claim 1 wherein the base is formed by a process selected from the group consisting of ceramic lamination, 3-D molding and ceramic quenching. 2. The temporary package of claim 1 wherein the electrical passage comprises a wire bonded conductive trace formed on an interconnect in a conductor formed on the base in electrical communication with an external contact. A base that holds a die and has an internal conductive trace in electrical communication with a pattern of outer contacts formed of a land grid array (LGA) and a dense grid array selected from the group consisting of a pin grid array (PGA) and a ball grid array (BGA). And an interconnect, mountable on the base, the interconnect having a contact member for electrically contacting a contact location on the die, and a conduction formed between the contact member on the interconnect and an external contact on the base. A temporary package for a semiconductor die, comprising a passageway. 7. The temporary package of claim 6 wherein the package base has outline and external contacts having a configuration that substantially matches a conventional semiconductor package conforming to the standards of an approved industry standard setting body. 7. The conductive path of claim 6, wherein the conductive passage forms a conductor on the base in electrical communication with an internal conductive trace and wire bonds the conductor to the conductive trace formed on the interconnect in electrical communication with the contact member. A temporary package for a semiconductor die, characterized in that formed. 7. The temporary package of claim 6 wherein the base is formed using a lamination process in which a green sheet of ceramic material is bonded using a sintering process. 7. The temporary package of claim 6 wherein the base is formed using a 3-D molding process in addition to glass filled plastics. 7. The temporary package of claim 6 wherein the base is formed using a ceramic quenching process. The method of claim 6, wherein the external contact is 50 500 Between 50 and 50 500 A temporary package for a semiconductor die, characterized by a pitch between. 7. The temporary package of claim 6 wherein the external contacts are formed in a dense grid array with a packing rate of at least 0.25. 7. The temporary package of claim 6 wherein the external contact is formed of a flat land pad. 7. The temporary package of claim 6 wherein the external contact is shaped like a pin attached to the flat land pad. 7. The temporary package of claim 6 wherein the outer contact is formed like a solder bump formed on the flat land pads. A package base comprising a die mounted thereon, the package base including a pattern of conductors in electrical communication with a pattern of external contacts formed in a dense grid array, and a pattern of contact members mountable on the base and in electrical communication with the pattern of conductors An interconnect comprising a force supply, a force supply for holding the die in a hole in electrical communication with the interconnect, and a latching device for securely securing the force supply to the base; Temporary package for a semiconductor die, characterized in that the base and the outer contact is formed in a size and shape to match the conventional semiconductor package. 18. The temporary package of claim 17 wherein the dense grid array is selected from the group consisting of a land grid array (LGA), a ball grid array (BGA) and a pin grid array (PGA). 18. The temporary package of claim 17 wherein the interconnect comprises a protruding silicon contact member having an extended through projection formed on a silicon substrate. 18. The temporary package of claim 17 wherein the interconnect comprises a microbump contact member mounted on a substrate using a flexible adhesive layer. 18. The temporary package of claim 17 wherein the package base is formed of a material selected from the group consisting of plastic and ceramic. 18. The temporary package of claim 17 wherein the package base is formed by a process selected from the group consisting of ceramic lamination, 3-D molding, and ceramic immersion (Cerdip). 18. The temporary package of claim 17 wherein the force supply includes a spring and a cover. 18. The temporary package of claim 17 wherein the spring is formed of a carbon polymer material. 18. The temporary package of claim 17 wherein the latching device includes a clip removably attached to the package base. 18. The temporary package of claim 17 wherein the external contacts of the dense grid array have a packing rate of at least 0.25.