KR100213240B1 - Filter with dual input mutual conductance amplifier - Google Patents

Abstract

A filter using a dual input operational cross-conductance amplifier is disclosed. The filter using the dual input operational cross-conductance amplifier includes one or more dual input OTAs, and amplifies the voltage input to the positive input and negative input terminals, and amplifies the signal corresponding to a predetermined resistance value. A first resistor unit for outputting as; A coil generator having one or more dual input OTAs, inputting and amplifying the output of the first resistor unit and outputting the amplified result as a signal corresponding to a predetermined inductance value; A second resistor unit having one or more OTAs, inputting and amplifying the output of the coil generator, and outputting the amplified result as a signal corresponding to a predetermined resistance value; Two capacitors connected between an output of the first resistor unit and a reference power source, respectively; And two capacitors connected between the output of the coil generator and the reference power supply, respectively.

Description

Filter Using Dual Input Operational Interconductance Amplifier

The present invention relates to an Operational Transconductance Amplifier (OTA), and more particularly, to a filter using a dual input OTA constituting a filter using an OTA and a capacitor.

A filter implemented using a transconductance (gm) and capacitance of a MOS transistor is also called a transconductance-C filter or a gm-C filter. FIG. 1 is a circuit diagram of a low pass filter among gm-C filters.

Figure 1 (a) is a typical low pass filter implemented with a resistor, a coil and a capacitor, Figure 1 (b) is a gm-C filter implemented with a conventional OTA the filter shown in (a).

FIG. 1 (a) illustrates a typical third-order low pass filter including a first resistor R1 connected to an input voltage Vin and a first node, a first capacitor C1 connected between a first node, and a reference power source. A coil L connected to a resistor connected between the node and the second node, a second capacitor C2 connected between the second node and the reference power supply, and a second resistor R2 connected between the second node and the reference power supply GND. It consists of.

FIG. 1 (b) is a circuit diagram of a gm-C filter implementing the filter shown in FIG. 1 (a) using a conventional OTA. The first OTA 24 constituting the first resistor R1 20, Capacitors C11 and C12 having the same capacitance as the second OTA 26, the first capacitor C1, capacitors C21 and C22 having the same capacitance as the second capacitor C2, and the coil L 40. The third, fourth, fifth and sixth OTA (42, 44, 46 and 48), the two capacitors (C31, C32), and the seventh OTA forming the second resistor (R2) (80) .

FIG. 1B is an equivalent implementation of the conventional low pass filter shown in FIG. 1A having one input terminal and one output terminal using an OTA having two input terminals and two output terminals. It is. The first OTA 24 shown in FIG. 1 (b) is composed of two OTAs having a mutual conductance gm, that is, 2 * gm, to compensate for the power of the input signal, respectively, the positive input terminal VIN + and the negative input terminal. The signal input through VIN- is amplified, and the amplified signal is output to the positive output terminal and the sub output terminal, respectively. The output voltage is input to the positive input terminal and the negative input terminal of the second OTA 26. The signal output through the positive output and the negative output terminals of the second OTA 26 is blocked by the high frequency components by the capacitors C11 and C12.

The fourth OTA 44 constituting the coil (L) 40 receives the output of the second OTA 26 and outputs it to the third OTA 42 and the six OTA 48, and the output of the third OTA 42 is fed back. It is input to the fourth OTA 44. Similarly, the output of the sixth OTA 48 is fed back to the fifth OTA 46. In addition, the high frequency component is cut off by the capacitors C31 and C32 having the same capacitance as that of the third capacitor C3. Here, the currents of the third and fourth nodes constituting the coil (L) 40 are the currents of the fourth OTA 44 when the output currents of the fourth OTA 44 and the fifth OTA 46 are I, respectively. And the currents of the fifth OTA 46 become 2I.

Therefore, in the gm-C filter using the conventional OTA, voltages applied to the nodes N1 to N6 are not constant, and voltages applied to the third and fourth nodes N3 and N4 are equal to the first, second nodes, and the first. There is a problem that the voltage becomes higher than the voltage of the fifth and sixth nodes. In addition, when implementing a gm-C (mutual conductance) filter with a completely differential structure, a direct current in which the DC level of the positive output terminal and the sub output terminal of the filter are different from each other due to layout problems or other reasons. There is a problem that an offset (DC OFFSET) occurs.

An object of the present invention is to provide a filter using a dual input OTA in which the input terminal of the OTA is doubled and an input terminal for applying an offset removing voltage is added.

1 (a) is a filter implemented with a resistor, a coil and a capacitor, 1 (b) is a circuit diagram for explaining a filter using a conventional OTA.

FIG. 2 is a circuit diagram illustrating a scaled filter using the OTA shown in FIG. 1.

3 is a circuit diagram of one preferred embodiment of a filter using a dual input OTA according to the present invention.

FIG. 4 is a circuit diagram illustrating an OTA of a filter using the dual input OTA shown in FIG. 3.

FIG. 5 is a waveform diagram illustrating an output of a filter using the dual input OTA illustrated in FIG. 3.

In order to achieve the above object, the filter using the dual input OTA according to the present invention includes at least one dual input OTA, amplifies the voltage input to the positive input and the negative input terminals, and amplifies the amplified result to a predetermined resistance value. A first resistor unit outputting a signal corresponding to the first resistor unit; A coil generator having one or more dual input OTAs, inputting and amplifying the output of the first resistor unit and outputting the amplified result as a signal corresponding to a predetermined inductance value; A second resistor unit having one or more OTAs, inputting and amplifying the output of the coil generator, and outputting the amplified result as a signal corresponding to a predetermined resistance value; Two capacitors connected between an output of the first resistor unit and a reference power source, respectively; And two capacitors connected between the output of the coil generator and the reference power source, respectively.

Hereinafter, a filter using a dual input OTA according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of a scaled gm-C filter using the conventional OTA shown in FIG. 1B, and includes a first resistor unit R1, capacitors C11 and C12, and a coil generator L ) 40, the capacitors C31 and C32, and the second resistor unit 80, wherein the first resistor unit 20 includes the first OTAs 242 and 244 and the second OTA 26. The capacitors C21 and C22 are formed of capacitors C21A and C21B and capacitors C22A and C22B, respectively, and the coil generator 40 includes OTAs 424 and 426 and a fourth OTA forming a third OTA. 44, OTAs 484 and 486 constituting the fifth OTA 46 and the sixth OTA.

The filter using the dual input OTA according to the present invention, in order to equalize the voltage applied to each node (N1 ~ N6) of the filter using the conventional OTA as described above, and to minimize the peak voltage (PEAK) A portion of the coil generator 40 is divided by applying a scaling rule. That is, the gyrator portion of the coil is scaled to form a parallel form of an OTA having a single gm, and the transformation is performed while maintaining the transfer function of the filter.

That is, the third OTA 42 constituting the coil generator L 40 is divided into two OTAs 424 and 426, and the sixth OTA 48 is divided into OTAs 484 and 486. Here, in the coil generator L 40 illustrated in FIG. 1, the relationship between the conductance value gm and the capacitance and inductance of the capacitor C2 may be expressed by the following equation.

[Equation 1]

C = gm ² * L

Where C denotes the capacitance value of the capacitor C21 or C22, gm denotes the mutual conductance value of the OTAs 42, 44, 46 or 48, and L denotes the inductance value of the coil. In order to obtain the L value, Equation 1 is again displayed.

[Equation 2]

L =

That is, the third OTA 42 and the sixth OTA 48 of the coil generator 40 are divided into two OTAs 424, 426, 484, and 486, respectively, and capacitors C21 having the same capacitance as the second capacitor C2. , C22) is divided into C21A, C21B and C22A, C22B, respectively. Therefore, when the scaling rule is applied, since the amount of current flowing through the third and fourth nodes is reduced, the voltage of the node may be reduced and the peak voltages of the first to sixth nodes may be balanced to some extent.

However, when the scaling rule is applied in the above manner, as shown in FIG. 2, the number of OTAs is increased, so that each OTA input terminal has two positive input terminals and two negative inputs to reduce the number of OTAs used. In other words, it is configured as a dual input (Dual Input) to configure a single dual OTA (DOTA).

That is, in FIG. 2, the input terminals are different from each other, and the output terminals are connected to each other with the same OTA.

FIG. 3 is a circuit diagram of a preferred embodiment of a filter using a dual input OTA according to the present invention. OTA and capacitor constituting the 450, the fourth DOTA 460, the OTAs 424 and 484, the coil generator 40 including the capacitors C21A, C21B, C22A, and C22B, and the second resistor unit 80. (C11, C12) and capacitors (C31, C32).

FIG. 4 is a detailed circuit diagram of the dual input OTA illustrated in FIG. 3. The first transistor M1 and the first bias voltage having a gate connected to the control signal CMFB, a supply power source, and a source and a drain connected to the first node. A first amplifier 52 which inputs the voltage of BS1 and the first node and outputs the amplified voltage, a gate connected to the output of the first amplifier 52, a source connected to the first node and the output terminal, The second amplifier M2 having the drain, the second bias voltage BS2 and the outputs of the second amplifier 56 and the second amplifier 56 which input and output the voltages of the second node as amplified voltages; A third transistor M3 having a gate and a source and a drain connected to the second node and the constant output terminal, a drain and a source connected to the second node and the reference power supply GND, and a gate connected to the first positive input terminal; A drain and a source connected to the fourth transistor M4, the second node, and the reference power source; A fifth transistor M5 having a gate connected to the second positive input terminal, a gate connected to the control signal CMFB, a sixth transistor M6 having a source and a drain connected to the supply power source and the first node, and a first bias; A source connected to the third amplifier 54 and a gate connected to the output of the third amplifier 54 for inputting and outputting the voltage BS1 and the voltage of the third node as an amplified voltage, and a source connected to the third node and the output terminal. And an output of the fourth amplifier 58 and the fourth amplifier 58 which input the seventh transistor M7 having the drain, the second bias voltage BS2 and the voltage of the fourth node, and output them as an amplified voltage. An eighth transistor M8 having a gate connected to the fourth node and a source and a drain connected to the fourth node and a negative output terminal, a drain and a source connected to the fourth node and the reference power source, and a ninth having a gate connected to the first sub-input terminal A drain and a source connected to the transistor M9, the second node, and the reference power source; The first and third amplifiers 52 and 54 have the same voltage amplification degree A1, and the second and fourth amplifiers 56 and 58 has the same voltage amplification degree A2.

As shown in FIG. 4, the signal input through the input terminal VIN + in the first OTA 24 divided into two OTAs 242 and 244 is connected to the first and second positive input terminals of the first DOTA 250 ( Signals commonly input through V1 + and V2 + are input through the first and second sub-input terminals V1 and V2- of the first DOTA 250, respectively. In addition, the OTAs 44 and 46 having different inputs and the same outputs are configured as one dual input OTA, that is, the second DOTA 430. Here, the OTAs 26 and 424 with different inputs and the same output shown in FIG. 3 can be configured as one DOTA, and similarly, the OTAs 484 and 80 can be configured as one DOTA. Do. In addition, the third DOTA 426 applies an offset removing voltage by using an extra input terminal, that is, a second positive input and a second sub-input terminal.

That is, as shown in FIG. 3, the offset removing voltage V _OFFSET is applied to the second positive input terminal V2 + of the third DOTA 450, and the in-phase voltage V is applied to the second sub-input terminal V2-. _CM ) can be applied to remove the offset voltage appearing at the output of the filter. Also in the case of the fourth DOTA 436 of FIG. 3, the in-phase voltage V _CM is commonly applied to the extra input terminals V2 + and V 2-to stabilize the filter output.

Referring to FIG. 4, the DOTA of the third DOTA 450 illustrated in FIG. 3 will be described in detail. The supply power source VDD represents a driving power source for driving the OTAs and is input to the gates of the transistors M1 and M6. Power is supplied or cut off by the control signal CMFB (COMMON FEEDBACK). When the power is supplied, the first amplifier 52 amplifies the first bias voltage BS1 and the drain voltage of the first transistor, that is, the voltage of the first node, and amplifies the second transistor M2. Is applied to the gate of. In addition, the second amplifier 56 amplifies the voltage of the second bias voltage BS2 and the second node input through the positive input and negative input terminals, respectively, and the amplified signal is a gate of the third transistor M3. Is applied to. The PMOS transistor M2 and the NMOS transistor M3 driven according to the output voltages of the first amplifier 52 and the second amplifier 54 operate as a resistor. The voltage input through the positive input terminals V1 + and V2 + is amplified corresponding to the divided resistance values of M2 and M3 acting as resistors, and the amplified signal is output through the output terminal VO +. Similarly, when the power supply voltage is supplied by the control signal CMFB, the third amplifier 52 receives the drain voltage of the first bias voltage BS1 and the sixth transistor M6, that is, the voltage of the first node N3. Is inputted and amplified, and the amplified signal is applied to the gate of the seventh transistor M7. In addition, the fourth amplifier 58 amplifies the voltage of the second bias voltage BS2 and the third node input through the positive input and negative input terminals, respectively, and the amplified signal is a gate of the third transistor M3. Is applied to. The PMOS transistor M7 and the NMOS transistor M8 driven according to the output voltages of the third amplifier 54 and the second amplifier 58 operate as a resistor, and the voltage input through the negative input terminal VIN1- Amplified corresponding to the divided resistance values of M7 and M8 acting as a resistor, the amplified signal is output through the output terminal VO-.

Herein, when an offset voltage having different DC levels of output voltages of the positive output terminal and the sub output terminal is generated due to the characteristics of the transistors or the amplifier part used, the offset is removed from the second positive input terminal shown in FIG. 4. By applying a voltage and applying an in-phase voltage (V _CM ) and a voltage of approximately VDD / 2 to the second sub-input terminal, a stable output from which the offset voltage is removed can be obtained. If the DOTA illustrated in FIG. 4 is the fourth DOTA 460, the amount of current flowing to each node by applying the V _CM voltage in common using an extra input terminal, that is, the second positive input terminal and the second sub-input terminal. Constant so that the DC levels of the output signals are constant with each other. However, applying the offset removal voltage or the in-phase voltage V _CM may be flexibly changed depending on the design, or the positions of the input terminals thereof may be changed.

5 (a) and 5 (b) are examples of simulating the output of a filter using the dual input OTA according to the present invention, where (a) is a case of applying an offset elimination voltage of about 1.6 V, and (b) is about This is a simulation example for comparing the DC level of the output signal when applying an offset elimination voltage of 1.7V.

FIG. 5 illustrates a case where there is a slight difference in DC level by applying an offset elimination voltage. Consequently, if an offset elimination voltage inputted correctly through the input terminal shown in FIG. 4 is correctly inputted, a DC level between two outputs is corrected. You get the output of the filter with no difference.

As described above, the filter using the dual input OTA according to the present invention can not only reduce the number of OTAs required. Not only can the offset voltage be removed by applying the offset removal voltage at the input of the filter, but the voltage can also reduce the generation of noise on the output.

Claims (7)

A first resistor having at least one dual input OTA, amplifying a voltage input to the positive input and negative input terminals and outputting the amplified result as a signal corresponding to a predetermined resistance value; A coil generator having one or more dual input OTAs, inputting and amplifying the output of the first resistor unit, and outputting the amplified result as a signal corresponding to a predetermined inductance value; A second resistor unit having one or more OTAs, inputting and amplifying the output of the coil generator, and outputting the amplified result as a signal corresponding to a predetermined resistance value; Two capacitors connected between an output of the first resistor unit and a reference power source, respectively; And And a two input capacitor connected between an output of the coil generator and a reference power supply, respectively. The method of claim 1, wherein the first resistor unit, A first amplifying the positive input voltage commonly input to the first positive input terminal and the second positive input terminal and the negative input voltage commonly input to the first sub input and the second sub input terminal and outputting the amplified signal; Dual input OTA; And And a first OTA for inputting and amplifying the negative output and the positive output of the first dual input OTA to the positive input terminal and the negative input terminal, respectively, and outputting the amplified voltage. . The method of claim 1, wherein the coil generator, A second dual input OTA having a first positive input and a first sub input terminal connected to the first node and a second node, and a second positive input and second sub input terminal connected to the sixth node and the fifth node; A third dual input OTA having a first positive input and a first sub input terminal connected to the fourth node and a third node, and a second positive input and second sub input terminals; A fourth dual input OTA having first positive input and first sub input terminals connected to the third node and fourth node, and a second positive input and second sub input terminals; A second OTA having a positive input terminal and a negative input terminal connected to the fourth node and the third node; A third OTA having positive input and negative input terminals connected to the third and fourth nodes; Two capacitors connected between the third node and the reference power supply; And And a two capacitor connected between the fourth node and the reference power supply. The method of claim 3, wherein the first resistor unit, A first amplifying the positive input voltage commonly input to the first positive input terminal and the second positive input terminal and the negative input voltage commonly input to the first sub input and the second sub input terminal and outputting the amplified signal; Dual input OTA; And And a first OTA for inputting and amplifying the negative output and the positive output of the first dual input OTA to the positive input terminal and the negative input terminal, respectively, and outputting the amplified voltage to the second dual input OTA. Filter using mutual conductance amplifier. 5. The filter of claim 4, wherein the first OTA and the second OTA constitute one dual input OTA. The method of claim 3, wherein the third dual input OTA, A filter using a dual input operational mutual conductance amplifier, wherein the voltage input to the second positive input terminal or the second sub input terminal is an offset cancellation voltage. The method of claim 3, wherein the fourth dual input OTA, A filter using a dual input operational cross-conductance amplifier, characterized in that the voltage commonly applied to the second positive input and the second sub-input terminals is in phase voltage.

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