KR100216866B1 - Ferroelectric ram for preventing leakage currents and its manufacturing method - Google Patents
Ferroelectric ram for preventing leakage currents and its manufacturing method Download PDFInfo
- Publication number
- KR100216866B1 KR100216866B1 KR1019960017529A KR19960017529A KR100216866B1 KR 100216866 B1 KR100216866 B1 KR 100216866B1 KR 1019960017529 A KR1019960017529 A KR 1019960017529A KR 19960017529 A KR19960017529 A KR 19960017529A KR 100216866 B1 KR100216866 B1 KR 100216866B1
- Authority
- KR
- South Korea
- Prior art keywords
- barrier layer
- ferroelectric
- opening
- forming
- ferroelectric capacitor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 69
- 230000004888 barrier function Effects 0.000 claims abstract description 46
- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 239000002131 composite material Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- -1 oxygen ions Chemical class 0.000 claims 4
- 235000014653 Carica parviflora Nutrition 0.000 claims 1
- 241000243321 Cnidaria Species 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 8
- 229910010413 TiO 2 Inorganic materials 0.000 description 7
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000035515 penetration Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000003609 titanium compounds Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
강유전체 캐패시터를 구비한 강유전체 램 및 그 제조방법에 관한 것이다.A ferroelectric ram having a ferroelectric capacitor and a method of manufacturing the same.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
누설전류를 방지하기 위한 강유전체 램 및 그 제조방법을 제공함에 있다.The present invention provides a ferroelectric ram and a method of manufacturing the same to prevent leakage current.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
기판상에 형성되고, 상부전극 및 하부전극 사이에 강유전성 물질이 형성되어 있는 강유전체 캐패시터를 적어도 하나 이상을 포함하는 강유전체 램 제조방법에 있어서 : 상기 강유전체 캐패시터에 발생하는 누설전류를 방지하기 위하여, 그 강유전체 캐패시터 전면에 복합 배리어층을 형성하는 단계와 ; 상기 복합 배리어층 상부에 층간절연막을 형성한 뒤, 이를 식각하여 상기 상부전극 및 하부전극의 일부 상부가 노출되는 개구부를 형성하는 단계와 ; 상기 개구부의 측벽에 절연막을 이용하여 스페이서를 형성한 뒤, 상기 개구부에 도전막을 형성하여 콘택을 형성하는 단계를 구비함을 요지로 한다.A method of manufacturing a ferroelectric ram comprising at least one ferroelectric capacitor formed on a substrate and having a ferroelectric material formed between an upper electrode and a lower electrode, in order to prevent leakage current occurring in the ferroelectric capacitor. Forming a composite barrier layer on the entire surface of the capacitor; Forming an interlayer insulating layer on the composite barrier layer and etching the same to form an opening through which a portion of the upper electrode and the lower electrode are exposed; After forming a spacer using an insulating film on the sidewall of the opening, a conductive film is formed in the opening to form a contact.
4. 발명의 중요한 용도4. Important uses of the invention
누설전류를 방지하기 위한 강유전체 램 및 그 제조방법에 적합하다.It is suitable for ferroelectric ram and its manufacturing method for preventing leakage current.
Description
제1도는 종래 기술에 따라 제조된 강유전체 캐패시터의 단면도이다.1 is a cross-sectional view of a ferroelectric capacitor manufactured according to the prior art.
제2도는 본 발명의 실시예에 따라 제조된 강유전체 캐패시터의 단면도이다.2 is a cross-sectional view of a ferroelectric capacitor manufactured according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
2 : 하부전극 4 : 강유전체층2: lower electrode 4: ferroelectric layer
6 : 상부전극 8 : 배리어층6: upper electrode 8: barrier layer
10 : 산화막 배리어층 12 : 확산 배리어층10 oxide film barrier layer 12 diffusion barrier layer
14 : 충간절연막 16 : 절연막 스페이서14 interlayer insulating film 16 insulating film spacer
18a, 18b : 콘택 ①, ② : 누설전류 흐름방향18a, 18b: Contact ①, ②: Leakage current flow direction
본 발명은 불휘발성 반도체 메모리 장치에 관한 것으로서, 특히 강유전체 캐피시터를 구비한 강유전체 램 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a ferroelectric ram having a ferroelectric capacitor and a method of manufacturing the same.
통상적으로, 강유전체 캐패시터를 이용하는 반도체 메모리 장치는 불휘발 특성을 가진다. 그 불휘발성 반도체 메모리 장치는 표준 램셀로 구성되며, 두 개의 메탈 전극에 강유전성 물질(PZT)이 샌드위치된 작은 배터리를 가진다. 최근에, NEC는 1MBIt로 가장 큰 메모리 용량의 칩을 상기한 강유전체 캐패시터를 이용하여 시작(試作)하였다. 그 불휘발성 반도체 메모리 장치의 메모리 셀은 1개의 모오스 전계효과 트랜지스터와 1개의 강유전체 캐패시터로 구성한다. 따라서, 그 강유전체 캐패시터 분극방향의 차이를 전하로서 리이드한다. 상술한 형태의 불휘발성 반도체 메모리 장치에 대한 구조 설명은 발명자 Kazuhiro Hoshiba에 의해 1993년 2월 23일자로 특허 허여된 미합중국 특허 U.S.P. No. 5,189,594하에 제목 capacitor in a semiconductor intergrated circuit and non-volatile memory using same에 자세히 개시되어 있다.Typically, semiconductor memory devices using ferroelectric capacitors have nonvolatile properties. The nonvolatile semiconductor memory device is composed of standard ram cells and has a small battery in which ferroelectric material (PZT) is sandwiched between two metal electrodes. Recently, NEC has started a chip with the largest memory capacity of 1MBIt using the above ferroelectric capacitor. The memory cell of the nonvolatile semiconductor memory device is composed of one MOS field effect transistor and one ferroelectric capacitor. Therefore, the difference in the ferroelectric capacitor polarization direction is read as a charge. The structure description of the above-described nonvolatile semiconductor memory device is described in US Patent U.S.P., issued February 23, 1993, by inventor Kazuhiro Hoshiba. No. 5,189,594 is described in detail in the heading capacitor in a semiconductor intergrated circuit and non-volatile memory using same.
제1도는 종래 기술에 따라 제조된 강유전체 캐패시터의 단면도로서, 상기 강유전체 캐패시터에서 발생하는 누설전류의 흐름방향이 도시되어 있다.1 is a cross-sectional view of a ferroelectric capacitor manufactured according to the prior art, in which the flow direction of leakage current generated in the ferroelectric capacitor is shown.
제1도를 참조하면, 강유전체 캐패시터는 일반적으로 하부전극(bottom electrode)(2), 강유전체층(ferroelectric layer)(4) 그리고 상부전극(top electrode)(6)으로 이루어진다. 이때, 상기 상부전극(6)은 플래티늄(platinum), 티타늄(titanium), 알루미늄(aluminum) 물질층으로 다시 세분화되고, 하부전극(2)는 플래티늄, 티타늄 나이트라이드(titanium nitride), 티타늄의 물질층으로 세분화된다. 이와 같은 구성은 발명자 William L. Larson에 의해 1991년 4월 2질자로 특허 허여된 미합중국 특허 U.S.P. No. 5,005,102하에 제목 multilayer electrodes for integrated circuit capacitors에 개시된 내용이다.Referring to FIG. 1, a ferroelectric capacitor generally consists of a bottom electrode 2, a ferroelectric layer 4, and a top electrode 6. As shown in FIG. In this case, the upper electrode 6 is further subdivided into a layer of platinum, titanium, and aluminum, and the lower electrode 2 is formed of a material layer of platinum, titanium nitride, or titanium. Broken down into. Such a configuration is described in US Patent U.S.P. Pat. No. 5,005,102, which is disclosed in the title multilayer electrodes for integrated circuit capacitors.
한편, 상기 강유전체 캐패시터 완성후 반도체 기판의 단차를 완화시키기 위해서 층간절연막을 증착하게 되는데, 이처럼 증착에 의해 층간절연막일 형성할 경우 층간절연막 내부의 수소 원자들이 상기 강유전체층(4)으로 침투하여 캐패시터의 특성을 변화시키게 된다.Meanwhile, after completion of the ferroelectric capacitor, an interlayer insulating film is deposited to alleviate the step difference of the semiconductor substrate. Thus, when the interlayer insulating film is formed by the deposition, hydrogen atoms inside the interlayer insulating film penetrate into the ferroelectric layer 4 to form the interlayer insulating film. It will change its characteristics.
따라서, 본 분야에서는 수소 원자의 침투를 막기 위한 베리어막(8)으로서 TiO2막을 적용하게 되었으며, 이러한 TiO2막을 적용함으로써 캐패시터의 특성이 변화되는 것을 방지할 수 있었다. 그러나, 상기 TiO2막 형성과정으로 살펴보면, 상기 강유전체층(4)을 이루고 있는 강유전체 물질층에 영향을 미치지 않기 위해서 티타늄을 먼저 스퍼터링 증착한 후에 비교적 낮은 온도, 통상적으로 약 600℃이하의 저온하에서 산화공정을 실시하여 TiO2막을 형성하여야 한다. 따라서, 상기 TiO2막은 수소 원자의 침투를 막는데에는 유리하나 완전하게 산화되지 못하여 약한 도전성을 띠고 있다. 그러므로, 후속의 공정에서 상기 하부전극(2)과 상부전극(6) 상에 콘택을 형성할 경우 상기 도전성을 띠는 TiO2막으로 인하여 도시된 것과 같이, 상부전극(6)에서 하부전극(2)방향으로의 누설전류 ①이 흐르게 되며, 캐패시터 내부에서도 누설전류 ②가 흐르게 된다. 이러한 누설전류는 강유전체 캐패시터의 값을 변화시키고 강유전체층으로 이루고 있는 강유전 물질의 분극량을 변화시키게 되므로 반도체 장치에 바람직하지 못한 영향을 미치게 된다.Therefore, in this field, the TiO 2 film was applied as the barrier film 8 for preventing the penetration of hydrogen atoms, and by applying such TiO 2 film, it was possible to prevent the characteristics of the capacitor from being changed. However, in the process of forming the TiO 2 film, in order not to affect the ferroelectric material layer constituting the ferroelectric layer 4, titanium is first sputter deposited and then oxidized at a relatively low temperature, typically about 600 ° C. or less. The process should be carried out to form a TiO 2 film. Therefore, the TiO 2 film is advantageous in preventing penetration of hydrogen atoms, but has a weak conductivity because it is not completely oxidized. Therefore, when a contact is formed on the lower electrode 2 and the upper electrode 6 in a subsequent process, as shown by the conductive TiO 2 film, the lower electrode 2 at the upper electrode 6 is shown. Leakage current ① flows in the) direction, and leakage current ② also flows inside the capacitor. This leakage current has an undesirable effect on the semiconductor device because it changes the value of the ferroelectric capacitor and the polarization amount of the ferroelectric material of the ferroelectric layer.
따라서, 상기한 종래의 문제점을 해소하기 위한 본 발명의 목적은 강유전체 캐패시터 내부 및 주변에 흐르는 누설전류를 방지하기 위한 강유전체 램 및 그 제조방법을 제공함에 있다.Accordingly, an object of the present invention for solving the above-described problems is to provide a ferroelectric ram and a method of manufacturing the same to prevent leakage current flowing in and around the ferroelectric capacitor.
본 발명의 다른 목적은, 안정된 동작을 수행하는 강유전체 캐패시터를 가지는 강유전체 램 및 그 제조방법을 제공함에 있다.Another object of the present invention is to provide a ferroelectric ram having a ferroelectric capacitor which performs a stable operation, and a method of manufacturing the same.
상기한 목적들을 달성하기 위하여 본 발명에서는, 기판상에 형성되고, 상부 전극 및 하부전극 사이에 강유전성 물질이 형성되어 있는 강유전체 캐패시터를 적어도 하나 이상을 포함하는 강유전체 램 제조방법에 있어서 ; 상기 강유전체 캐패시터에 발생하는 누설전류를 방지하기 위하여, 그 강유전체 캐패시터 전면에 복합 배리어층을 형성하는 단계와 ; 상기 복합 배리어층 상부에 중간 절연막을 형성한 뒤, 이를 식각하여 상기 상부전극 및 하부전극의 일부상부가 노출되는 개구부를 형성하는 단계와 ; 상기 개구부의 측벽에 절연막을 이용하여 스페이서를 형성한 뒤, 상기 개구부에 도전막을 형성하여 콘택을 형성하는 단계를 포함함을 특징으로 하는 강유전체 램 제조방법을 제공한다.In the present invention to achieve the above objects, in the ferroelectric ram manufacturing method comprising at least one ferroelectric capacitor formed on the substrate, the ferroelectric material is formed between the upper electrode and the lower electrode; Forming a composite barrier layer on the entire surface of the ferroelectric capacitor to prevent leakage current generated in the ferroelectric capacitor; Forming an intermediate insulating layer on the complex barrier layer and etching the same to form an opening through which a portion of the upper electrode and the lower electrode is exposed; And forming a contact by forming a spacer on the sidewall of the opening by using an insulating layer and then forming a conductive film on the opening.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
제2도는 본 발명의 실시예에 따라 제조된 강유전체 캐패시터의 단면도이다.2 is a cross-sectional view of a ferroelectric capacitor manufactured according to an embodiment of the present invention.
도면을 참조하면, 제1도에서와 같이 상부전극(6)과 하부전극(2), 그리고 상기 상부전극(6)과 하부전극(2) 사이에 강유전성 물질로 이루어진 강유전체충(4)을 형성하여 강유전체 캐패시터를 완성한다. 그리고 상기 강유전체 캐패시터 상부에 종래와는 달리 산화막 배리어층(10) 및 확산 배리어층(12)으로 이루어져 있는 복합 배리어층을 형성한다. 여기서, 상기 산화막 배리어층(10)은 수소 원자를 함유하지 않도록 산소 이온 스퍼터링 방식을 이용하여 상기 강유전체 캐패시터 전면에 약 20Å~1000Å 두께로 형성하며, 상기 확산 배리어층(12)과 강유전체 캐패시터 사이에 형성되어 강유전체 캐패시터 내부 및 주변으로 누설전류가 흐르는 것을 방지하는 기능을 수행한다. 그리고 상기 확산 배리어층(12)은 티타늄 화합물, 예컨대 TiO2막으로서 후속의 공정을 통해 형성되어질 층간절연막(14) 내부의 수소 원자들이 강유전체 캐패시터로 침투하여 상기 강유전체층(4)과 반응하는 것을 방지하는 기능을 수행한다. 이때, 상기 확산 배리어층(12)은 온도에 민감한 상기 강유전체층(4)에 악영향을 미치지 않도록 하기 위해, 약 600℃이하의 저온하에서 산화공정을 실시하여 약 50Å-~1000Å 두께로 형성하는 것이 바람직하다.Referring to the drawings, as shown in FIG. 1, a ferroelectric charge 4 made of a ferroelectric material is formed between the upper electrode 6 and the lower electrode 2 and between the upper electrode 6 and the lower electrode 2 Complete the ferroelectric capacitor. Unlike the related art, a complex barrier layer including an oxide barrier layer 10 and a diffusion barrier layer 12 is formed on the ferroelectric capacitor. Here, the oxide barrier layer 10 is formed to a thickness of about 20 kPa to 1000 kPa on the entire surface of the ferroelectric capacitor by using an oxygen ion sputtering method so as not to contain hydrogen atoms, and is formed between the diffusion barrier layer 12 and the ferroelectric capacitor. To prevent leakage current from flowing into and around the ferroelectric capacitor. The diffusion barrier layer 12 is a titanium compound, such as a TiO 2 film, to prevent hydrogen atoms in the interlayer insulating film 14 to be formed through a subsequent process to penetrate into the ferroelectric capacitor to react with the ferroelectric layer 4. It performs the function. In this case, the diffusion barrier layer 12 is preferably formed to have a thickness of about 50 kPa to 1000 kPa by performing an oxidation process under a low temperature of about 600 ° C. or less so as not to adversely affect the ferroelectric layer 4 which is sensitive to temperature. Do.
이어서, 상기 확산 배리어층(12)이 형성되어 있는 결과물을 평탄화시키기 위해 단차도포성이 양호한 층간절연막(14)을 증착한 뒤, 사진 및 식각공정을 실시하여 콘택을 형성하고자 하는 소정영역에 콘택홀을 형성한다. 그리고 나서, 상기 콘택홀 및 층간절연막(14) 상부에 산소 이온 스퍼터링 방식으로 절연막을 형성한 뒤, 이를 전면 에치백하여 콘택홀 하부만을 노출시키는 절연막 스페이서(16)를 형성한다. 이어서, 상기 절연막 스페이서(16)가 형성되어 있는 결과물의 상부에 도전물, 예컨대 금속물을 증착한 후에 이를 패터닝하여 상부전극(6) 및 하부전극(4) 각각에 상부전극용 콘택(18a) 및 하부전극용 콘택(18b)을 형성한다.Subsequently, in order to planarize the resultant on which the diffusion barrier layer 12 is formed, the interlayer insulating film 14 having a high level coating property is deposited, and then a contact hole is formed in a predetermined region to form a contact by performing a photo and etching process. To form. Then, an insulating film is formed on the contact hole and the interlayer insulating film 14 by an oxygen ion sputtering method, and then the entire surface is etched back to form an insulating film spacer 16 exposing only the contact hole lower portion. Subsequently, a conductive material, for example, a metal material is deposited on the resultant on which the insulating film spacer 16 is formed, and then patterned to form a contact 18a for the upper electrode and the upper electrode 6 and the lower electrode 4, respectively. The lower electrode contact 18b is formed.
여기서, 상기 절연막 스페이서(16)를 형성하는 이유는 다음과 같다. 상기 확산 배리어층(12)은 수소 확산을 방지하기 위해서 필수적으로 형성되어야 하지만, 상기한 바와 같이 완전히 산화시키지 않은 상태이므로 약한 도전성을 띠고 있다.Here, the reason for forming the insulating film spacer 16 is as follows. The diffusion barrier layer 12 is essentially formed to prevent hydrogen diffusion, but has a weak conductivity because it is not completely oxidized as described above.
따라서, 상기 콘택홀에 직접 상부전극용 콘택(18a)과 하부전극용 콘택(18b)을 형성하게 되면 상기 확산 배리어층(12)을 통해 상기 상부전극용 콘택(18a)과 하부전극용 콘택(18b)이 전기적으로 단락되어 결국 캐패시터의 특성을 잃게 되므로, 상부전극용 콘택(18a)과 하부전극용 콘택(18b)을 서로 절연시키기 위해 상기 절연막 스페이서(16)를 형성하는 것이다.Therefore, when the upper electrode contact 18a and the lower electrode contact 18b are directly formed in the contact hole, the upper electrode contact 18a and the lower electrode contact 18b are formed through the diffusion barrier layer 12. ) Is electrically shorted and eventually loses the characteristics of the capacitor. Thus, the insulating film spacer 16 is formed to insulate the upper electrode contact 18a and the lower electrode contact 18b from each other.
상기한 바와 같이, 본 발명에서는 상기 확산 배리어층(12)을 형성함으로써 층간절연막(14) 내부의 수소 원자들이 강유전체층(4)을 이루고 있는 강유전체 물질과 반응하는 것을 방지할 수 있으며, 상기 확산 배리어층(12)으로 인해 발생되는 누설전류는 상기 확산 배리어층(12) 하부에 산화막 배리어층(10)을 구비함으로써 해소할 수 있다. 또한, 상기 확산 배리어층(12)으로 인해 상부전극용 콘택(18a)과 하부전극용 콘택(18b)이 서로 단락되는 문제점은 상기 콘택(18a, 18b)들이 형성되어질 콘택홀 측벽에 절연막 스페이서(16)을 형성함으로써 해소할 수 있다.As described above, in the present invention, by forming the diffusion barrier layer 12, it is possible to prevent the hydrogen atoms in the interlayer insulating film 14 from reacting with the ferroelectric material of the ferroelectric layer 4. The leakage current generated by the layer 12 can be eliminated by providing the oxide barrier layer 10 under the diffusion barrier layer 12. In addition, the short-circuit of the upper electrode contact 18a and the lower electrode contact 18b due to the diffusion barrier layer 12 may cause an insulation layer spacer 16 on the sidewalls of the contact holes where the contacts 18a and 18b are to be formed. Can be solved by forming
이처럼 본 발명에서는 층간절연막(14) 형성을 위해 필수적으로 구비되어야 하는 확산 배리어층(12)으로 인한 누설전류 문제를 해소하기 위해 상기 산화막 배리어층(10)을 형성한다. 그 결과, 캐패시터 내부 및 주변으로 흐르는 누설전류 문제가 해소되어 캐패시터의 특성이 향상된다. 또한, 상기 콘택홀 측벽에 절연막 스페이서(16)를 형성함으로써, 캐패시터의 상부전극과 하부전극에 형성된 콘택들(18a, 18b)이 서로 단락되는 것을 방지한다.As described above, the oxide barrier layer 10 is formed in order to solve the leakage current problem caused by the diffusion barrier layer 12 which is essentially provided for forming the interlayer insulating layer 14. As a result, the problem of leakage current flowing into and around the capacitor is solved, thereby improving the characteristics of the capacitor. In addition, the insulating layer spacers 16 are formed on the sidewalls of the contact holes, thereby preventing the contacts 18a and 18b formed on the upper and lower electrodes of the capacitor from being shorted to each other.
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960017529A KR100216866B1 (en) | 1996-05-22 | 1996-05-22 | Ferroelectric ram for preventing leakage currents and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960017529A KR100216866B1 (en) | 1996-05-22 | 1996-05-22 | Ferroelectric ram for preventing leakage currents and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970077687A KR970077687A (en) | 1997-12-12 |
| KR100216866B1 true KR100216866B1 (en) | 1999-09-01 |
Family
ID=19459555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960017529A KR100216866B1 (en) | 1996-05-22 | 1996-05-22 | Ferroelectric ram for preventing leakage currents and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100216866B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100362179B1 (en) * | 1999-12-30 | 2002-11-23 | 주식회사 하이닉스반도체 | Semiconductor memory device having oxide and Ti double layer capable of preventing hydrogen diffusion and method for forming the same |
| KR100706015B1 (en) * | 2001-03-27 | 2007-04-11 | 샤프 가부시키가이샤 | Method of using titanium doped aluminum oxide for passivation of ferroelectric materials and devices including the same |
-
1996
- 1996-05-22 KR KR1019960017529A patent/KR100216866B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100362179B1 (en) * | 1999-12-30 | 2002-11-23 | 주식회사 하이닉스반도체 | Semiconductor memory device having oxide and Ti double layer capable of preventing hydrogen diffusion and method for forming the same |
| KR100706015B1 (en) * | 2001-03-27 | 2007-04-11 | 샤프 가부시키가이샤 | Method of using titanium doped aluminum oxide for passivation of ferroelectric materials and devices including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970077687A (en) | 1997-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3407204B2 (en) | Ferroelectric integrated circuit and method of manufacturing the same | |
| US5702970A (en) | Method for fabricating a capacitor of a semiconductor device | |
| US20010001488A1 (en) | Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer | |
| JPH01154551A (en) | Semiconductor storage integrated circuit device and manufacture thereof | |
| JPH0465548B2 (en) | ||
| KR960011653B1 (en) | Dram cell and the method | |
| JPH05183106A (en) | Semiconductor device and manufacture thereof | |
| US6162671A (en) | Method of forming capacitors having high dielectric constant material | |
| US6294805B1 (en) | Ferroelectric memory devices including capacitors located outside the active area and made with diffusion barrier layers | |
| US6171941B1 (en) | Method for fabricating capacitor of semiconductor memory device using titanium aluminum nitride as diffusion-inhibiting layer | |
| KR19990083038A (en) | Ferroelectric memory device with improved ferroelectric capacity characteristic | |
| KR100519240B1 (en) | Manufacturing method of capacitor electrode made of platinum metal | |
| KR100216866B1 (en) | Ferroelectric ram for preventing leakage currents and its manufacturing method | |
| US6090658A (en) | Method of forming a capacitor including a bottom silicon diffusion barrier layer and a top oxygen diffusion barrier layer | |
| US6605505B2 (en) | Process for producing an integrated semiconductor memory configuration | |
| US20020033493A1 (en) | Semiconductor storage device and its manufacturing method | |
| JPH07169854A (en) | Semiconductor device and manufacture of it | |
| KR100317980B1 (en) | Semiconductor device and manufacturing method for the same | |
| KR100308369B1 (en) | Capacitor Structure for Integrated Circuit and Manufacturing Method Thereof | |
| JPH02288361A (en) | Semiconductor device | |
| JPH08236719A (en) | Platinum thin film and semiconductor device, and method of their fabrication | |
| KR0166809B1 (en) | Memory cell capacitor fabrication method | |
| KR100614578B1 (en) | high-dielectric capacitor in semiconductor device | |
| JPH06132496A (en) | Semiconductor memory device and fabrication thereof | |
| JPH0456160A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070514 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |