KR100216065B1 - Multi-lead on chip package - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead-on-chip type multi chip package, in which at least two or more semiconductor chips having a plurality of bonding pads are horizontally spaced apart from each other, Wherein the semiconductor chip is mounted on the lower surface of the inner lead with a bonding means and a base chip having a bonding pad formed at a central portion thereof on the lower surface of the semiconductor chip is attached so that the bonding pad is positioned between the semiconductor chips, Wherein the semiconductor chip, the base chip, the electrical connection means, and the inner lead are sealed with molding resin, and the outer lead formed integrally with the inner lead is exposed to the outside of the molding resin . According to this, the chip occupancy area is increased compared to the package, and the size of the package is reduced, so that a multi-chip package capable of multi-functioning and compositing can be realized.

Description

Lead-On Chip Multi-Chip Package (LEAD ON CHIP TYPE MULTI CHIP PACKAGE)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead-on-chip type multi-chip package, and more particularly, to a lead-on-chip type multi-chip package having a plurality of chips will be.

In recent years, companies that mount semiconductor packages on printed circuit boards and mount them on electronic devices to be commercialized, for example, are demanding improvements in technologies such as versatility, high functionality, high speed, and small size and light weight of semiconductor packages.

As a result, semiconductor manufacturers have increased the size of semiconductor chips by incorporating many functions within a single semiconductor chip. The increase in the size of the semiconductor chip has been faced with the difficulty and reliability of the semiconductor package manufacturing process due to the size restriction of the semiconductor chip which can be embedded in the limited semiconductor package.

When the occupation rate of a chip in a plastic semiconductor package is more than about 70%, it is impossible to mount a chip using a general lead frame having a die pad, In addition, in a semiconductor package mounting a memory chip, it is difficult to further assemble the package due to a chip size that increases in proportion to the memory capacity.

To solve these problems, semiconductor manufacturers have developed a new concept of lead-on-chip package that uses a chip in a semiconductor package without using a lead frame with a die pad. The structure of such a lead-on-chip package will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing the structure of a general lead-on-chip package.

Referring to FIG. 1, the lead-on chip package 50 includes a center pad-type semiconductor chip 10 having a plurality of bonding pads 12 formed at the upper center thereof, And is attached to the lower surface by an electrically insulating adhesive tape 20.

The bonding wires 30 are electrically connected to the bonding pads 12 corresponding to the inner leads 42 bonded and fixed to the upper surface of the semiconductor chip 10 and the electrical connection portions including the semiconductor chip 10 are formed Is sealed with a resin (60), and the outer lead (43) is molded in a shape suitable for mounting.

First, a lead frame having a down set 45 formed on a predetermined portion of the inner lead 42 is prepared so as to facilitate chip bonding. .

A polyimide-based double-sided adhesive tape is attached as an adhesive tape 20 to the upper surface of the semiconductor chip 10 to which the lower surface of the inner lead 42 or the inner lead 42 thereof is bonded, The internal leads 42 are bonded to each other by a method of aligning the semiconductor chip 10 and the semiconductor chip 10 and then pressing the internal leads 42 using a bonding tool that emits high heat, .

Next, the bonding pad 12 and the inner lead 42 are wire-bonded with the metal wire 30 so that the semiconductor chip 10 can transmit an electric signal to the outside, and the electrical connection portion between the semiconductor chip and the bonding pad The molding resin 60 is molded with an epoxy mold compound, which is a plastic resin series, in order to safely protect it from external physical, mechanical impact or chemical reaction.

Thus, in the conventional lead-on-chip package, the die pad to which the semiconductor chip is adhered and fixed can be removed to achieve miniaturization, and various defects generated in the die pad are removed, which is advantageous in terms of reliability.

However, since such a lead-on-chip package has a structure capable of mounting only a single semiconductor chip, it is impossible to mount a plurality of semiconductor chips having various functions. This means that it is impossible to make a multi chip package in which a plurality of semiconductor chips are mounted, and there are disadvantages in that it is impossible to improve functions of multi-functionalization and compounding by mounting chips having various functions.

It is an object of the present invention to provide a multi-lead-on-chip package that can be multi-functionalized and compounded by allowing a plurality of semiconductor chips to be mounted on the structure of a lead-on-chip package while maintaining miniaturization and reliability as advantages of a lead- have.

FIG. 1 is a cross-sectional view showing a structure of a general lead-on-chip package. FIG.

FIG. 2 is a partial cutaway perspective view showing one embodiment of a lead-on-chip type multi-chip package according to the present invention; FIG.

3 is a sectional view taken along line 3-3 of FIG. 2;

FIG. 4 is a partially cutaway perspective view showing another embodiment of a lead-on-chip type multi-chip package according to the present invention;

5 is a cross-sectional view taken along line 5-5 of FIG. 4;

DESCRIPTION OF THE REFERENCE NUMERALS

10, 110, 210: chips 12, 112, 212: bonding pads

20, 120, 220: adhesive tape 30, 130, 230: bonding wire

40, 140, 240: leads 45, 145, 245:

60, 160, 260: molding resin 280: base chip

In order to achieve the above object, a lead-on-chip type multi-chip package according to the present invention is characterized in that at least two or more semiconductor chips having a plurality of bonding pads are horizontally arranged so as to be spaced apart from each other, A base chip having a bonding pad formed at a central portion thereof on the lower surface of the semiconductor chips, and a bonding pad so that the bonding pads are positioned between the semiconductor chips, and electrically connected to the bar or conductor chips, And the inner leads are sealed with a molding resin, and the outer leads integrally formed with the inner leads are exposed to the outside of the molding resin.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a partially cutaway perspective view showing an embodiment of a lead-on-chip type multi-chip package according to the present invention, and FIG. 3 is a sectional view taken along the line 3-3 'in FIG.

Referring to FIGS. 2 and 3, a lead-on-chip type multi-chip package 100 according to the present invention includes two semiconductor chips 110 having a plurality of bonding pads 112 formed thereon, And is attached to the lower surface of the inner lead 142.

The inner leads 142 formed on the top surface of the semiconductor chips 110 are formed integrally with the outer leads 143 formed in a direction away from the inner leads 142. The semiconductor chips 110 are attached and fixed to the lower surface of the inner lead 142 by an adhesive tape 120. [

The bonding wires 130 electrically connect the bonding pads 112 formed in the semiconductor chips 110 and the corresponding internal leads 142 and the molding resin 160 is electrically connected to the semiconductor chips 110 and the electrical connection portion are internally sealed.

The adhesive tape 120 used for attaching the semiconductor chip 110 and the lead 142 is formed by applying an adhesive material to both sides of a polyimide tape electrically insulated from the semiconductor chip 110, 112 are not formed.

The inner leads are easily attached to the semiconductor chips 110, and the semiconductor chips 110 are positioned in the molding resin during the molding process. Thus, .

In such a multi-lead-on-chip package, two semiconductor chips are attached to the internal leads, which is advantageous in increasing the occupied area of the semiconductor chip relative to the package. In addition, in the manufacture of a multi-lead-on-chip package, a device used for manufacturing a conventional lead-on chip package can be used as a substitute.

Meanwhile, although the electrical connection method using wires is applied in the above embodiment, another method may be used in which a bump is formed, and a direct electrical connection is made between the extended inner lead and the metal bump formed on the bonding pad . In addition, in the embodiment, the leads are symmetrically bisected to both sides and the semiconductor chips are respectively bonded and fixed to the respective leads. However, a plurality of chips having center pads are horizontally arranged at regular intervals, On-chip package having a shape in which leads are adhered and fixed on the substrate.

FIG. 4 is a partially cutaway perspective view showing another embodiment of the lead-on-chip type multi-chip package according to the present invention, and FIG. 5 is a sectional view taken along line 5-5 of FIG.

4 and 5, in the lead-on-chip type multi-chip package 200, the semiconductor chips 210 having the plurality of bonding pads 212 formed on the lower surfaces of the internal leads 242 are horizontally spaced apart from each other A center chip type base chip 280 in which a plurality of bonding pads 282 are formed on the upper surface of the semiconductor chips 210 is attached to the bottom surface of the semiconductor chips 210 by an electrically insulating adhesive tape 222 As shown in Fig. At this time, the bonding pads 282 of the base chip 280 are positioned between the upper semiconductor chips 210.

The bonding pads 212 and 282 of the semiconductor chips 210 and 280 and the internal leads 240 are electrically connected by a bonding wire 230. The forming resin 260 is electrically connected to the semiconductor chips 210 and the base 210. [ The chip 280 and the electrical connection portion are internally encapsulated.

This embodiment is a structure in which semiconductor chips are laminated with an electrically insulating adhesive tape by using a semiconductor chip having a center pad in another form of the multi-lead-on-chip type multi-chip package. That is, the semiconductor chips having no center pads are horizontally spaced apart from each other to be attached to the lower surface of the leads with an electrically insulating adhesive tape, and the base chips having the center pads on the lower surfaces of the semiconductor chips are stacked to form multi- It is advantageous to reduce the size of the package as several mounted types.

As described above, the multi-lead-on-chip type multi-chip package according to the present invention can increase the mounting density of a semiconductor package when implementing a multi-chip package having a plurality of semiconductor chips, It is possible to manufacture a composite multi-chip package.

Claims (1)

Wherein at least two or more semiconductor chips having a plurality of bonding pads are horizontally arranged to be spaced apart from each other so that the surface on which the bonding pads are formed is attached to the lower surface of the inner leads by adhesive means, The semiconductor chip, the base chip and the inner lead are electrically connected by the electrical connection means, and the semiconductor chips, the base chip, the electrical connection And the inner leads are sealed with a molding resin, and an outer lead integrally formed with the inner leads is exposed to the outside of the molding resin.