KR100196222B1 - Manufacturing method of semiconductor chip - Google Patents
Manufacturing method of semiconductor chip Download PDFInfo
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- KR100196222B1 KR100196222B1 KR1019960040149A KR19960040149A KR100196222B1 KR 100196222 B1 KR100196222 B1 KR 100196222B1 KR 1019960040149 A KR1019960040149 A KR 1019960040149A KR 19960040149 A KR19960040149 A KR 19960040149A KR 100196222 B1 KR100196222 B1 KR 100196222B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- Condensed Matter Physics & Semiconductors (AREA)
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 상부에 회로가 형성된 소자영역과 소자영역의 가장자리에 형성된 패드형성영역을 구비한 반도체 칩에 있어서, 패드형성영역에 형성된 다 수개의 관통홀과, 관통홀에 형성되어, 회로에 접속된 관통배선과, 관통배선과 전기적으로 연결되는 하부금속배선과, 반도체 칩의 하부에 형성되며, 하부금속배선과 전기적으로 연결되어 회로를 외부회로와 연결시키는 다 수개의 패드을 구비한다.SUMMARY OF THE INVENTION The present invention provides a semiconductor chip having a device region with a circuit formed thereon and a pad forming region formed at an edge of the device region, wherein the plurality of through holes formed in the pad forming region are formed in the through holes and connected to the circuit. The through wiring, a lower metal wiring electrically connected to the through wiring, and a plurality of pads formed under the semiconductor chip and electrically connected to the lower metal wiring to connect a circuit with an external circuit are provided.
Description
제1도는 종래의 반도체 칩 및 그 제조방법을 설명하기 위한 도면이고,1 is a view for explaining a conventional semiconductor chip and its manufacturing method,
제2도는 본 발명의 반도체 칩 및 그 제조방법을 설명하기 위한 도면이다.2 is a view for explaining the semiconductor chip and the manufacturing method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10, 20 : 반도체 칩 11, 21 : 소자영역10, 20: semiconductor chip 11, 21: device area
23 : 관통홀 24 : 절연막23 through hole 24 insulating film
25 : 관통배선 26 : 보호막25: through wiring 26: protective film
27 : 금속층 28 : 하부금속배선27: metal layer 28: lower metal wiring
본 발명은 반도체 칩 및 그 제조방법에 관한 것으로, 특히 디바이스의 내부에 형성된 회로를 외부회로와 연결하는 역할을 수행하는 패드가 칩에 있어서 차지하는 면적을 최소화하는 데 적당한 반도체 칩 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a method of manufacturing the same, and more particularly, to a semiconductor chip suitable for minimizing an area occupied by a pad, which serves to connect a circuit formed inside a device with an external circuit, and a method of manufacturing the same will be.
반도체 칩의 소자영역의 가장자리에 형성되는 패드는 디바이스의 내부에 형성된 회로를 외부회로와 연결하는 역할고, 디바이스의 불/양품을 구별하는 테스트 과정에서의 콘택, 신규 디바이스 물리적/전기적 특성을 규명하는 콘택점 역할을 한다.The pad formed at the edge of the element region of the semiconductor chip connects the circuit formed inside the device with the external circuit, and identifies the contact and new device physical / electrical characteristics during the test process to distinguish the defective / goods of the device. It acts as a contact point.
제1도는 종래의 반도체 칩 및 그 제조방법을 설명하기 위한 도면으로, 제1도의 (a)는 소자영역과 그 가장자리의 패드를 표시한 종래의 반도체 칩의 평면도이고, 제1도의 (b)는 종래의 반도체 칩의 단면도이다.1 is a view for explaining a conventional semiconductor chip and a method of manufacturing the same. FIG. 1 (a) is a plan view of a conventional semiconductor chip showing device regions and pads at their edges, and FIG. It is sectional drawing of the conventional semiconductor chip.
이하, 첨부된 도면을 참고로 하여 종래의 반도체 칩 및 그 제조방법을 설명하겠다.Hereinafter, a conventional semiconductor chip and a method of manufacturing the same will be described with reference to the accompanying drawings.
종래의 반도체 칩(10)은 제1도의 (a)(b)와 같이, 회로가 형성된 소자영역(11)과 소자영역의 가장자리에 형성된 패드형성영역을 갖으며, 패드형성영역에는 다 수개의 패드(12)가 형성된다.The conventional semiconductor chip 10 has an element region 11 in which a circuit is formed and a pad forming region formed at an edge of the element region, as shown in (a) and (b) of FIG. 1, and a plurality of pads are formed in the pad forming region. 12 is formed.
종래의 대부분의 반도체 디바이스 소자는 공정상 양면을 가공하는 것이 어려우므로 설계시부터 메모리소자, 배선, 패드를 한쪽면에만 구성된다.Since most of the conventional semiconductor device elements are difficult to process on both sides in the process, the memory elements, the wirings, and the pads are configured only on one side from the design time.
디램기술이 발전됨에 따라 메모리 셀 자체는 축소되며, 디램 뿐만 아니라 기타 여러 소자의 외부와의 연결부분에 해당하는 패드는 메모리 셀에 비해 큰 면적을 차지하고 있다.As DRAM technology advances, the memory cell itself shrinks, and pads corresponding to external parts of not only DRAM but also other devices occupy a larger area than memory cells.
즉, 종래의 반도체 칩은 소자영역에 비해 지나치게 패드가 차지하는 비율이 크며, EDS 테스트시에는 소자의 전압과 신호를 공급하는 프로브가 잘못 패드를 찍거나 프로브가 웨이퍼 표면을 긋는 스크래치 현상이 발생된다.That is, in the conventional semiconductor chip, the pad occupies an excessively large ratio compared to the device region, and during the EDS test, a phenomenon in which the probe supplying the voltage and the signal of the device incorrectly pads or scratches the wafer surface is generated.
또한, 웨이프 한면만을 이용하는 기술은 회로, 배선, 패드를 한 평면에 배치함으로써 패드 자체의 면적이 제한도는 문제점이 발생된다.In addition, the technology using only one side of the wafer causes a problem that the area of the pad itself is limited by arranging the circuit, the wiring, and the pad in one plane.
본 발명은 이러한 문제저믈 해결하고자 안출된 것으로, 반도체 칩에 있어서 소자영역의 가장자리에 차지하고 있는 패드의 비율을 최소화하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and aims to minimize the proportion of pads occupying the edges of device regions in semiconductor chips.
상기와 같은 목적을 달성하고자, 본 발명은 상부에 회로가 형성된 소자영역과 소자영역의 가장자리에 형성된 패드형성영역을 구비한 반도체 칩에 있어서, 패드형성영역에 형성된 다 수개의 관통홀과, 관통홀에 형성되어, 회로에 접속된 관통배선과, 관통배선과 전기적으로 연결되는 하부금속배선과, 반도체 칩의 하부에 형성되며, 하부금속배선과 전기적으로 연결되어 상기 회로를 외부회로와 연결시키는 다 수개의 패드를 갖으며, 또한 본 발명의 반도체 칩 및 그 제조방법을 통하여 반도체 칩의 패드를 하부표면으로 옮김으로써 종래 패드 크기보다 상당히 확대된 패드를 얻을 수 있다.In order to achieve the above object, the present invention is a semiconductor chip having a device region with a circuit formed on the top and a pad forming region formed on the edge of the device region, a plurality of through holes and through holes formed in the pad forming region; A through wiring connected to the circuit, a lower metal wiring electrically connected to the through wiring, and a lower portion of the semiconductor chip and electrically connected to the lower metal wiring to connect the circuit with an external circuit. It is possible to obtain a pad which has two pads and is significantly enlarged than the conventional pad size by moving the pad of the semiconductor chip to the lower surface through the semiconductor chip and the method of manufacturing the same.
제2도의 (a)∼(e)는 본 발명의 반도체 칩 및 그 제조방법을 단계적으로 설명하기 의해 도시된 도면으로, 이하 첨부된 도면을 참조로 하여 본 발명의 반도체 칩 및 그 제조방법을 알아보면 다음과 같다.(A) to (e) of FIG. 2 are diagrams illustrating the semiconductor chip of the present invention and its manufacturing method step by step, and the semiconductor chip of the present invention and its manufacturing method will now be described with reference to the accompanying drawings. If you look like this:
상부에 회로가 형성된 소자영역(21)과 소자영역의 가장자리에 형성된 패드 형성영역을 구비한 본 발명의 반도체 칩(20)은 제2도의 (a)(b)(c)(d)(e)와 같이, 소자영역의 가장자리, 즉 패드형성영역에 형성된 다 수개의 관통홀(23)과, 관통홀(23)에 형성되어, 회로에 접속된 관통배선((25)과, 회로가 형성된 반도체 칩(20) 하부에 형성되어, 관통배선(25)과 전기적으로 연결되는 하부 금속배선(28)고, 회로가 형성된 반도체 침(20)의 하부에 형성되며, 하부금속배선(28)과, 전기적으로 연결되어 회로를 외부회로와 연결시키는 다 수개의 패드(22-2)를 포함하여 이루어진다.The semiconductor chip 20 of the present invention having a device region 21 having a circuit formed thereon and a pad forming region formed at an edge of the device region is shown in (a) (b) (c) (d) (e) of FIG. As described above, a plurality of through holes 23 formed in the edge of the element region, that is, the pad forming region, through holes 25 formed in the through holes 23 and connected to the circuit, and a semiconductor chip in which the circuit is formed. The lower metal wiring 28 is formed under the 20, and electrically connected to the through wiring 25, and is formed under the semiconductor needle 20 on which the circuit is formed, and the lower metal wiring 28 is electrically connected to the lower metal wiring 28. And a plurality of pads 22-2 connected to connect circuits with external circuits.
그리고 본 발명의 반도체 칩(20)은 회로가 형성된 칩 하부에 형성된 다 수개의 패드(22-2)들과 관통배선(25)을 전기적으로 연겨랗는 하부금속배선(28)을 구비하거나, 또는 관통홀(23)을 회로가 형성된 반도체 칩(20) 하부에 형성된 패드(22-2)에 형성한다.In addition, the semiconductor chip 20 of the present invention includes a plurality of pads 22-2 formed under the chip on which the circuit is formed, and a lower metal wiring 28 electrically connecting the through wiring 25, or through The hole 23 is formed in the pad 22-2 formed under the semiconductor chip 20 where the circuit is formed.
이러한 구성으로 이루어진 본 발명의 반도체 칩의 제조방법을 알아보면 다음과 같다.Looking at the manufacturing method of the semiconductor chip of the present invention having such a configuration as follows.
우선, 제2도의 (a)와 같이, 상부에 회로가 형성된 칩(20)의 소자영역(21) 가장자리에 다 수개의 관통홀(23)을 형성하고, 제2도의 (b)와 같이, 관통홀(23) 표면에 SiO2로 절연막(24)을 형성한다.First, as shown in FIG. 2A, a plurality of through holes 23 are formed at the edges of the element region 21 of the chip 20 having the circuit formed thereon, and as shown in FIG. An insulating film 24 is formed of SiO 2 on the surface of the hole 23.
이때, 관통홀(23)은 칩 상부표면의 패드 형성영역에 레이저를 이용하여 반도체 칩 하부를 관통하도록 형성하는 데, 하나의 패드형성영역에 다 수개의 홀을 형성할 수도 있다.In this case, the through hole 23 is formed to penetrate the lower portion of the semiconductor chip by using a laser in the pad formation region of the upper surface of the chip, and a plurality of holes may be formed in one pad formation region.
그리고 제2도의 (c)와 같이, 절연막(24)이 형성된 관통홀(23)에 금속을 매립하여 관통배선(25)을 형성한다.As shown in (c) of FIG. 2, through-holes 25 are formed by burying metal in the through-holes 23 in which the insulating film 24 is formed.
이때, 관통배선을 매립하는 금속으로는 알루미늄이나 또는 폴리실리콘을 사용한다.At this time, aluminum or polysilicon is used as a metal for embedding the through wiring.
이어서 제2도의 (d)(e)와 같이, 반도체 칩(20) 하부에 패드(22-2)를 형성하고, 관통배선(25)과 패드를 연결시키는 하부금속배선(28)을 형성한다.Subsequently, as illustrated in FIG. 2D, the pad 22-2 is formed under the semiconductor chip 20, and the lower metal wiring 28 connecting the through wiring 25 and the pad is formed.
이때, 반도체 칩 하부에 형성되는 패드는 정방형으로 형성하여 패키지와 디바이스핀의 역할을 할 수 있도록 충분히 크게 형성한다.At this time, the pad formed on the lower portion of the semiconductor chip is formed in a square and large enough to serve as a package and a device pin.
그리고 하부금속배선(28)을 보호하기 위하여 보호막(26)을 형성하고, 보호막 공정이 완료된 후 패드영역에 강화된 금속층(27)을 증착한다.In addition, a protective film 26 is formed to protect the lower metal wiring 28, and the reinforced metal layer 27 is deposited on the pad region after the protective film process is completed.
본 발명의 반도체 칩 및 그 제조방법으로는 디바이스 상부표면의 패드의 면적을 축소하거나 완전히 칩의 하부표면으로 옮김으로써 기존의 패드 크기보다 상당히 확대된 패드를 얻을 수 있다.In the semiconductor chip of the present invention and a method of manufacturing the same, a pad that is considerably enlarged than a conventional pad size can be obtained by reducing the area of the pad on the upper surface of the device or completely moving to the lower surface of the chip.
또한, 확대된 패드는 탐침 테스트시 탐침의 긁힘현상에 능동적으로 회로를 보호할 수 있다.In addition, the enlarged pad can actively protect the circuit during probe probe scratches.
아울러 본 발명의 반도체 칩 하부표면에 형성된 확대된 패드는 프로브탐침과 같은 고정밀도 장비의 마진을 높일 수 있다.In addition, the enlarged pad formed on the lower surface of the semiconductor chip of the present invention can increase the margin of high precision equipment such as a probe probe.
그리고 반도체 칩 하부에 패드가 형성되어 있기 때문에 반도체 칩 자체가 와이어본딩을 하지 않고 금속의 배선층을 형성하고, 보호막의 형성으로 자체패키지를 만들 수 있으며, 이로 인하여 발생하는 핀손상등의 에러를 줄일 수 있고, 또한 패키지 두께도 축소할 수 있다.And since the pad is formed under the semiconductor chip, the semiconductor chip itself can form a metal wiring layer without wire bonding, and a self-package can be made by forming a protective film, thereby reducing errors such as pin damage. In addition, the package thickness can be reduced.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960040149A KR100196222B1 (en) | 1996-09-16 | 1996-09-16 | Manufacturing method of semiconductor chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960040149A KR100196222B1 (en) | 1996-09-16 | 1996-09-16 | Manufacturing method of semiconductor chip |
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| Publication Number | Publication Date |
|---|---|
| KR19980021334A KR19980021334A (en) | 1998-06-25 |
| KR100196222B1 true KR100196222B1 (en) | 1999-06-15 |
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| KR1019960040149A KR100196222B1 (en) | 1996-09-16 | 1996-09-16 | Manufacturing method of semiconductor chip |
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| KR (1) | KR100196222B1 (en) |
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- 1996-09-16 KR KR1019960040149A patent/KR100196222B1/en not_active IP Right Cessation
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| KR19980021334A (en) | 1998-06-25 |
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