KR0122096B1 - Source voltage regurator of semiconductor lsi - Google Patents

Abstract

The power supply voltage regulator of a semiconductor integrated circuit having a dielectric gate field effect type output driving transistor which has a channel connected between an internal power supply voltage and a power supply voltage and a gate controlled by a power supply voltage sensing signal and a converting control signal, and a differential amplifier which has an output node connected to the gate of the output driving transistor and a first input stage connected to the internal power supply voltage, has a control node the potential of which is determined according to the power supply voltage sensing signal and the converting control signal; a dielectric gate field effect type pass transistor which has a gate connected to the control node and a channel connected between the gate of the output driving transistor and a current sink; a dielectric gate field effect type first pull-up transistor which has a channel connected between the gate of the output driving transistor and the power supply voltage and a gate connected to the converting control signal; a dielectric gate field effect type equalization transistor which has a gate connected to the converting control signal and a channel connected between the output node of the differential amplifier and the drain of an NMOS transistor which has a gate connected to the first input stage of the differential amplifier; a dielectric gate field effect type pull-down transistor which has a channel connected between a second input stage of the differential amplifier and a ground voltage and a gate connected to the control node; and a dielectric gate field effect type second pull-up transistor which has a channel connected between a reference voltage and the second input stage of the differential amplifier and a gate connected to the control node, whereby if the power supply voltage is over a predetermined level, the gate of the output driving transistor is connected to the power supply voltage and the gates of the transistors for loading of the differential amplifier via the channel of the first pull-up transistor and the second input stage of the differential amplifier is connected to the reference voltage via the channel of the second pull-up transistor, while if the power supply voltage is below the predetermined level, the gate of the output driving transistor is connected to the current sink via the channel of the pass transistor and the second input stage of the differential amplifier is connected to the ground voltage via the channel of the pull-down transistor.

Description

Supply Voltage Regulator of Semiconductor Integrated Circuits

1 is a circuit diagram of a conventional power supply voltage regulator.

2 is a block diagram of a power supply voltage regulator according to an embodiment of the present invention.

3A is a detailed circuit diagram illustrating an example of the first reference voltage generator 20 of FIG. 2.

3B is a detailed circuit diagram illustrating an example of the comparison voltage generator 50 of FIG. 2.

3c is a detailed circuit diagram showing an example of the sense amplifier 30 of FIG.

3d is a detailed circuit diagram showing an example of the pulse generator 80 of FIG.

FIG. 3E is a detailed circuit diagram showing an example of the latch portion 70 of FIG.

4A is a detailed circuit diagram illustrating an example of the second reference voltage generator 90 of FIG. 2.

4B is a detailed circuit diagram showing an example of the conversion control unit 60 in FIG.

4c is a detailed circuit diagram illustrating an example of the power supply voltage converter 100 of FIG.

5 is an operation timing diagram of FIG.

FIG. 6A is a detailed circuit diagram illustrating another embodiment of the power supply voltage converter 100 of FIG. 2.

FIG. 6B is a detector circuit diagram for outputting the detection signal of FIG.

6C is an operation timing diagram of FIG.

FIG. 7A is a waveform diagram showing an operation pattern of a Vccp signal according to the configuration of FIG.

7b is a waveform diagram showing simulation results according to the Vccp signal and the? DET signal.

* Explanation of symbols for main parts of the drawings

10: Control : Low address strobe signal

20: 1st reference voltage generating part øR: Master clock

30: detection amplifier Vcomp: comparison voltage

50: comparison voltage generator øDETEN: detection control signal

60: conversion control part RP: latch control signal

70: Latch part øVCCD: Detection voltage signal

80: pulse generator øDET: power supply voltage detection signal

90: second reference voltage generator øENPB: first conversion control signal

100: power supply voltage conversion part øENPBP: second conversion control signal

200: power supply voltage detection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for stabilizing a level of power supply voltage used in a semiconductor integrated circuit. In particular, the present invention relates to a power voltage regulator required for an integrated circuit such as a highly integrated semiconductor memory device using a low power supply voltage. It is about.

In the case of a semiconductor integrated circuit, for example, dynamic-RAM, which is a read / write memory, the improvement of the density is accompanied by a four times progression for each generation in addition to the increase in the capacity. In the case of a large integrated circuit (VLSI), the gate length of a transistor constituting a memory cell is designed to be less than 1 micron, that is, a sub-micron design rule. The pitch between wirings is also narrowing. In particular, MOS transistors and other circuit components designed for sub-micron class have become sensitive and vulnerable to the electric field formed during operation. Thus, the power voltage level of 5V, which has been used until recently, has been inevitably lowered. In addition, as the number of memory cells operating at a time increases due to high integration, the peak current rapidly increases, and the induced noise often causes an unstable level of the power supply voltage. Thus, a power supply voltage regulator or a power supply voltage conversion circuit has been proposed to stabilize the level of the power supply voltage which is undesirably changed by noise induced during operation. It is common for this power supply voltage regulator to be manufactured by an integrated circuit manufacturing process on one semiconductor chip.

An example of a conventionally presented power supply voltage regulator is shown in FIG. 1 (see IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 5, October 1988, pp. 1128-1132). The power supply voltage regulator of FIG. 1 comprises a differential amplifier 1 for comparing the reference voltage V _L1 with the current power supply voltage Vcc level V _L2 , and a driver 2 using a PMOS transistor M _D. It is. The differential amplifier 1 uses the PMOS transistors M _L1 and M _L2 as loads and the NMOS transistors M _D1 and M _D2 as inputs. When the voltage V _{L2, which} is the potential of the internal voltage, is input at a potential lower than the reference voltage V _L1 , the gate voltage V _G of the M _D of the driving PIM transistor is lowered so that the gate of the PMO transistor M _D becomes low. The magnitude of the source-to-source voltage | Vgs | becomes large. Then, the voltage V _L2 rises through the channel of the PIO transistor M _D until the potential of the reference voltage V _L1 is reached. On the contrary, when V _L2 is input at a potential higher than V _L1 , the voltage V _L2 is lowered until the potential of the reference voltage V _L1 is reached by the decrease of Vgs.

As can be seen from the operation of the conventional circuit of FIG. 1, the correction of the internal power supply voltage lower or higher than the reference voltage is entirely dependent on the gate-to-source voltage of the PMOS transistor M _D used for driving. Its calibration width is defined by | Vgs |, the absolute value of the gate-to-source voltage. The size of this │Vgs│ depends on the voltage difference between the gate voltage V _G and the power supply voltage Vcc which is an output of the differential amplifier (1). Since the output potential of the differential amplifier 1 is represented by a slight potential difference between V _L1 and V _L1 , a small value even though the output potential of the differential amplifier 1, that is, V _G is a potential that can turn on the PMO transistor M _D. It is not enough to raise the lowered internal power supply voltage V _L2 to a desired potential. In particular, when the power supply voltage is low, the potential of V _L2 that sufficiently turns on the PIO transistor M _D to become an internal power supply voltage. Although the value of | Vgs | becomes smaller even though the value of? Vgs | is increased, it is not possible to provide the PMO transistor M _D with sufficient driving capability in raising and correcting the internal power supply voltage. In other words, the capacity for voltage compensation is insufficient.

In addition, since the magnitude of Vgs is small, the internal power supply voltage V _L2 lowered due to its poor sensitivity in feeding back V _L2 to the gate of the NMOS transistor M _D2 is brought to a desired potential. There is a problem that it takes a long time to recover. The smaller the value of Vgs is, the longer the charging time of the lower V _L2 is and the longer the gate voltage V _G appears. This phenomenon becomes more prominent as the potential of the power supply voltage employed in the memory device is lowered.

Accordingly, an object of the present invention is to provide a power supply voltage regulator capable of stabilizing a potential of a power supply voltage used internally in an integrated circuit employing a low power supply voltage.

Another object of the present invention is to provide a low power supply voltage regulator having a sufficient capacity to stabilize the potential of the power supply voltage used therein even when an integrated circuit such as a semiconductor memory device uses a low power supply voltage.

It is still another object of the present invention to provide a low power supply voltage regulator capable of high speed operation in stabilizing the potential of a power supply voltage used therein even when an integrated circuit such as a semiconductor memory device uses a low power supply voltage.

It is still another object of the present invention to provide a low power semiconductor memory device having a power supply voltage regulator capable of quickly restoring a potential of a power supply voltage that is out of a constant level.

It is still another object of the present invention to provide a low power integrated circuit having a power supply voltage regulator capable of quickly restoring the potential of the power supply voltage beyond a certain level.

In order to achieve the object of the present invention, the present invention uses a power supply voltage of a constant potential, the channel is connected between the internal power supply voltage and the power supply voltage and the gate of the gate according to the power supply voltage detection signal and the conversion control signal An integrated circuit having an output gate transistor of an insulated gate field effect type whose potential is controlled, and a differential amplifier circuit having an output node connected to a gate of the output drive transistor and a first input terminal connected to the internal power supply voltage terminal. A control node having a potential determined according to a sensing signal and a conversion control signal, an insulated gate field effect type fast transistor having a gate connected to the control node, and a channel connected between the gate and the current sink of the output driving transistor; A channel is connected between the gate of the driving transistor and the power supply voltage to the conversion control signal. A first pull transistor of an insulated gate field effect type having a gate connected thereto, a drain of an enMOS transistor having a gate connected to the conversion control signal, and a gate connected to a first input terminal of the differential amplifier circuit, and an output of the differential amplifier circuit. An equalization transistor of an insulated gate field effect type having a channel connected between nodes, an insulated gate field effect type pull-down transistor having a channel connected between a second input terminal of the differential amplifier circuit and a ground voltage and a gate connected to the control node; And an insulated gate electric field connected to a pull-down transistor and having a channel connected between a reference voltage set according to a current potential of the power supply voltage and a second input terminal of the differential amplifier circuit and a gate connected to the control node. And an effective second pull transistor. When the power supply voltage is greater than or equal to a predetermined potential, the gate of the output driving transistor is connected to the power supply voltage and the gates of the load transistors of the differential amplification circuit through a channel of the first pull transistor. A second input terminal is connected to the reference voltage through the channel of the second pull transistor, and when the power supply voltage is below a predetermined potential, the gate of the output driving transistor is connected to the current sink through the channel of the fast transistor, A second input terminal of the differential amplifier circuit is connected to the ground voltage through a channel of the pull down transistor. In addition, the differential amplification circuit used in the present invention is connected to the ground voltage through a channel of an insulated gate field effect transistor, and the insulated gate field effect transistor is used when the power supply voltage is above a certain potential when the integrated circuit is active. Is turned on.

Hereinafter, preferred embodiments of the present invention will be described in detail with the accompanying drawings. First, the configuration of the power supply voltage regulator according to the present invention will be described. It should be noted that examples of each component described later based on the drawings are not exhaustive and may be used in any form or power supply voltage regulator of the present invention as long as they have a function for achieving the object of the present invention.

2, a power supply voltage conversion circuit according to the present invention is a row address strove signal (row address strove signal) By typing Master Clock master clock) to generate øR The control unit 10, the power supply voltage sensing circuit 200 for detecting the potential of the current internal power supply voltage, the second reference voltage generator 90, the conversion control unit 60 and the power supply voltage conversion unit 100 It is. The power supply voltage sensing circuit 200 includes a first reference voltage generator 20, a sense amplifier 30, a comparison voltage generator 50, a latch unit 70, and a pulse generator 80. It is composed. The first reference voltage Vref generated from the first reference voltage generator 20 is supplied to the sensing amplifier 30, the comparison voltage generator 50, and the second reference voltage generator 90. On the other hand, the pulse generator 80 is Enter master clock øR The detection control signal øDETEN and the latch control signal øRP are generated to indicate that the controller has entered an active cycle. The signals? DETEN and? RP have different pulse widths. The sense control signal? DETEN is applied to the comparison voltage generator 50 and the sense amplifier 30, and the latch control signal? RP is supplied to the latch unit 70. The comparison voltage generator 50 inputs the first reference voltage Vref and sends the comparison voltage Vcomp generated by the control of the sensing control signal? DETEN to the sensing amplifier 30. The sensing amplifier 30 compares the potential of the comparison voltage Vcomp with the reference voltage Vref, and then outputs the sensing voltage signal? VCCD which amplifies the potential difference to the latch unit 70. The sensing voltage signal? VCCD is latched by the latch unit 70 and then output as the power supply voltage detection signal? DET and supplied to the power supply voltage converting unit 100. The conversion control unit 60 A master clock? R is input to generate first and second conversion control signals? ENPB and? ENPBP for controlling the enable / disable of the power supply voltage converter 100. The second reference voltage generator 90 inputs the first reference voltage Vref to generate a second reference voltage Vrefp that is more stable with respect to temperature and process changes than the first reference voltage Vref, and supplies the same to the power voltage converter 100. . The internal power supply voltage Vccp corrected through the power supply voltage converter 100 is made.

FIG. 3 shows a specific embodiment of each element constituting the power supply voltage sensing circuit 200 of FIG.

In the first reference voltage generator 20 of FIG. 3 (a), resistors R1 and R2 and PMO transistors M1 and M2 are connected in series between the power supply voltage Vcc and the ground voltage Vss. The gate of the CMOS transistor M1 is connected to a node 21 between the resistors R1 and R2, and a first reference voltage Vref is generated from the node 21. A PIO transistor M2 having a gate connected to the drain node 22 of the NMOS transistor M1 is connected between the node 21 and the ground voltage Vss. When the power supply voltage Vcc changes, the level of the first reference voltage Vref also changes accordingly. When the potential of the power supply voltage Vcc rises to the level that turns on the MOS transistor M1, the potential of the drain node 22 is lowered by the current flowing to the ground voltage Vss through the channel of the MOS transistor M1. By this, the PIO transistor M2 is turned on and the potential of the first reference voltage Vref of the node 21 is lowered until the voltage pull-down path through the PIO transistor M2 is cut off. On the contrary, when the potential of the power supply voltage Vcc is low, the turn-on resistance of the MOS transistor M1 is increased so that the first reference voltage Vref is pulled up through the resistor R1 and its potential is increased. . That is, the first reference voltage Vref is generated at a low level when the power supply voltage is high, and at a high level when the power supply voltage is low. Here, it should be noted that the configuration of the reference generation circuit as shown in FIG. 3 (a) has a compensating effect on temperature change. In other words, M1, an MOS transistor, has a channel resistance (or threshold voltage) due to an increase in the channel region of holes, which are thermally generated minority carriers, when the temperature rises. Since the channel resistance (or the threshold voltage) is inversely proportional to temperature in M2, which is a PIO transistor, even when the temperature rises or falls, a first reference voltage Vref having a relatively stable potential may be generated.

In the comparison voltage generation unit 50 shown in FIG. 3 (b), the NMO transistors M4, M5, and M6 are connected in series between the power supply voltage Vcc and the ground voltage Vss. Gates of the PMO transistor M4 and the NMO transistor M5 are connected to the first reference voltage Vref generated from the first reference voltage generator 20 of FIG. The gate of the NMOS transistor M6 connected to the ground voltage Vss is described above. The detection control signal øDETEN made from the master clock øR is applied. The PMO transistor M4 and the NMO transistor M5 constitute one complementary-MOS inverter, and the output of the inverter becomes a comparison voltage Vcomp, which is an inverted signal of the first reference voltage Vref. The potential of the comparison voltage Vcomp varies depending on the value of each transistor of the transistors M4 and M5 constituting the inverter, that is, W (channel width): L (channel length). In the comparison voltage generation unit 50 of FIG. 3 (b), it operates only when the sensing control signal? DETEN is applied to the gate of M6 at a high level.

The sensing amplifier 30 shown in FIG. 3 (c) employs a differential amplifier which is a current mirror of a p-channel input type. The first reference voltage Vref and the comparative voltage Vcomp are applied to the gates of the PMO transistors M7 and M8, respectively, and the sources of the M7 and M8 are connected to the power supply voltage Vcc. Enmotransistors M9 and M10 connected between the drain and pull-down node 33 of the PMO transistors M7 and M8 are formed in a latch form, and the pull-down node 33 and the ground voltage Vss are described above. One Enmotransistor M11, which receives the signal øDETEN made from the master clock øR, is connected. At the output node 32 connected with the gate of M9 and connected to the drains of M8 and M10, a sense voltage signal? VCCD is generated according to the potential difference between the first reference voltage Vref and the comparison voltage Vcomp. The sensing voltage signal? VCCD inputs the amount of current flowing through the PMOS transistor M7, which inputs the first reference voltage Vref, to the node 31 (node connected to the drain of M7 and M9 and connected to the gate of M10) and the comparison voltage Vcomp. It is determined by the relative difference in the amount of current flowing to the output node 32 through the PMOS transistor M10. For example, if the potential of the comparison voltage Vcomp is greater than the potential of the first reference voltage Vref (note that the magnitude of the potential here is an absolute value), the amount of current through M7 is the amount of current through M8. By more, the voltage of the output node 32 is pulled down through M10 so that the logic of the sense voltage signal? VCCD is at a low level. On the contrary, when the potential of Vref is greater than the potential of Vcomp, the? VCCD is generated in a high level logic state.

3 (d) shows a detailed circuit of the pulse generator 80. Shown in FIG. Generated from the control unit 10 The master clock øR is shaped to a predetermined pulse width by a first pulse shaping circuit consisting of three inverters 81, 82 and 83, and a NAND gate 84, and then through the inverter 85. It is made of detection control signal øDETEN. This øDETEN serves to control the enable / disable of the sense amplifier 30 and the comparison voltage generator 50 as described above, and this signal is used to detect the sense amplifier 30 and the comparison voltage generator 50. By controlling the driving of the circuit, the stand-by currnet is reduced. Also above The master clock øR is shaped to a predetermined pulse width by a second pulse shaping circuit composed of the inverter 86 and the NAND gate 87 (shaping to a shorter pulse width than in the case of the first pulse shaping circuit described above). Through the 88, the latch control signal? RP for controlling the signal transmission in the latch portion 70 of FIG.

3 (e) shows an embodiment of the latch unit 70. As shown in FIG. The voltage signal? VCCD generated from the sense amplifier 30 and input to the latch unit 70 includes a latch 78 composed of a transfer gate 73, a closed circuit having two inverters 74 and 75, Through the inverters 76 and 77, it is output as the power supply voltage detection signal? DET. The transfer gate 73 is of CMOS type, and its gating operation is controlled by the latch control signal? RP generated from the pulse generator 80. The latch 78 operates only while the sensing amplifier 30 generating the sensing voltage signal? VCCD operates only while the sensing control signal? DETEN is at a high level. Therefore, the latch 78 outputs the sensing voltage signal? VCCD which is output while the? DETEN is active at a high level. It is a means for keeping it in that state. In addition, since the potential of the sensing voltage signal? VCCD is difficult to maintain the full Vcc or the full Vss potential in a specific power supply voltage range, an uncertain sensing voltage is determined using two inverters 76 and 77 connected in series. The potential of the signal? VCCD can be stabilized. Since the pulse width of the latch control signal? RP for controlling the transfer gate 73 to temporarily store the sense voltage signal? VCCD in the latch 78 is sufficient as long as the sense voltage signal? VCCD is at a constant potential. The enable period of the high level state is shorter than the pulse width of the above-described sense control signal? DETEN.

The power supply voltage detection signal? DET becomes the final output of the power supply voltage detection circuit 200 and is input to the power supply voltage conversion unit 100 of FIG.

The second reference voltage generator 90 of FIG. 4 (a) includes a differential amplification circuit 96 which is an n-channel input type current mirror composed of PMO transistors M12 and M13, NMOS transistors M14, M15, and M16; A sensing circuit 97 composed of PMOS transistors M18 and M19 and PMOS transistor M17 used for driving the second reference voltage Vrefp. The first reference voltage Vref is applied to the gates of the M14 and the M16. Since M16 is used for pulldown connected to the ground voltage Vss, the differential amplification circuit 96 can be turned on only when the first reference voltage Vref is above a predetermined potential (above the threshold voltage of M17). do. M18 and M19 of the voltage divider 97 are connected in series between the second reference voltage terminal 94 and the ground voltage Vss. Each of them is connected in the form of a two-terminal diode. The sensing node 95 located between M18 and M19 is connected to the gate of the EnMOS transistor M15 of the differential amplifier circuit 96. This feedback connection stabilizes the potential of the second reference voltage Vrefp. The driving PMO transistor M17 is connected between the power supply voltage Vcc and the second reference voltage terminal 94, and the output node 93 of the differential amplifier circuit 96 is connected to the gate of the PMO transistor M27. have. Therefore, when the potential of the first reference voltage Vref is input at a level (high level) at which the Enmo transistors M14 and M16 are turned on (high level), the potential of the second reference voltage Vrefp is Vcc + 2V _TP (V _TP is a voltage divider circuit. The threshold voltage of the formed PIO transistor. On the contrary, when the potential of the first reference voltage Vref is input at a level (low level) that does not turn on the Enmo transistors M14 and M16, the output potential of the differential amplifier 96 is raised to a high level, so that the second reference voltage Vrefp is increased. Is maintained at 2V _TP . The second reference voltage Vrefp is supplied to the power supply voltage converter 100 shown in FIG.

4 (b) the conversion control unit 60, An inverter 62 for inputting the master clock øR to generate the first conversion control signal øENPB; A current mirror 61 for inputting the master clock? R and an inverter 64 for inverting the output of the current mirror 61 to generate the second conversion control signal? ENPBP. The current mirror 61 has a source connected in common to the power supply voltage Vcc, and a channel is connected between the PMO transistors M20 and M21 cross-coupled with each other, and the drain and ground voltage Vss of the PMO transistor M20. Being A channel is connected between the NMOS transistor M22 having a gate connected to the master clock øR, and the drain of the PMOS transistor M21 and the ground voltage Vss and passed through the inverter 63. It consists of Enmotransistor M23 whose gate is connected to the inverted signal of master clock øR. The first and second conversion control signals? ENPB and? ENPBP are signals for controlling the power supply voltage converting section 100 shown in FIG. 2, and have a logic level opposite to? R, and appear after being delayed from? R.

4 (c) shows the power supply voltage converting unit 100 for supplying the second reference voltage Vrefp, the power supply voltage detection signal? DET, and the first and second conversion control signals? ENPB and? ENPBP to maintain the potential of the internal power supply voltage Vccp. Show the detailed circuit. The channel of PIO transistor M27 used for output driving is connected between the power supply voltage Vcc and the internal power supply voltage terminal 104, and its gate is connected to the output node 105 of the differential amplifier circuit 160. The internal power supply voltage terminal 104 becomes one input of the differential amplifier circuit 160. The output of the inverter 110 for inverting the logic level of the first conversion control signal? ENPB is connected to one input of the NAND gate 120, and the power supply voltage detection signal? DET is connected to the type force of the NAND gate 120. The output of the NAND gate 120 is connected to the control node 101 through the inverter 130. The control node 101 is connected to a gate of the PMOS transistor M28 in which a channel is connected between the second reference voltage Vrefp and one input of the differential amplifier circuit 160. In addition, the control node 101 is connected to the gate of the NMOS transistor M31 having a channel connected between the one input of the differential amplifier circuit 160 and the ground voltage Vss. On the other hand, the output of the inverter 140 for inputting the power supply voltage detection signal øDET is connected to the gate of the PMO transistor M27 for output driving through the channel of the ENMO transistor M34 having the gate connected to the control node 101. Output node 105 of amplification circuit 160). A circular circuit of the inverter 140 and a detailed circuit thereof is provided to help understand the operation description described below. The differential amplification circuit 160 is an n-channel type having a basic configuration of PMO transistors M25 and M26 for loads and NMO transistors M30 and M32 for inputs, and is connected to the ground voltage through the ENMO transistor M33. . The gate of the NMO transistor M33 for ground connection is connected to the output of the NOA gate 150 for inputting the first conversion control signal? ENPB and the power supply voltage detection signal? DET. Between the drains of the input enmotransistors M30 and M32, a PIO transistor M29 having a gate connected to the output of the inverter 155 for inputting the second conversion control signal? ENPBP is connected. In addition, between the power supply voltage Vcc and the output node 105, a PIO transistor M24 having a gate connected to the output of the inverter 155 is connected.

The power supply voltage regulator operation according to the present invention will now be described with reference to the operation timing diagram shown in FIG. For the following description, it is preferable to refer to FIG. 2, 3 (a)-(e), and 4 (a)-(c) which were mentioned above. The device to which the present embodiment is applied is a low power semiconductor memory device using 3.3V as an internal power supply voltage. Thus, as shown in FIG. 5, the power supply voltage regulation for each of the case where the potential of the power supply voltage Vcc is raised to 3.6V (hereinafter referred to as HVCC) and the case where it is lowered to 3.0V (hereinafter referred to as LVCC) The process will be explained. In addition to the operation according to the potential state of the power supply voltage, the semiconductor memory device is in an active mode, that is, a low address strobe signal. Is in an active cycle, and the semiconductor memory is in a stand-by mode, that is, the low address strobe signal. This embodiment will also apply to the case where is placed in a precharge cycle.

First, the case where the semiconductor memory device to which the present embodiment is applied is active while the power supply voltage is HVCC will be described.

Low address strobe signal Is active at a low level, Master clock øR is enabled at a high level. In the pulse generator 80 for inputting øR, a high delay after the øR passes through the corresponding delay times corresponding to the three inverters 81, 82, and 83 of the first pulse shaping circuit. Level detection control signal? DETEN is generated, and after the? R is activated, a delay time equivalent to the inverter 86 of the second pulse shaping circuit is passed, and a latch control signal? RP of a high level is generated.

When the sensing control signal? DETEN is enabled at a high level, the comparison voltage generator 50 of FIG. 3 (b) and the sensing amplifier 30 of FIG. 3 (c) operate. As can be seen from the Vcc waveform shown in FIG. 5, since the potential of the current internal power supply voltage Vcc is 3.6 V and is HVCC, the first reference voltage generator 20 of FIG. As the voltage Vcc is connected to the ground voltage Vss, the potential of the first reference voltage Vref is lowered through the channel of the PIO transistor M2. Note that the potential of the first reference voltage Vref is set to about 1.4V in this embodiment. Then, in the comparison voltage generator 50 of FIG. 3 (b), the first reference voltage Vref of about 1.4V is recognized as the low level, so that the high level comparison voltage Vcomp is generated. Currently, since the potential of the first reference voltage Vref is lower than the potential of the comparison voltage Vcomp, in the sense amplifier 30 of FIG. 3 (c), the potential of the output node 32 is the channel of the enmo transistors M10 and M11. It is pulled down through. Thus, as shown in FIG. 4, the sense voltage signal? VCCD is generated at a low level. It is understood that the period during which the sense voltage signal? VCCD is maintained at the low level is in accordance with the period during which the sense control signal? DETEN, which controls the driving of the sense amplifier 30, maintains the high level, as indicated by the arrow of FIG. Can be. That is, the comparison voltage generator 50 and the sense amplifier 30 may have a pull-down path to the ground voltage Vss only during the period when? DETEN is high level. The low-level sense voltage signal? VCCD is input to the latch portion 70 shown in Fig. 3E.

In the latch unit 70, the latch control signal? RP generated from the pulse generator 80 is applied at a high level to turn on the transfer gate 73, so that the sense voltage signal? VCCD is transferred to the transfer gate 73. ) Is stored in the latch 78 through the channel. When the sensing voltage signal? VCCD is stored in the latch 78, the latch control signal? RP is brought to the low level so that the transfer gate 73 is turned on again and the sensing voltage signal? VCCD of another level (for example, a high level). Unless is input, the power supply voltage detection signal? DET is kept at a low level, which is applied to the power supply voltage converter 100 shown in FIG. 3 (h) to indicate that the potential of the current internal power supply voltage is in the HVCC state. .

On the other hand, the second reference voltage generation section 90 in (operation 4 (a) refer to Fig.), The initial potential of the partial pressure of the node (95) (V _TP18 + V _TP19) / 2 [V _TP18 will coat agarose transistor M18 Is the threshold voltage, and V _TP19 represents the threshold voltage of the PMO transistor M19], the level 1.4V of the first reference voltage Vref is higher than the potential of the voltage dividing node 95. As it is easier, current flows from the output node 93 of the differential amplifier circuit 96 to the ground voltage Vss through the NMOS transistors M14 and M15. As the potential of the output node 93 is lowered, the second reference voltage terminal 94 is charged through the channel of the PIO transistor M17 for driving. When the potential of the charged second reference voltage terminal 94 rises above a predetermined level, that is, when the potential of the divided node 95 is higher than the first reference voltage Vref, the enmo transistor M15 is turned on. The potential of the gate node 91 of the PIO transistors M12 and M13 in the differential amplifier circuit 96 is lowered, thereby closing the channel of the PMOS transistor M17, so that the potential of the second reference voltage Vrefp does not increase any more. . The second reference voltage Vrefp generated at a constant potential by this adjusting action is supplied to the power supply voltage converting part 100 of FIG. 3 (h).

High state input to the conversion control unit 60 The master clock [Delta] R turns on the MOS transistor M22 of the current mirror 61 and turns on the MOS transistor of the inverter 63. Therefore, the potential of the output node 63 of the level shifter 61 becomes high level and the second conversion control signal? ENPBP is generated at the low level. On the other hand, the first conversion control signal? ENPB is generated at the low level by the inverter 62 to inform the power supply voltage converting section 100 of FIG. 4 (c) that the current chip is active. The period during which the first and second conversion control signals? EPPB and? ENPBP remain at a low level is The master clock is followed by the period that øR remains high.

Referring to FIG. 4 (c), the level state of signals currently input to the power supply voltage converting unit 100 is about 3.3 V in which the first reference voltage Vrefp is close to the potential of the power supply voltage Vcc currently used. The voltage sensing signal? DET is at the low level, and the first and second conversion control signals? ENPB and? ENPBP are at the same low level. Since the power supply voltage detection signal? DET is at the low level, the output of the NAND gate 120 is at the high level, so that the potential of the control node 101 is at the low level. Therefore, the second reference voltage Vrefp is charged to the gate of the enmotransistor M30 which is one input of the differential amplifier circuit 160 through the channel of the PMO transistor M28. At this time, the MOS transistor M31 connected between the gate of the MOS transistor M30 and the ground voltage Vss is turned off. In addition, since the MOS transistor M34 is turned off by the potential of the low-level control node 101, the path from the power supply voltage detection signal? DET to the output node 105 of the differential amplifier circuit 160 is cut off. In addition, since the power supply voltage detection signal? DET input to the noar gate 150 is at the low level, the first conversion control signal? ENPB in the low state makes the output of the noah gate 150 at a high level. At 160, the Enmoistor transistor M33, which is used for ground connection, is turned on so that the comparison circuit 160 can operate.

On the other hand, in the state where the second conversion control signal øENPBP is at a high level before being input to the low level, the PMO transistor M24 for precharge connected between the power supply voltage Vcc and the output node 105 of the differential amplifier circuit 160 is turned on. Then, the output node 105 is charged with a power supply voltage Vcc, and at the same time, an equalization PMO transistor M29 for turning on the output node 105 and the drain of the ENMO transistor M32 is turned on. Then, the drain potentials of the MOS transistor M30 which receives the second reference voltage Vrefp as the gate and the MOS transistor M32 which receives the current internal power supply voltage Vccp as the gate start from a state at the same potential, and thus the relative potential difference between the Vrefp and Vccp. As a result, their potentials are different from each other. In addition, since the gate of the PMO transistor M27 for output driving is connected to the output node 105, the charging path from the power supply voltage Vcc to the internal power supply voltage Vccp is cut off and the internal power supply voltage Vccp does not increase any more. The operation of the PMO transistors M24 and M29 by the øENPBP allows the power supply voltage conversion circuit 100 of FIG. 4 (c), which is the final voltage comparison step, to quickly and reliably change the current internal power supply voltage Vccp. It should be noted that this part contributes to the means for making a good detection. After øENPBP becomes low level, PIO transistors M24 and M29 are turned off, so that the differential amplifier circuit 160 operates normally. As assumed above, since the potential of the current internal power supply voltage Vcc is 3.6 V and HVCC, more current flows out through the M32 channel than the M30 channel to the ground voltage Vss. As the potential of the node 106 which is the drain of M32 is lowered, the PIO transistor M25 connected to the power supply voltage Vcc is turned on. As a result, the output node 105 of the differential amplifier circuit 160 is connected to the power supply voltage Vcc through two voltage pull paths, that is, the channels of M24 and M25, so that the potential of the output node 105 is at the full-Vcc level. To rise. Then, the | Vgs | value of the PMO transistor M27 for output driving becomes small. Therefore, the capacitance between the gate and the channel of M32 until the potential of the second reference voltage Vrefp is reached without increasing the internal power supply voltage Vccp in the HVCC state. discharged through capacitance).

The chip is in a stand-by state (or low address strobe signal) when the supply voltage Vcc is HVCC. Is high level When in the precharge cycle, the sensing control signal? DETEN is applied to the sensing amplifier 30 and the comparison voltage generating section 50 at a low level, and the latch control signal? RP is applied to the latch section 70 at a low level. The first and second conversion control signals? ENPB and? ENPBP are applied to the power supply voltage converter 100 at a high level (where? ENPBP precharges and equalizes the output of the differential amplifier circuit 160). The power supply voltage detection signal? DET is still at the low level because the current Vcc is in the HVCC state.

Accordingly, the sense amplifier 30 and the comparison voltage generator 50 controlled by the sense control signal? DETEN are in a disabled state. In addition, since the latch control signal? RP is at a low level, the transfer gate 73 of the latch portion 70 is blocked. In the power supply voltage conversion unit 100, the differential amplification circuit 160 is generated by the output of the NOA gate 150 that controls the EnMOS transistor M33 connected to the ground voltage Vss at a low level in the differential amplification circuit 160. Is placed in the disabled state. In addition, since the potential of the control node 101 is at the low level, the MOS transistor N31 connecting the gate and the ground voltage of the MOS transistor M30 is in a turn-off state as in the case described above. As a result, when the semiconductor memory device is in the standby state while the power supply voltage is in the state of HVCC, the power supply voltage regulating operation does not need to be performed. Therefore, the circuit elements constituting the power supply voltage regulator according to the present invention do not consume unnecessary power. It can be seen that the current consumed in the standby state can be removed.

Next, when the power supply voltage Vcc is in the LVCC state of 3.0 V to 3.0 V, the power supply voltage conversion operation according to the present invention will be described.

First, when the semiconductor memory device to which the embodiment of the present invention is applied is placed in an active state, that is, a low address strobe signal Let's consider the case where is in the active cycle at the low level. Is in an active cycle, The master clock? R is at a high level, and a high level detection control signal? DETEN and a latch control signal? RP are generated from the pulse generator 80 of FIG. The first and second conversion control signals? ENPB and? ENPBP are at a low level. Referring to FIG. 3 (a), in the first reference voltage generator 20, the potential of the node 21 after the voltage drop of 3.0 V of the power supply voltage Vcc is dropped by the resistor R1 causes the potential of the transistor 21 M1 to be morphosistor M1. Since it is not turned on, the pull-down of the first reference voltage Vref through the channel of the PMO transistor M2 is not performed. Therefore, the potential of the first reference voltage Vref at this time is charged through the resistor R1. The potential appears as a high level. As a result, the comparison voltage Vcomp is generated at the low level from the comparison voltage generator 50 of FIG. 3 (b), and thus, the sense voltage signal? VCCD generated from the sense amplifier 30 of FIG. The potential goes high. In the latch portion 70 of FIG. 3 (e), the high voltage detection voltage signal? VCCD is stored as the latch 78 while? RP as the latch control signal becomes high level. It outputs the stable high level power supply voltage detection signal ø DET through. The timing at which the voltage detection signal? DET becomes high level depends on the timing at which the latch control signal? RP becomes high level. On the other hand, since the first reference voltage Vref is supplied at a high level in FIG. 4 (a), the second reference voltage Vrefp is charged to the level of Vcc + 2V _TP by the power supply voltage pull operation of the PIO transistor M17.

Referring to FIG. 4 (c), the level of the signals currently input to the power supply voltage converter 100 has the power supply voltage detection signal? DET at a high level, and the first and second conversion control signals? ENPB and? ENPBP are the same. It is low level. Since the first conversion control signal? ENPB is at a low level and the power supply voltage detection signal? DET is at a high level, the output of the NAND gate 120 is at a low level, and the potential of the control node 101 is at a high level. Accordingly, the PMO transistor M28 is turned off, and the MOS transistor M31 connected between the gate and the ground voltage Vss of the MOS transistor M30, which is one input of the differential amplifier circuit 160, is turned on. Since the ENMO transistor M34 is turned on by the potential of the high-level control node 101, a current path is formed between the power supply voltage detection signal? DET and the output node 105 of the differential amplifier circuit 160. At this time, the differential amplification circuit 160 is operated by turning off the NMOS transistor M33 used for ground connection because the output of the NOA gate 150 is turned low by the power supply voltage detection signal? DET of a high level. I never do that.

Here, referring to FIG. 4 (c), the circular portion of the inverter 140 for inputting the power supply voltage detection signal? DET is referred to. The inverter 140 includes the PMO transistor 141 and the ENMO transistor 142. It is composed of CMOS inverter connected between internal power supply voltage Vccp and ground voltage Vss. Since the current power supply voltage detection signal? DET is at a high level, the enMOS transistor 142 in the inverter 140 is turned on. Then, as described above, Enmotransistor M34 is turned on. As the gate of the PMO transistor M27 for output driving is connected to the ground voltage Vss through the channel of the ENMO transistor M34 and the channel of the ENMO transistor 142 of the inverter 140, the gate of the PMO transistor M27 The potential is pulled down to ground voltage. As a result, the | Vgs | value of the PMO transistor M27 for output driving becomes large, so that the potential of the internal power supply voltage terminal 140 rises. The ground voltage Vss to which the inverter 140 is connected serves as a current sink for the gate of the PMO transistor M27.

Here, in the conventional case, as can be seen from FIG. 1, the turn-on level of the PMO transistor M _D for output driving only in accordance with the potential difference between the reference voltage V _L1 and the current power supply voltage V _L2 , that is, | Mgs | While the magnitude is determined, it should be noted that in the present invention, as described above, the gate of the PMO transistor M27 for output driving is absolutely connected to the ground voltage according to the standardized logic of? DET in the power supply voltage detection signal. The pull-down operation of the gate potential of the PMO transistor M27 is performed by the low address strobe signal as shown in the timing diagram of FIG. Enters the precharge cycle signal in a high state, and then ends after a predetermined time when the first conversion control signal? ENPB transitions from a low level to a high level.

On the other hand, in addition to the gate potential pull-down action of the PMO transistor M27 for output driving as described above, there is another action that contributes to the potential rise of the internal voltage terminal 104. By the low level second conversion control signal? ENPBP, the PMO transistor M24 connected between the power supply voltage Vcc and the output node 105 of the differential amplification circuit 160 is turned on and the drain of the output node 105 and the ENMO transistor M32 is turned on. The PIO transistor M29 that connects to is turned on. As a result, the drain potential of the MOS transistor M32 becomes Vcc level, and the internal power supply voltage terminal 104 can be raised by the capacitance between the drain and the gate of the MOS transistor M32. This is possible because the NMO transistor M33 for ground connection which can operate the differential amplifier circuit 160 is turned off and the source electrode of the M32 is opened. As a result, in the LVCC state, the internal power supply voltage Vccp is charged by the channel of the PMO transistor M27 having a sufficient capacity of | Vgs | and the drain-gate capacitance of the ENMO transistor M32. It can be seen that the power supply voltage can be restored.

In the LVCC state, the semiconductor memory to which the present embodiment is applied is in a standby state (low address strobe signal). Is high level In the precharge cycle), the sensing control signal? DETEN is applied to the sensing amplifier 30 and the comparison voltage generating section 50 at a low level, and the latch control signal? RP is applied to the latch section 70 at a low level. And the first and second conversion control signals? ENPB and? ENPBP are applied to the power supply voltage converter 100 at a high level. The power supply voltage detection signal? DET is still at a low level because the current Vcc is in the HVCC state. Accordingly, the sense amplifier 30 and the comparison voltage generator 50 controlled by the sense control signal? DETEN are in a disabled state. In addition, since the latch control signal? RP is at a low level, the transfer gate 73 of the latch portion 70 is blocked. In the power supply voltage converting unit 100, the differential amplification circuit 160 is generated at a low level by the output of the NOA gate 150 that controls the EnMOS transistor M33 connected to the ground voltage Vss in the differential amplifying circuit 160. Is placed in the disabled state. In addition, since the potential of the control node 101 is at the low level, the MOS transistor M31, which connects the gate of the MOS transistor M30 and the ground voltage, is turned off as in the case described above. After all, even if the power supply voltage is in the LVCC state, when the semiconductor memory device is in the standby state, the power supply voltage regulating operation does not need to be performed. It can be seen that the current consumed in the standby state can be eliminated by avoiding it.

From the pulse generator 80 of FIG. 3 (d) and the timing diagram of FIG. 5, the sensing control signal? DETEN and the latch control signal? RP for controlling the operation of the power supply voltage sensing circuit 200 of FIG. Since the voltage is enabled with a constant pulse width in accordance with the enable of the master clock øR, the power supply voltage sensing circuit 200 is a low address strobe signal. Note that it only operates at the beginning of the active cycle. This allows power to be consumed only for a minimum amount of time to detect the potential of the supply voltage, even during supply voltage regulation operation.

The pulse widths of øDETEN and øRP may be variously set by adjusting the number of inverters of the pulse shaping circuit of FIG. 3 (d).

On the other hand, when the voltage level of the internal power supply voltage Vccp drops while the power supply voltage Vcc is low due to the configuration of the power supply voltage converter 100 of FIG. It is shown in (a). FIG. 6 (a) is another embodiment of the power supply voltage converting unit 100. Compared to FIG. 4 (c), the dotted line block 170 for controlling the gate of the PMO transistor M27 is different in structure, and at the same time, the sixth It is a characteristic of the structure of (a). The configuration of the dotted block 170 is terminated when the output node 105 of the differential amplifier circuit and the gate signal? ENPB of the PMOS transistor M27 transition from a low level to a high level.

On the other hand, there is another action that contributes to the gate potential pull-down action of the PMO transistor M27 for output driving as described above and the potential rise of the internal voltage terminal 104. By the low level second conversion control signal? ENPBP, the PMO transistor M24 connected between the power supply voltage Vcc and the output node 105 of the differential amplification circuit 160 is turned on and the drain of the output node 105 and the enmo transistor M32 is turned on. The PIO transistor M29 that connects to is turned on. As a result, the drain potential of the MOS transistor M32 becomes Vcc level, and the internal power supply voltage terminal 104 can be raised by the capacitance between the drain and the gate of the MOS transistor M32. This is possible because the NMO transistor M33 for ground connection which can operate the differential amplifier circuit 160 is turned off and the source electrode of the M32 is opened. As a result, in the LVCC state, the internal power supply voltage Vccp is charged by the channel of the PMO transistor M27 having a sufficient capacity of | Vgs | and the drain-gate capacitance of the ENMO transistor M32. It can be seen that the power supply voltage can be restored.

In the LVCC state, the semiconductor memory to which the present embodiment is applied is in a standby state (low address strobe signal). Is high level In the precharge cycle), the sensing control signal? DETEN is applied to the sensing amplifier 30 and the comparison voltage generating section 50 at a low level, and the latch control signal? RP is applied to the latch section 70 at a low level. And the first and second conversion control signals? ENPB and? ENPBP are applied to the power supply voltage converter 100 at a high level. The power supply voltage detection signal? DET is still at the low level because the current Vcc is in the HVCC state. Accordingly, the sense amplifier 30 and the comparison voltage generator 50 controlled by the sense control signal? DETEN are in a disabled state. In addition, since the latch control signal? RP is at a low level, the transfer gate 73 of the latch portion 70 is blocked. In the power supply voltage converting unit 100, the differential amplification circuit 160 is generated at a low level by the output of the NOA gate 150 that controls the EnMOS transistor M33 connected to the ground voltage Vss in the differential amplifying circuit 160. Is placed in the disabled state. In addition, since the potential of the control node 101 is at the low level, the MOS transistor M31, which connects the gate of the MOS transistor M30 and the ground voltage, is turned off as in the case described above. After all, even if the power supply voltage is in the LVCC state, when the semiconductor memory device is in the standby state, the power supply voltage regulating operation does not need to be performed. It can be seen that the current consumed in the standby state can be eliminated by avoiding it.

From the pulse generator 80 of FIG. 3 (d) and the timing diagram of FIG. 5, the detection control signal? DETEN and the latch control signal? RP controlling the operation of the power supply voltage sensing circuit 200 of FIG. Since the voltage is enabled with a constant pulse width in accordance with the enable of the master clock øR, the power supply voltage sensing circuit 200 is a low address strobe signal. Note that it only operates at the beginning of the active cycle. This allows power to be consumed only for a minimum amount of time to detect the potential of the supply voltage, even during supply voltage regulation operation.

In addition, the pulse widths of? DETEN and? RP may be variously set by adjusting the number of inverters of the pulse shaping circuit of FIG.

Meanwhile, when the voltage level of the internal power supply voltage Vccp drops while the power supply voltage Vcc is low by modifying the configuration of the power supply voltage converter 100 of FIG. It is shown in (a). FIG. 6 (a) is another embodiment of the power supply voltage converting unit 100. Compared to FIG. 4 (c), the dotted line block 170 for controlling the gate of the PMO transistor M27 is different in structure, and at the same time, the sixth It is a characteristic of the structure of (a). The dotted block 170 has a transmission gate 164 as a switching transistor for forming a channel between the output node 105 of the differential amplifier circuit and the gate terminal of the PMOS transistor M27, and for inputting the power supply voltage sensing circuit? DET. A channel is formed between the gate terminal of the PMO transistor M27 and the ground voltage Vss, and is formed of the ENMO transistor 166 which gate-inputs the power supply voltage detection signal? DET through the inverter 162. In FIG. 6A, inverters 172 and 174 for inputting the first conversion control signal? ENPB to the internal power supply voltage terminal 104 are provided. In FIG. 6 (a), the? DET issuing circuit serving as the latch unit for outputting the power supply voltage detection signal? DET was performed as in FIG. 6 (b). The configuration of the øDET generation circuit of FIG. 6 (b) includes the PMO transistor 176 which inputs the internal power supply voltage Vccp as the source power source and the gate input of the reference voltage Vrefp, and the drain terminal is connected to the drain terminal of the PMO transistor 176. The MOS transistor 182 for gate input of the voltage Vrefp, the drain terminal connected to the source terminal of the MOS transistor 180, and the MOS transistor 182 for gate input of the first conversion control signal øENPB through the inverter 186, and the MOS transistor 182 An input terminal is connected to an output node 178 where a gate terminal and a drain terminal are commonly connected to a source terminal, and a source terminal is connected to a ground voltage Vss terminal, and an output node 178 where a PMO transistor 176 and an enmo transistor 180 are commonly connected. And amplification circuits 188 and 190 for outputting a power supply voltage detection signal? DET. The configuration characteristic of FIG. 6 (b) is that the level can be detected easily and at high speed by inputting the internal power supply voltage Vccp to the source power supply. 6 (c) is an operation timing diagram of FIG. 6 (a). An operation characteristic according to the configuration of the power supply voltage converting unit as still another embodiment shown in FIG. 6 (a) is as follows. In FIG. 6 (a), the operation characteristics of the components except for the dashed block 170 are the same as those of FIG. 4 (c), and the description thereof is omitted. The configuration characteristic of the sixth (a) can be summarized into two things. One is that the recovery can be performed at a high level at a low level of the internal power supply voltage Vccp, so that the operating speed of each circuit in the chip can be brought at a high speed. There is an advantage. In detail, if the voltage level of the internal power supply voltage Vccp drops even a little, the reference voltage Vrefp in FIG. 6 (b) is a constant voltage signal having a constant voltage level. The response to the dropped level is immediately apparent. Therefore, the power supply voltage detection signal? DET is immediately outputted to the low level through the amplification circuits 188 and 190. From this, the transmission gate 164 is turned off and the node 168 is turned on. Through 166, the ground level Vss is obtained. In response, the internal power supply voltage Vccp immediately rises through the turn-on of the PIO transistor M27 to compensate for the previously fallen level. Another configuration feature of FIG. 6 (a) is a configuration for outputting the internal power supply voltage Vccp at high speed during power-up. This may refer to FIG. 6 (c), which is an operation timing of power-up of FIG. 6 (a). That is, since the voltage level of the internal power supply voltage Vccp corresponding to the voltage level of the power-shutdown reference voltage Vrefp is low in FIG. 6 (b), the power supply voltage detection signal? DET immediately goes low, and thus, in FIG. The node 168 becomes the ground level, from which the internal power supply voltage Vccp immediately rises in proportion to the supply of the power supply voltage Vcc. 7 (a) and 7 (b) are waveform diagrams showing simulation results according to the Vccp signal and the power supply voltage detection signal? DET signal. Referring to FIG. 7 (a), it can be seen that even if the internal power supply voltage Vccp becomes 3.1V, for example, about 0.2V from 3.3V, the voltage is immediately restored to 3.3V by detecting it.

The above embodiments are applied to the semiconductor memory using 3.3 V as the potential of the power supply voltage Vcc, but the present invention is not limited to the above embodiments. That is, it is common in the art to apply the spirit of the present invention to a semiconductor integrated circuit (VLSI) requiring a constant internal power supply voltage or other semiconductor memory device using a power supply voltage higher or lower than 3.3V. It should be noted that it is possible for those who have the knowledge of.

As described above, the present invention has an effect of securing sufficient driving capacity in stabilizing the potential of the internal power supply voltage which fluctuates unstable in a semiconductor integrated circuit such as a memory device using a low power supply voltage. In addition, the present invention has an advantage in that, in a semiconductor integrated circuit such as a memory device, the potential of the current internal power supply voltage which is in a state lower or higher than the normal potential can be restored to the normal potential faster than before. Furthermore, the present invention reduces the unnecessary power consumption by detecting the potential of the current power supply voltage only at the beginning of the period in which the semiconductor integrated circuit such as a memory device employing a low power supply voltage is active, thereby reducing the amount of power consumed in detecting the power supply voltage level. Can be minimized.

Claims (17)

An output drive transistor of an insulated gate field effect type using a power supply voltage having a constant potential and having a channel connected between the internal power supply voltage and the power supply voltage, and having a gate potential controlled according to a power supply voltage detection signal and a conversion control signal; An integrated circuit having a differential amplifier circuit having an output node connected to a gate of an output driving transistor and having a first input terminal connected to the internal power supply voltage terminal, the integrated circuit comprising: a control node whose potential is determined according to a power supply voltage sensing signal and a conversion control signal; An insulated gate field effect type fast transistor having a gate connected to the control node and a channel connected between a gate of the output driving transistor and a current sink, and a channel connected between the gate of the output driving transistor and the power supply voltage and the conversion An insulated gate field effect type first pull transistor having a gate connected to the control signal; An insulated gate field effect type equalization transistor having a channel connected between a drain of the MOS transistor and an output node of the differential amplifier circuit, the gate of which is connected to a pre-conversion control signal and the gate of the first input terminal of the differential amplifier circuit; A pull-down transistor of an insulated gate field effect type having a channel connected between the second input terminal of the differential amplifier and a ground voltage and a gate connected to the control node, and complementary to the pull-down transistor; A second pull transistor of an insulated gate field effect type having a channel connected between a reference voltage set according to a potential of the second amplifier and a second input terminal of the differential amplifier circuit and a gate connected to the control node, wherein the power supply voltage is constant. If the potential is higher than that, the gate of the output driving transistor is connected to the channel of the first pull transistor. The power supply voltage and the gates of the load transistors of the differential amplifier circuit, a second input terminal of the differential amplifier circuit is connected to the reference voltage through the channel of the second pull transistor, and the power supply voltage is constant. When the potential is lower than that, the gate of the output driving transistor is connected to the current sink through the channel of the fast transistor, and the second input terminal of the differential amplifier circuit is connected to the ground voltage through the channel of the pull-down transistor. Integrated circuits. The method of claim 1, wherein the differential amplification circuit is connected to the ground voltage through a channel of an insulated gate field effect transistor, and the insulated gate field effect transistor is formed when the power supply voltage is above a predetermined potential when the integrated circuit is active. Integrated circuit, characterized in that turned on. The integrated circuit of claim 1, wherein the current sink is connected to a channel of the fast transistor through a channel of an N type insulating gate field effect transistor receiving the power voltage sensing signal as a gate. 4. The integrated circuit of claim 3, wherein a type of insulated gate field effect transistor receiving the power supply voltage sensing signal as a gate is connected between the channel of the N-type insulated gate field effect transistor and the power supply voltage. An output drive transistor of an insulated gate field effect type using a constant level power supply voltage, a channel being connected between an internal power supply voltage and the power supply voltage, and having a gate potential controlled according to the power supply voltage detection signal and the conversion control signal; An integrated circuit having a differential amplifier circuit having an output node connected to a gate of the output driving transistor and having an internal power supply voltage terminal connected to a first input terminal, the integrated circuit comprising: means for generating a master signal for detecting an active state of the integrated circuit; A first reference voltage generator for generating a first reference voltage according to a current potential state of the power supply voltage, a sensing control signal and a latch control signal having a pulse width at least shorter than that of the master signal in response to the master signal; A generated pulse generator and a voltage complementary to the first reference voltage and operating according to the sensing control signal; A sensing amplifier for inputting a first reference voltage to generate a sensing voltage signal, a latch for storing the sensing voltage signal and generating a power voltage sensing signal according to the latch control signal, and a potential of the first reference voltage A second reference voltage generator for generating a second reference voltage according to a state, a conversion control unit for generating a delayed control signal from the master signal in response to the master signal, and a power supply voltage detection signal and a conversion control signal A control node having a potential determined, an insulated gate field effect type fast transistor having a gate connected to the control node, and a channel connected between the gate and the current sink of the output driving transistor, the gate of the output driving transistor and the power supply voltage. A first pull transistor of an insulated gate field effect type having a channel connected therebetween and a gate connected to the conversion control signal And an insulated gate field effect type equalization transistor having a channel connected between the drain of the MOS transistor and the output node of the differential amplifier circuit, the gate of which is connected to the conversion control signal and the gate of the first input terminal of the differential amplifier circuit. A pull-down transistor of an insulated gate field effect type having a channel connected between the second input terminal of the differential amplifier and a ground voltage and connected to a gate of the control node, and a complementary operation of the pull-down transistor; And an isolated gate field effect type second pull transistor having a channel connected between a reference voltage and a second input terminal of the differential amplifier circuit and a gate connected to the control node. 6. The method of claim 5, wherein when the power supply voltage is below a predetermined potential, the gate of the output driving transistor is connected to a current sink through a channel of the fast transistor, and the second input terminal of the differential amplifier circuit is a channel of the pull-down transistor. Integrated circuit, characterized in that connected to the ground voltage through. 7. The method of claim 6, wherein the differential amplification circuit is connected to the ground voltage through a channel of an insulated gate field effect transistor, and the insulated gate field effect transistor is formed when the power supply voltage is above a predetermined potential when the integrated circuit is active. Integrated circuit, characterized in that turned on. 6. The integrated circuit of claim 5, wherein the current sink is connected to a channel of the fast transistor through a channel of an N type insulated gate field effect transistor receiving the power voltage sensing signal as a gate. 9. The integrated circuit of claim 8, wherein a type of insulated gate field effect transistor receiving the power supply voltage sensing signal as a gate is connected between a channel of the N-type insulated gate field effect transistor and the power supply voltage. An output drive transistor of an insulated gate field effect type using a constant level power supply voltage, a channel being connected between an internal power supply voltage and the power supply voltage, and having a gate potential controlled according to the power supply voltage detection signal and the conversion control signal; A semiconductor memory device having a differential amplifier circuit having an output node connected to a gate of the output driving transistor and having an internal power supply voltage terminal connected to a first input terminal, wherein the master signal is configured to detect an active state of a low address strobe signal. And a first reference voltage generator for generating a first reference voltage according to a current potential state of the power supply voltage, a sensing control signal and a latch having a pulse width at least shorter than that of the master signal in response to the master signal. A pulse generator for generating a control signal, and operating according to the detection control signal and performing the first reference A sensing amplifier for inputting a voltage complementary to the voltage and the first reference voltage to issue a sensing voltage signal, a latch unit for storing the sensing voltage signal and generating a power voltage sensing signal according to the latch control signal; A second reference voltage generator for generating a second reference voltage according to a potential state of the first reference voltage, a conversion controller for generating a delayed control signal from the master signal in response to the master signal, and the power voltage sensing signal And an insulating gate field effect type fast transistor having a control node whose potential is determined according to a conversion control signal, a gate connected to the control node, and a channel connected between a gate and a current sink of the output driving transistor, and the output driving transistor. An insulated gate field having a channel connected between the gate and the power supply voltage and a gate connected to the conversion control signal An insulating gate having a channel connected between the first pull-up transistor of an oversized type, a drain of the MOS transistor having a gate connected to the conversion control signal, and a gate connected to a first input terminal of the differential amplifier circuit, and an output node of the differential amplifier circuit. A field effect type equalization transistor, an insulated gate field effect type pulldown transistor having a channel connected between the second input terminal and the ground voltage of the differential amplifier circuit and a gate connected to the control node, and complementary to the pulldown transistor And an insulated gate field effect type second pull transistor having a channel connected between the second reference voltage and a second input terminal of the differential amplifier circuit and a gate connected to the control node, wherein the power supply voltage is constant. If the potential is higher than that, the gate of the output driving transistor is connected to the channel of the first pull transistor. The power supply voltage and the gates of the load transistors of the differential amplification circuit, a second input terminal of the differential amplification circuit is connected to the reference voltage through a channel of the second pull transistor, and the power supply voltage is a constant potential. In the following case, the semiconductor of the output driving transistor is connected to the current sink through the channel of the fast transistor, and the second input terminal of the differential amplifier circuit is connected to the ground voltage through the channel of the pull-down transistor Memory device. 11. The method of claim 10, wherein when the power supply voltage is below a predetermined potential, the gate of the output driving transistor is connected to the current sink through the channel of the fast transistor, the second input terminal of the differential amplifier circuit is the channel of the pull-down transistor The semiconductor memory device, characterized in that connected to the ground voltage through. 12. The method of claim 11, wherein the differential amplification circuit is connected to the ground voltage through a channel of an insulated gate field effect transistor, and the insulated gate field effect transistor is formed when the power supply voltage is above a predetermined potential when the integrated circuit is active. A semiconductor memory device, characterized in that turned on. The semiconductor memory device of claim 10, wherein the current sink is connected to a channel of the fast transistor through a channel of an N type insulating gate field effect transistor receiving the power voltage sensing signal as a gate. The semiconductor memory device according to claim 13, wherein a type of insulated gate field effect transistor receiving the power supply voltage sensing circuit as a gate is connected between the channel of the N-type insulated gate field effect transistor and the power supply voltage. An output drive transistor of an insulated gate field effect type that uses a power supply voltage having a constant potential, and a channel is connected between the internal power supply voltage and the power supply voltage, and the potential of the gate is controlled according to the power supply voltage detection signal and the conversion control signal; A semiconductor memory device having a differential amplifier circuit having an output node connected to a gate of a driving transistor and a first input terminal connected to the internal power supply voltage terminal, wherein the channel is provided between an output node of the differential amplifier circuit and a gate of an output driving transistor. And a channel is formed between the switching transistor for gate-input the power supply voltage sensing signal and a gate of the output driving transistor and the ground voltage terminal, and in response to the power supply voltage sensing signal, a gate potential of the output driving transistor is formed. Peninsula characterized by having a pull-down transistor for leveling ground Memory device. The method of claim 15, wherein the power supply voltage detection signal is a pull-up transistor for supplying the internal power supply voltage to a sensing node in response to a gate input of a predetermined reference voltage, and the sensing node in response to a gate input of the reference voltage. A channel is formed between the first pull-down transistor for pulling down the voltage and the first pull-down transistor and the ground voltage terminal, and in response to a gate input of the conversion control signal, the sensing node is connected through the channel of the first pull-down transistor. And a signal output from a power supply voltage sensing signal generation circuit each having a second pulldown transistor for pulling down a voltage. In a power supply voltage regulator of a semiconductor memory device using a power supply voltage of a predetermined level, an insulation in which a channel is connected between an internal power supply voltage and the power supply voltage and a potential of a gate is controlled according to the power supply voltage detection signal and the conversion control signal. An output driving transistor having a gate field effect type, an output node connected to a gate of the output driving transistor, a first amplifier connected to the internal power supply voltage terminal, and a potential according to a power supply voltage sensing signal and a conversion control signal. A control node of which the control node is determined, an insulated gate field effect type fast transistor having a gate connected to the control node, and a channel connected between the gate and the current sink of the output driving transistor, An insulated gate having a channel connected to it and a gate connected to the conversion control signal. A channel is connected between a first pull-up transistor of a system effect type, a drain of an MOS transistor having a gate connected to the conversion control signal, and a gate connected to a first input terminal of the differential amplifier circuit, and an output node of the differential amplifier circuit. An equalization transistor of an insulated gate field effect type, a pulldown transistor of an insulated gate field effect type having a channel connected between a second input terminal of the differential amplifier circuit and a ground voltage and a gate connected to the control node, and the pull-down transistor A second pull-out type of insulation gate field effect type, in which a channel is connected between a reference voltage set according to a current potential of the power supply voltage and a second input terminal of the differential amplifier circuit and a gate is connected to the control node, is operated complementarily. A transistor provided, when the power supply voltage is equal to or higher than a predetermined potential, a gate of the output driving transistor Is connected to the power supply voltage and the gates of the load transistors of the differential amplifier circuit through the channel of the first pull transistor, and the second input terminal of the differential amplifier circuit is connected to the reference voltage through the channel of the second pull transistor transistor. When the power supply voltage is below a predetermined potential, the gate of the output driving transistor is connected to the current sink through the channel of the fast transistor, the second input terminal of the differential amplifier circuit through the channel of the pull-down transistor And a power supply voltage regulator for the semiconductor memory device.