KR0119516Y1 - Variable velocity recording device - Google Patents

Abstract

The present invention relates to a variable speed recording apparatus for recording a variable speed according to the distribution characteristics of input data, and selecting a mode by inputting a selection signal generator that generates a mode selection signal according to the characteristics of the input data, a low speed clock and a high speed clock. A first selector selected according to the signal, an address generator that generates an address according to the output of the first selector, a second selector that inputs data and a fixed data value and outputs it according to the mode selection signal, and a low-speed write enable signal and a high speed The third selector which inputs the write enable signal and selects it according to the mode selection signal, and stores the input data in accordance with the low speed light enable signal (WE) in the address area generated according to the low speed clock in the low speed mode, and in the high speed mode. The data value fixed to the address area generated according to the fast clock CLK2 is transferred to the fast write enable signal / WE2. La and a memory to store.

Description

Variable speed recorder

1 is a block diagram showing a variable speed recording apparatus according to the present invention,

2a to 2c is an example of the input data structure used in the present invention,

3a to 3e are timing diagrams showing a low speed mode operation according to the present invention,

4A to 4E are timing diagrams showing a high speed mode operation according to the present invention.

* Explanation of symbols for main parts of the drawings

10,30,40: Multiplexer 20: Address generator

50: selection signal generator 60: memory

The present invention relates to a device for recording a series of data input from the outside, in particular, when writing a specific data in a continuous address space in succession, the write speed is changed according to the characteristics of the data to be recorded A variable speed recording apparatus.

Conventionally, when a series of data is input and recorded in the memory, it is stored in the memory according to a predetermined fixed clock regardless of the distribution characteristic of the input data. That is, conventionally, the input data is recorded according to a fixed clock speed regardless of whether the input data is continuous '1' or the continuous '0' or randomly '0' and '1'. Therefore, even when a continuous '0' or a continuous '1' is recorded in a predetermined address area, it is equal to the recording speed of random data. However, when the input data is a continuous '0' or a continuous '1', the speed can be improved by increasing the clock speed to record. In particular, in the general stage of using the memory, the memory space may be initialized to '0' or '1'.

Accordingly, an object of the present invention is to provide a variable speed recording apparatus in which a recording speed is improved by selecting a clock speed according to a distribution characteristic of input data.

In order to achieve the above object, the device of the present invention, in the variable speed recording apparatus for selecting the clock speed in accordance with the distribution characteristics of the input data to record in a continuous address space,

A selection signal generator for generating a mode selection signal according to the characteristics of the input data;

First selecting means for inputting a low speed clock and a high speed clock and selecting the low speed clock according to the mode selection signal;

An address generator for generating an address in accordance with the output of said first selecting means;

Second selection means for inputting data and a fixed data value and outputting the data in accordance with the mode selection signal;

Third selecting means for inputting a low speed light enable signal and a high speed light enable signal and selecting the low speed light enable signal according to the mode selection signal; And

In the low speed mode, input data is stored in the address area generated according to the low speed clock in accordance with the low speed write enable signal, and the data value fixed in the address area generated in accordance with the high speed clock in the high speed mode is stored in accordance with the high speed write enable signal. It is characterized by comprising a memory.

Hereinafter, the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a variable speed recording apparatus according to the present invention, and includes a first multiplexer 10, an address generator 20, a second multiplexer 30, a third multiplexer 40, and a selection signal generator 50. ) And a memory 60.

In FIG. 1, the selection signal generator 50 is constituted by a NOR gate.

In general, '0' and '1' are randomly distributed in the binary data. However, in the case of performing a specific function by using an initialization step or a table, '0' or '1' may be continuously recorded in the continuous address space of the memory. Examples of recording distribution characteristics of such input data are shown in FIGS. 2A to 2C. Referring to FIG. 2A, when input data is random, data of '1' and '0' is randomly stored at addresses '000H' to '7FFH' of the memory. In FIG. 2B, when a specific portion of the input data is all '0', '0' is continuously stored at addresses '500H' to '7FFH' of the memory. In FIG. 2C, when the input data is all '0', it can be seen that '0' is written in all of addresses '000H' to '7FFH' of the memory.

According to the present invention, when data is randomly stored as shown in FIG. 2A, the data is written using a predetermined low speed mode as in the prior art, and data of '0' or '1' is stored in consecutive address spaces of the memory as shown in FIGS. 2B and 2C. In the case of storing the data, the recording mode is changed to the high speed mode and the recording speed is improved.

In Fig. 1, the selection signal generator 50 composed of eight input noar gates outputs a high speed mode selection signal when all data input from the data buses D0 to D7 are '0' or '1'. If it is random, the low speed mode selection signal is output. That is, when the distribution characteristic of the input data is random as shown in FIG. 2a, the selection signal generator 50 outputs a low speed mode select signal. As shown in FIG. 2b and FIG. Otherwise, if '1', high speed mode selection signal is output. The first multiplexer 10 inputs a low speed clock CLK and a high speed clock CLK2. When the low speed mode selection signal is input, the first multiplexer 10 selects and outputs a low speed clock CLK. The address generator 20 has a counter therein and generates an address of a predetermined bit in accordance with an input clock. Therefore, the faster the clock speed, the faster the address generation speed. The second multiplexer 30 inputs the input data DATA and a predetermined fixed value ('0' or '1') to select the input data in the low speed mode and write the input data to the memory 60. In the high speed mode, Select and print a fixed value of '0' or '1'. The third multiplexer 40 inputs the low speed light enable signal / WE and the high speed light enable signal / WE2 to select and output the low speed light enable signal / WE in the low speed mode. In the high speed mode, the high speed write enable signal / WE2 is selected and output. The memory 60 stores the input data in the address area generated according to the low speed clock CLK in the low speed mode according to the low speed write enable signal / WE, and in accordance with the high speed clock CLK2 in the high speed mode. The data value '0' or '1' fixed in the generated address area is stored in accordance with the fast write enable signal / WE2.

The operation in the low speed mode and the high speed mode will now be described in detail with reference to the timing chart. In the embodiment of the present invention, if the mode selection signal SEL is 'low', it is a low speed mode.

3A to 3E are operation timing diagrams in the low speed mode.

3A shows the mode selection signal SEL, which is 'low' in the low speed mode. FIG. 3B shows the low speed clock CLK, and FIG. 3C shows the address ADR generated according to the low speed clock CLK. FIG. 3d shows the input data DATA, and FIG. 3e shows the low speed write enable signal / WE.

4A to 4E are operation timing diagrams in the high speed mode.

4A shows the mode selection signal SLE, which is 'high' in the high speed mode. 4B shows the fast clock CLK2, and FIG. 4B shows the address ADR generated according to the fast clock CLK2. 4C shows that data to be stored in the memory is fixed to '0'. If the fixed data is '1', it continues to show 'high'. 4E shows a fast write enable signal / WE2.

Comparing Figs. 3A to 3E with Figs. 4A to 4E, it can be seen that in the high speed mode, the recording speed is improved by storing predetermined data at a K-times higher than in the low speed mode.

As described above, when the input data including the continuous '1' or '0' is recorded in the memory, the recording speed is improved.

Claims (1)

11. A variable speed recording apparatus for selecting a clock speed according to a distribution characteristic of input data and recording the result in a continuous address space, comprising: a selection signal generator for generating a mode selection signal according to the characteristic of the input data; First selecting means for inputting a low speed clock and a high speed clock and selecting the low speed clock according to the mode selection signal; An address generator for generating an address in accordance with the output of said first selecting means; Second selection means for inputting data and a fixed data value and outputting the data in accordance with the mode selection signal; Third selecting means for inputting a low speed light enable signal and a high speed light enable signal and selecting the low speed light enable signal according to the mode selection signal; And store the input data according to the low speed write enable signal in the address area generated according to the low speed clock in the low speed mode, and store the data value fixed in the address area generated according to the high speed clock in the high speed mode according to the high speed write enable signal. And a memory for storing.