KR0117495Y1 - Exclusive xor circuit - Google Patents

Abstract

The present invention is the most basic circuit element of the logic circuit configuration, and relates to an exclusive OR circuit which is widely used in the construction of digital circuits. The present invention relates to an XOR circuit designed to reduce the area of a chip or the like, and to reduce power consumption. Since the XOR circuit can be configured with fewer components than a conventional configuration, the size of the circuit device to which the present invention is applied is reduced. It has an effect that can be miniaturized. Specifically, 16 MOS transistors are required when the XOR circuit is configured and used as the MOS transistor as shown in FIG. 1, but only 6 MOS transistors are required when the circuit is constructed and implemented according to the present invention. In manufacturing, there is an effect that can significantly reduce the area of the chip.

Description

Exclusive-OR circuit

1 is a configuration diagram of a conventional XOR circuit,

2 is a block diagram of an XOR circuit according to the present invention.

* Description of the symbols for the main parts of the drawings *

M1 ~ M2: PMOS transistor

M3 ~ M4: NMOS Transistor

The present invention is the most basic circuit element of the logic circuit configuration, and relates to the exclusive OR (XOR) circuit widely used in the digital circuit configuration, in particular, it is applied to configure less elements than the conventional circuit configuration The present invention relates to an XOR circuit that reduces the area of a chip or the like and reduces power consumption.

The prior art related to the present invention will be described with reference to FIG.

FIG. 1 is a block diagram of a conventional XOR circuit. As shown in the drawing, the structure of a conventional exclusive OR circuit includes a NAND gate that receives two input signals A and B, which are subject to an exclusive OR operation, and performs an AND logic operation on an output. G1), an OR gate G2 that receives the two input signals A and B, and performs an OR operation, and outputs the NAND gate G1 and an OR gate G2. And a NAND gate G3 for outputting and a NOT gate G4 for receiving the output of the NAND gate G3 and inverting the same.

In the conventional XOR circuit configured as described above, when the NOT gate G4 having one input and one output is configured in CMOS, each transistor is composed of one PMOS and NMOS, and a total of two transistors are required. In the same manner, the NAND gate G1 or G3 having the two inputs and one output is a total of four transistors, and the OR gate G2 having the two inputs and one output is a total of six transistors. It consists of a transistor.

Therefore, since a total of 16 transistors (eight PMOS and eight NMOS) are required to construct a conventional exclusive OR circuit, there is a limit to reducing the chip area when implementing a chip having a digital logic circuit. There was a big problem.

Accordingly, an object of the present invention is to provide an XOR circuit which reduces the area and power required for application by reducing the number of elements as components.

In order to achieve the above object, the present invention provides an inverting means for inverting and outputting a first input signal among first and second input signals input to a calculation target, and a second input receiving an output signal of the inverting means. A first switching device for switching on and off in response to an input signal and a second switching device for switching on and off in response to an output signal of the inverting means receiving the second input signal and being input to a control terminal; And a third switching element configured to receive the first input signal and switch on / off according to a second input signal input to a control terminal, and to output the second input signal to the control terminal. And a fourth switching element configured to switch on / off and output according to the signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying FIG. 2.

2 is a configuration diagram of an XOR circuit according to an embodiment of the present invention, and shows a configuration implemented using a CMOS transistor as a switching element, in which A and B are signals input as a calculation target, and M1 to M4 are MOSs. The transistor G5 represents a NOT gate, respectively.

As shown in the drawing, in the embodiment of the present invention, M1 and M2 are configured as PMOS transistors and M3 and M4 are configured as NMOS transistors. same.

First, if A = 0, B = 0,

Since the first PMOS transistor M1 receives A through the source terminal, which is an input terminal, and B through the gate terminal, which is a control terminal, the first PMOS transistor M1 is turned on to output A having a logic '0' through the drain terminal, which is an output terminal. Since the second PMOS transistor M2 receives B through the source terminal serving as an input terminal and A through the gate terminal serving as the control terminal, the second PMOS transistor M2 is turned on to output B having a logic '0' to the drain terminal serving as the output terminal. . The NMOS transistor M3 receives A as a drain terminal as an input terminal and B through a NOT gate G5 as a gate terminal as a control terminal. Is turned on and outputs 'A' which is logic '0' through the source terminal which is the output terminal, and the second NMOS transistor M4 is the drain terminal which is the input terminal B through the NOT gate G5, that is, The output terminal is turned off because the input signal is turned off and the output signal is turned off. Therefore, when the A and B signal values to be calculated are both '0', the exclusive OR signal '0' to which the output terminals of the four transistors are commonly connected is output.

Next, if A = 0, B = 1,

Since the first PMOS transistor M1 receives A through the source terminal, which is an input terminal, and receives B through the gate terminal, the first PMOS transistor M1 is turned off and opens with the output terminal. The second PMOS transistor M2 inputs B through the source terminal, which is an input terminal. Since A is input to the gate terminal, it is turned on to output B, which is a logic '1', to the drain terminal which is the output terminal. The first NMOS transistor M3 receives A through the drain terminal, which is an input terminal, and B through the NOT gate G5, that is, the gate terminal, that is, Is turned off and is open to the output terminal. The second NMOS transistor M4 is the drain terminal which is the input terminal. Is inputted, and A is inputted to the gate terminal, so that the output terminal is opened. Therefore, when the A and B signal values to be calculated are '0' and '1', respectively, the logic signal '1' is output to the exclusive logical sum output terminal in which the output terminals of the four transistors are commonly connected.

Also, if A = 1, B = 0,

Since the first PMOS transistor M1 receives A through the source terminal, which is an input terminal, and B through the gate terminal, the first PMOS transistor M1 is turned on to output A, which is a logic '1', to the drain terminal, which is an output terminal, and the second PMOS transistor M2. ) Is input to the source terminal, which is an input terminal, and A is input to the gate terminal, which is a control terminal. The first NMOS transistor M3 receives A through the drain terminal, which is an input terminal, and B through the NOT gate G5, that is, the gate terminal, that is, Is turned on and outputs 'A', which is logic '1', to the source terminal, which is an output terminal, and the second NMOS transistor M4 is the drain terminal, which is an input terminal, that is, B through the NOT gate G5. Is inputted, and A is inputted to the gate terminal, which is the control terminal, and outputs A, which is a logic '1', to the source terminal, which is the output terminal. Therefore, when the A and B signal values to be calculated are '1' and '0', respectively, the logic signal '1' is output to the exclusive logical sum output terminal in which the output terminals of the four transistors are commonly connected.

Finally, if A = 1, B = 1,

Since the first PMOS transistor M1 receives A through the source terminal, which is an input terminal, and receives the B through the gate terminal, the first PMOS transistor M1 is turned off and opens with the output terminal. The second PMOS transistor M2 receives B through the source terminal, which is an input terminal. And A is inputted to the gate terminal, which is the control terminal, and is thus turned off and opened with the output terminal. The NMOS transistor M3 receives A as a drain terminal as an input terminal and B through a NOT gate G5 as a gate terminal as a control terminal. Is turned off and is turned off from the output terminal. The second NMOS transistor M4 is the drain terminal which is the input terminal. Is inputted, and A is inputted to the gate terminal, which is the control terminal, so logic '0' is output to the source terminal, which is the output terminal. Outputs Therefore, when the A and B signal values to be calculated are '1' and '1', respectively, the logic signal '0' is output to the exclusive logical sum output terminal in which the output terminals of the four transistors are commonly connected.

When the operation state according to the input signal of the present invention configured and operated as described above and the output signal value accordingly are clearly shown, they are as shown in Table 1 below.

TABLE 1

As described above, it can be seen that the present invention performs the operation of the XOR circuit. In the above-described embodiment, the MOS transistor has been described as an example, but the PMOS transistor applies a low signal to the bias stage. Is replaced by a switching element (such as a P-type transistor) that is turned on, and an NMOS transistor is replaceable as a switching element (such as an N-type transistor) that is turned on when a high signal is applied to the bias stage.

Therefore, the present invention constructed and operated as described above has the effect of miniaturizing the scale of the circuit device to which the present invention is applied because the XOR circuit can be configured with fewer components than the conventional configuration. Specifically, 16 MOS transistors are required when the XOR circuit is configured and used as the MOS transistor as shown in FIG. 1, but only 6 MOS transistors are required when the circuit is constructed and implemented according to the present invention. In manufacturing, there is an effect that can significantly reduce the area of the chip.

Claims (4)

Inverting means for inverting and outputting the first input signal among the first and second input signals input to the calculation target; A first switching element configured to receive an output signal of the inverting means and switch on / off according to a second input signal input to a control terminal; A second switching element which receives the second input signal and switches on / off the output according to an output signal of the inverting means which is input to a control terminal; A third switching element configured to receive the first input signal and switch on / off the output according to a second input signal input to a control terminal; A fourth switching element configured to receive the second input signal and switch on / off the output according to the first input signal input to the control terminal; An exclusive OR circuit, comprising: a. The method of claim 1, And the first and second switching elements comprise a switching element that is turned on when a high logic signal is applied to a control stage. The method of claim 2, And the third and fourth switching devices each include a switching device that is turned on when a low logic signal is applied to a control terminal. The method of claim 3, wherein And the first and second switching elements are each composed of NMOS, and the third and fourth switching elements are each composed of PMOS.