KR0181159B1 - Pseudo noise synchronizing apparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a pseudo noise synchronization tracking device in a spread spectrum communication system.

2. The technical problem to be solved by the invention

It is implemented by digital circuit of pseudo noise code clock generator.

3. Summary of Solution to Invention

The early correlation value, the rate correlation value and the punctual correlation value are inputted to search for the state of the phase of the transmission / reception synchronization, the output of the phase search part is received, and at the time of early, a chip receives fast data from the phase search part. Counting is performed from the phase search unit when counting, and counting is performed from the phase search unit. After receiving the counter value, a pseudo noise generating clock is generated when a certain number is reached to generate a pseudo noise code.

4. Important uses of the invention

It can be used in pseudo-noise synchronization tracking device.

Description

Pseudo-noise synchronization tracking device in spread spectrum communication system

1 is a block diagram of a pseudo noise synchronization tracking device.

2 shows a conventional pseudo-noise code clock generator.

3 shows a pseudo noise synchronization tracking device in a spread spectrum communication system according to a preferred embodiment of the present invention.

4 shows the characteristics of the difference in the correlation between the early and the rate.

5 shows the characteristics of the difference between the correlation between early and late and punctual.

The present invention relates to a spread spectrum communication system, and more particularly, to a pseudo noise synchronization tracking device in a spread spectrum communication system.

In the spread spectrum communication system, an operation of precisely matching a chip phase by using a feedback circuit of a PN synchronization between a transmitter and a receiver having a PN synchronization within one chip after initial synchronization is performed is performed by synchronization of a PN code. Typically, the synchronization tracking of the PN code is performed using a phase lock technique. In this case, the important difference between the phase lock technology and the general PLL is that a phase discriminator is separately provided in the synchronous tracking of the PN code, unlike the general PLL. However, the basic operation of the phase determination circuit is the same as that of a phase locked loop (PLL). Accordingly, most of the synchronization tracking loops are also based on the PLL.

Meanwhile, the phase discrimination circuit of the PLL such as carrier synchronization is implemented by a simple multiplier. However, the phase discrimination circuit of the PN code synchronization tracking loop is composed of a plurality of multipliers, filters, integrators, and the like.

In addition, there are various methods for the synchronization tracking. When classified according to carrier synchronization, there are a synchronous method and an asynchronous method. In this case, unlike the asynchronous method, the synchronous method uses phase information of the received carrier.

On the other hand, the synchronous tracking loop can be classified structurally in terms of full time early-rate, tau dither early-late, and double dither early-late. Method). In this case, the full-time early-rate synchronous output receiver generates an early signal that is 1/2 chip faster than a punctual signal and a late signal that is 1/2 chip slow. In this case, correlation values Re (t) and Rl (t) between the early signal, the rate signal, and the received signal are obtained. The correlation values Re (t) and Rl (t) of the early signal and the rate signal obtained through the above process are used to calculate the difference D (t) of the correlation values. In this case, the difference D (t) of the correlation value is expressed by Equation 1 below.

In this case, the difference D (t) is used as an input control signal of the PN clock generator that drives the PN code generator. Accordingly, since the convergence is performed at the point where the phase of the transmission / reception PN code is t = 0, the synchronization tracking process can be performed. 4 is a diagram illustrating the phase difference D (t) graphically as shown in Equation (1). As shown in FIG. 4, the phase difference D (t) is a difference between a straight line indicating Re (t) and a straight line indicating Rl (t) in the drawing, descending from -3Tc / 2 and rising from -Tc / 2. It appears as an S-shaped curve that descends again from TC / 2.

On the other hand, Fig. 1 shows the conventional phase discrimination circuit. In the phase determination circuit of FIG. 1, the reception data received from the antenna 10 is input to the RF front end 12. FIG. The received data output from the RF front end 12 is low-pass filtered by a low pass filter (LPF) 14. The low filtered reception data is input to the first to third delay units 16 to 20. At this time, the low-pass filtered data is input to the first delay unit 16 and output half a chip ahead, which is referred to as early reception data. The low-pass filtered data is inputted to the second delay unit 18 and outputted without delay. This is called a functual received data. The low-pass filtered data is input to the third delay unit 20 and output after half chip, which is referred to as rate received data.

The early, functual and rate received data are input to the first to third multipliers 22 to 26. At this time, the first multiplier 22 receives the PN code generated by the PN code generator 48 and multiplies the early received data. At this time, the output of the first multiplier 22 is called an early information signal.

The second multiplier 24 receives and multiplies the PN code generated by the PN code generator 48 with the punctual reception data. At this time, the output of the second multiplier 24 is referred to as a punctual information signal. At this time, the third multiplier 26 receives and multiplies the PN code generated by the PN code generator 48 with the rate reception data. At this time, the output of the third multiplier is called a rate information signal.

The early information signal, functual information signal, and rate information signal are respectively input to the first to third integrators 28 to 32. At this time, the outputs of the first to third integrators 28 to 32 are respectively input to the first to third multipliers 34 to 38. At this time, the outputs of the first to third multipliers 34 to 38 are input to the first to third terminators 40 to 44. At this time, the first to third integrators 28 to 32, the first to third multipliers 34 to 38, and the first to third quadrants 40 to 44 correct the input signal. Accordingly, the early information signal, the func- tional information signal, and the rate information signal include the first to third integrators 28 to 32, the first to third multipliers 34 to 38, and the first to third quaternary roots 40. ~ 44) is corrected. In this case, the corrected early information signal is called Re (t), the corrected fungal information signal is called Rp (t), and the corrected rate information signal is called Rl (t).

The Re (t) and Rl (t) are input to the PN code clock generator 46. In this case, the conventional PN code clock generator 46 is shown in detail in FIG. 2. In FIG. 2, Re (t) and R1 (t) are input to the adder 50. At this time, Rl (t) is inverted. Accordingly, the adder 50 subtracts Re (t) and Rl (t). At this time, the subtracted information signal is input to the oscillator 54 through the loop filter 52 to control the oscillator 54. At this time, the output of the oscillator 54 is SCLK.

In this case, the adder 50, the loop filter 52, and the oscillator 54 are PLLs. In this case, the PLL is an analog PLL, and the PLL configuration is bulky and analogous, so the reproducibility is poor. And it is very difficult to determine the coefficient value of the loop filter 52.

On the other hand, the SCLK is a signal of N times the PN clock. The output of the oscillator 54 is divided into N SCLK input to the divider 56. The divided signal is applied to the clock of the counter 58. The counter 58 counts the clock and outputs a t = T signal if the count value is T.

Meanwhile, the divided signal is a PN generation clock. At this time, the PN generation clock is input to the PN code generator 48. The PN code generator 48 generates a PN code in response to the PN generation clock. The generated PN code is multiplied by the first to third multipliers 22 to 26 to perform despreading.

In the conventional general method as described above, early and rate signals having a half chip difference are used for synchronization tracking. As can be seen from FIG. 4, in order to see the correlation characteristics of the interval [-Tc / 2, Tc / 2] when only the early-rate correlation value is used for synchronization tracking, the phase shift of the PN code is performed during the search. It must move 1/2 chip. As a result, synchronization tracking takes a lot of time. As shown in FIG. 2, the conventional PN code clock generator includes a PLL including an adder 50, a loop filter 52, and an oscillator 54. As shown in FIG. At this time, each of the components is bulky, and because of the analog, the reproducibility is poor, and it is very difficult to determine the coefficient value of the loop filter 52. This made it difficult to implement.

Accordingly, an object of the present invention is to provide a PN synchronization tracking device in a spread spectrum communication system having a pseudo-noise code clock generation device composed of an end circuit.

In order to achieve the above object, the present invention receives an early correlation value, a rate correlation value and a punctual correlation value to search for a state of phase of transmission and reception synchronization, and receives an output of the phase search unit from the phase search unit. When one chip receives fast data and counts from the data, at the time of puncturing, the chip receives the punctual data from the phase searcher and counts, and at the rate, one chip is slow from the phase searcher. After receiving data and counting from the data, when the counter value is received, a PN generation clock is generated to generate a PN code.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

The present invention provides a PN code clock generator capable of performing synchronous tracking using not only the correlation value of an early-rate loop but also the correlation value of a func- tional loop.

PN code clock growth growth value according to the present invention from the first to the third square root (40 ~ 44) of FIG. To be provided. At this time, the difference D (t) of the correlation value is calculated from the three values. In this case, the difference D (t) is a sum of the correlation value Re (t) of the early loop and the correlation value Rl (t) of the rate loop multiplied by the scaling factor Fs and the punctual loop. The correlation value Rp (t) is compared to obtain the difference Re (t) of the correlation value. The equation regarding the difference Re (t) of the correlation value is as shown in (Equation 2).

In the above formula (2) Is Indicates. At this time, the synchronization tracking is driven like a digital PLL to control the clock of the PN code generator 48 such that the difference D (t) of the correlation value given by Equation 2 is minimized.

At this time, FIG. 5 is in accordance with Equation 2 It shows the S-curve characteristics using. Accordingly, D (t) generated according to Equation (2) is lowered from -3Tc / 2 to maintain the point of -Tc, and then starts to rise from -Tc / 2 and reaches to -Tc / 2. Then, it is generated as an S-curve descending at the Tc point.

Meanwhile, Equation 2 can directly generate the PN code clock of the PN clock generator. However, the above equation can be converted into a simple equation. The converted formula is the following (formulas 2-1 to 3).

In this case, Equation 2-1 indicates that the transmission and reception PN codes are synchronized in the functional loop. In the case of Equation 2-1, the PN code clock generator 46 normally outputs the PN code clock. At this time, the PN code clock generator 46 inputs the normal PN code clock to the PN code generator 48.

On the other hand, Equation (2-2) indicates that the synchronization of the transmission and reception PN codes in the early loop is identical. In the case of Equation 2-2, the phase of the received PN code is fast. At this time, the PN code clock generator 46 adjusts the PN code clock to quickly adjust the phase of the PN code which is the reference of the receiver.

On the other hand, Equation (2-3) indicates that the transmission and reception PN codes are synchronized in the rate loop. In the case of Equation 2-2, the phase of the received PN code is slow. At this time, the PN code clock generator 46 adjusts the PN code clock to slowly adjust the phase of the PN code which is the reference of the receiver.

3 illustrates the PN code clock generator 46 in detail according to an exemplary embodiment of the present invention.

In order to implement Equation 2-1, Rl (t) and Rl (t) are input to the adder 62. The output of the adder 62 and Fs are again input to the multiplier 64. The output of multiplier 64 and Rp (t) are input to adder 66. The output of the adder 66 is input to the A input terminal of the comparator 68. At this time, 0 is input to the B input terminal of the comparator 68. At this time, the comparator 68 generates a high state output to the AB output terminal when the value input to the A input terminal is smaller than the value input to the B input terminal. At this time, the value output from the AB output terminal is 0 to be.

The comparator 68 generates a high state output at the AB output terminal when the value input to the A input terminal is greater than the value input to the B input terminal. At this time, the value output from the AB output terminal is to be.

When the value input to the A input terminal is equal to the value input to the B input terminal, the comparator 68 generates a high state output at the A = B output terminal. At this time, the value output from the A = B output terminal is to be.

The signals output from the AB output terminal and the A = B output terminal of the comparator 68 are input to the oragate 70. The output of the oragate 70 to be. In this way, the output of the oragate 70 is shown in Equation 2-1. The output of the oragate 70 and t = T are input to the AND gate 80. At this time, the AND gate 80 is a case where t = T occurs high Outputs At this time, the output of the AND gate 80 is input to the P selection input terminal of the selector 80.

Rl (t) and Rl (t) are input to the A input terminal and the B input terminal of the comparator 72, respectively. In this case, the comparator 72 generates a high state output at the AB output terminal when the value input to the A input terminal is smaller than the value input to the B input terminal. In this case, the value output from the AB output terminal is Re (t) Rl (t).

The comparator 72 generates a high state output at the AB output terminal when the value input to the A input terminal is greater than the value input to the B input terminal. In this case, the value output from the AB output terminal is Re (t) Rl (t).

When the value input to the A input terminal is equal to the value input to the B input terminal, the comparator 72 generates a high state output at the A = B output terminal. In this case, the value output from the A = B output terminal is Re (t) = Rl (t).

Meanwhile, the outputs of the AB output terminal and the A = B output terminal of the comparator 72 are input to the oragate 74. The output of the oragate 74 and the output of the AB output terminal of the comparator 68 are input to the AND gate 76. The output of the AND gate 76 And to be. In this way, the output of the AND gate 76 is represented by Equation 2-2.

The output of the AND gate 76 and t = T are input to the AND gate 82. The output of the AND gate 82 is input to the E selection input terminal of the selector 88.

On the other hand, the output of the AB output terminal of the comparator 68 and the output of the AB output terminal of the comparator 72 are input to the AND gate 78. At this time, the output of the AND gate 78 And to be. In this way, the output of the AND gate 84 is as shown in Equation 2-3. The output of the AND gate 78 and t = T are input to the AND gate 84. The output of the AND gate 84 is input to the L selection input terminal of the selector 88.

On the other hand, t = T is inverted by the inverter 86 and then input to the N input terminal of the selector 88. Meanwhile, '0' is input to the A input terminal of the selector 88. '1' is input to the B input terminal of the selector 88. In addition, '2' is input to the C input terminal of the selector 88.

The selector 88 as described above outputs '1' input to B when the signal input to the P selection input terminal is high. '1' is input as an input value when the counter 90 is loaded. Accordingly, the counter 90 counts from the '1' when loading.

The selector 88 outputs '2' input to C when the signal input to the E selection input terminal is high. '2' is input as an input value when the counter 90 is loaded. Accordingly, the counter 90 starts counting from the '2' when loaded.

The selector 88 outputs '0' input to A when the signal input to the L selection input terminal is high. '0' is input as an input value when the counter 90 is loaded. Accordingly, the counter 90 counts from '0' at load.

The counter 90 receives the number input from the selector 88 and counts from the input number. At this time, the count clock is SCLK. The count value is input to the comparators 92 and 94. At this time, the comparator 92 outputs a high state signal when the count value is N. The comparator 94 outputs a high state signal when the count value is N / 2. The outputs of the two comparators 92 and 94 are input to the oragate 96. At this time, the output of the oragate 96 is input to the enable terminal of the D-flip flop (98). At this time, the output of the Q output terminal of the D-flop flop 98 is input to the inverter 100 is inverted and input again to the D input terminal of the D-flop flop 98. Accordingly, the D-flip-flop 98 inverts and outputs the output when the enabled. In this case, the D-flip-flop 98 is enabled whenever SCLK is counted N times. Accordingly, the output of the D-flip-flop 98 divides N SCLK. At this time, the N divided SCLK is a PN clock.

On the other hand, the counter 90 has a different value of starting counting according to the output of the selector 88. In other words, counting starts from 2 at early and 0 at late and 1 at punctual. As a result, the PN clock is output one chip early at an early stage, as it is at the time of punctuation, and one chip slowly at the rate.

As described above, the present invention can search by one chip using both correlation values of early and punctual rate loops. Accordingly, the synchronization tracking time can be reduced by half compared to the conventional method. In addition, even if the input signal is captured early or in the rate loop, the detection can detect the loss of the synchronization signal.

In addition, since it is realized as a digital circuit, it is excellent in miniaturization, integration, and reproducibility, and has low cost.

Claims (4)

A pseudo-noise synchronization tracking device in a spread spectrum communication system, comprising: an antenna for receiving data, a high frequency front end terminal for receiving data received from the antenna, a low frequency filter for receiving data from the high frequency front end terminal, A delay unit for receiving the output of the filter and delaying each of the delayed outputs at an early, rate and punctual output; a multiplier for receiving the delayed output and multiplying the pseudo noise code; A correction unit for correcting the punctual signal and outputting the early correlation rate, the rate correlation value and the punctual correlation value, and receiving the early correlation value, the rate correlation value and the puncture correlation value, and searching the state of the phase of the transmission and reception synchronization. When the early or slow data is input to the phase search unit and the output of the phase search unit, The data is counted from the phase search unit by receiving one-chip fast data from the phase search unit, and counting is performed by receiving the data from the phase search unit from the phase search unit. A counter that receives a slow data from the chip and performs a count from the data, a divider for generating a pseudo noise generating clock when the counter value of the counter is reached, and the costume noise generating clock And a clothes noise code generator for generating a noise code and inputting the noise code into the multiplier. The first comparator of claim 1, wherein the phase search unit adds an early correlation value and a rate correlation value, the addition value multiplies a scale factor, and compares a value obtained by adding the punctual correlation value to the multiplication value with zero. A second comparison unit comparing the early correlation value and the rate correlation value, an extraction unit for extracting a phase of a transmission / reception synchronization from the comparison values of the two comparators, and an output of the extraction unit as a selection signal, If the selection signal indicates the earliest phase of the transmit / receive synchronization, one chip early data is output, one rate slow data is output if the rate hour is displayed, and the data at the time of puncture is output. A pseudo noise synchronization tracking device in a spread spectrum communication system, characterized in that it comprises a selector. 3. The extractor according to claim 2, wherein the extracting unit ORs the output when the signal input among the outputs of the first comparator is greater than 0 and the output when it is equal to 0, and logically multiplies with the t = T signal to generate a puncture time. A first logic gate section for extracting a signal to be displayed, and an output of the second comparator and an output when the early signal is greater than the rate signal, and are logically summed, and then input again during the output of the first comparator Is a second logical gate portion that is logically multiplied by an output when is less than 0, and is then logically multiplied by a t = T signal to extract a signal representing early time, and when the input signal of the output of the first comparator is smaller than zero. The third logical gate is logically multiplied by the output when the early signal is smaller than the rate signal among the outputs of the output and the second comparator. Spread spectrum PN Code Tracking apparatus in a communication system characterized in that the. The apparatus of claim 1, wherein the pseudo-noise code clock generation device further comprises a t = T generation unit for counting the pseudo-noise generation clock and generating t = T when the count value is equal to the T value. Pseudo-noise synchronization tracking device in a spread spectrum communication system.