KR0173935B1 - Low Power Consumption Semiconductor Memory Device - Google Patents

Abstract

The present invention is a semiconductor memory device that performs a low power consumption bit line sensing operation, wherein each isolation element separates a bit line when a word line belonging to one of two sub-arrays is selected. The area of the subarray, which is controlled by the isolation control signal generator circuit and is increased by adding isolation elements in the memory cell array, is significantly smaller than that of the bitline sense amplifier area, where the wordline is selected and the data in the cell When the bit line sensing operation is carried out, the parasitic capacitance of one sub array of the separated bit lines may be excluded. As a result, the current consumption when the bit lines in the memory cell array are shifted to Vss and Vcc is reduced by 1/4.

Description

Low Power Consumption Semiconductor Memory Device

1 is a schematic diagram showing a conventional memory cell array structure.

2 illustrates a memory cell array structure in accordance with the present invention.

3 is a circuit diagram showing an embodiment of a separation control signal generation circuit for controlling the operation of the separation element according to the present invention.

4 is a timing diagram of FIG.

5 is a circuit diagram showing another embodiment of the separation control signal generation circuit according to the present invention.

6 is a timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

1, 2: output terminal 3: precharge circuit

4, 5: output drive circuit 6: separate signal drive control circuit

10: memory cell array 10a, 10b: sub array

BL, / BL: Bit line WL: Word line

SA: Bit Line Sense Amplifier

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device performing a low power consumption bit line sensing operation.

BACKGROUND OF THE INVENTION The manufacturing technology of a semiconductor memory device has been developed in a direction for storing a lot of information in a small area. Higher integration through development of pattern miniaturization technology in process technology, shorter input / output time through improved transistor performance, new circuit implementation in design field, development of new layout technology, High integration and shortening of access time have been achieved. As the device becomes highly integrated, the area of the peripheral circuit area of the initial semiconductor memory chip is larger in the memory cell array region and the peripheral circuit region. Increasingly, the memory cell array area occupies a larger area. However, the increase in package size does not increase proportionally. As a result, all efforts are being made to reduce chip size through the development of new circuit technologies, placement methods and new process technologies. As semiconductor memory devices are highly integrated, it is effective to reduce the area of a memory cell array to reduce chip size.

1 schematically shows a conventional conventional memory cell array structure. In Fig. 1, reference numeral 10 denotes a memory cell array, BL1 to BLn, / BL1 to / BLn denote bit lines, WL1 to WLm denote word lines, respectively, and SA1 to SAn denote bit line sense amplifiers. line sense amplifiers.

In the semiconductor memory device, at least one of the memory cell array regions 10 and the bit line sense amplifier regions SA1 to SAn are formed to form a memory cell array fj4. When the size of one memory cell array is m (the number of word lines arranged in the row direction) x n (the number of bit lines arranged in the column direction), the size of m has a great influence on the characteristics of the semiconductor memory device. do. The memory cell array 10 shown in FIG. 1 includes m word-lines and n bit-line pairs. As is well known, this configuration is a typical example of a folded bit-line architecture. In this structure, m / 2 cells are connected to one bit line.

Meanwhile, in the cell array of a semiconductor memory device, a structure of 128 cells per bit-line or a structure of 256 cells per bit line is mainly employed. This represents the number of cells connected to one bit line in the memory cell array. When the memory cell array has a '128 cell structure per bit line', an increase in the number of bit line sense amplifiers results in an increase in chip size. On the other hand, when the memory cell array has a '256 cell structure per bit line', a specific word line is selected and information stored in the corresponding cell is loaded on the corresponding bit line, and then the sensing operation is performed through the corresponding bit line detector. When the sensing operation is performed, the parasitic capaitance of the bit line is increased, thereby increasing the array current. Therefore, how to reduce the current consumption while reducing the chip size is a big challenge.

Here, the problem of the prior art will be described in more detail, for example, with a 16 Mb DRAM having a memory cell array block consisting of 4096 word lines, 4096 bit line pairs, and bit line sense amplifiers. The memory cell array block of this structure is usually divided into a plurality of memory cell array regions to ensure the characteristics of the bit line sense amplifier. When the '128 cell structure per bit line' is adopted, there are 16 memory cell array regions and 17 bit line sense amplifier regions in the memory cell array block. On the other hand, when the '256 cell structure per bit line' is adopted, there are eight memory cell array regions and nine bit line sense amplifier regions in the memory cell array block. As already mentioned earlier, the latter structure is advantageous in terms of chip size over the former structure, but has the drawback that much larger current consumption occurs in the bit line sensing operation after the word line is enabled. Briefly, the reason is as follows. If a memory cell array has a 'bit-lined 128-cell structure' or a '256-cell structure per bit line', in both cases, the number of bit line amplifiers enabled when a particular word line is selected is 4096. The same (not considered here for redundancy cells). However, in both cases, the parasitic capacitances for each bit line are different from each other. That is, the parasitic capacitance per bit line of the '256 cell structure per bit line' is twice that of the '128 cell structure per bit line'. Therefore, in the bit line sensing operation, the amount of current consumed to transition the bit lines to Vss and Vcc becomes much larger in the '256 cell structure per bit line'. Such current consumption becomes a big problem as memory devices are highly integrated.

Therefore, an object of the present invention is to enable high integration of a semiconductor memory device while suppressing its current consumption.

In accordance with an aspect of the present invention, a semiconductor memory device includes: first and second devices connecting bit line pairs respectively controlled by first and second switching signals and respectively belonging to neighboring memory cell arrays. Split gate pairs in a group; A plurality of sense amplifiers each connected to only one of the bit line pairs each connected by the separation gate pairs; And control means for driving any one of the switching signals when one of the word lines belonging to the neighboring memory cell arrays is selected.

In an embodiment of this aspect, the control means comprises: precharge means for precharging the first and second switching signals, respectively; First output driving means for driving the first switching signal to a boosted voltage level or a ground voltage level; Second output driving means for driving the second switching signal to the boosted voltage level or the ground voltage level; A predetermined first row address signal representing a selection of one of the memory cell arrays, a predetermined second row address signal representing a selection of the other one of the memory cell arrays and a predetermined representation representing both the selection of the memory cell arrays And another control means for controlling the operations of the precharge means, the first output drive means and the second output drive means, respectively, in response to the cell array selection signal of.

In another aspect, an apparatus according to the present invention includes a memory cell array region having m word lines and n bit lines spread in a row direction and a column direction, respectively, and a bit line disposed adjacent to the memory cell array region. In a semiconductor memory device having at least one sense amplifier region, the memory cell array is disposed at a predetermined position of each of the bit lines spread in the memory cell array region so that each bit line is divided into two sub bit lines. N separations to allow the region to be divided into two sub-array regions and for the sub-bit lines of each bit line to be electrically connected to each other or electrically isolated from each other in response to the predetermined control signals being provided respectively. Elements; Control means for controlling these separation elements; The control means may include a predetermined n / n of the n bit lines in response to predetermined input signals when one of the word lines in any one of the sub-array regions is selected to perform a bit line sensing operation. Control the isolation elements such that the sub bit lines of each of the two bit lines are electrically connected to each other and the sub bit lines of each of the remaining n / 2 bit lines of the n bit lines are electrically isolated from each other. It is characteristic.

As described above, the area of the subarray increased due to the addition of isolation elements in the memory cell array is significantly smaller than that of the bit line sense amplifier region, and the word line is selected and the data in the cell is loaded on the bit line to perform the bit line detection operation. When this is done, it is possible to exclude the parasitic capacitance of one sub-array of the separated bit lines. As a result, the current consumption when the bit lines in the memory cell array are shifted to Vss and Vcc is reduced by 1/4.

The present invention will now be described in detail with reference to the accompanying drawings. FIG. 2 is a diagram showing the structure of a memory cell array according to the present invention, in which components having the same functions as those of the components of the conventional memory cell array described above are identical to those of FIG. Reference numerals and signs are indicated. In FIG. 2, reference numerals 10a and 10b are denoted by MOS transistors that act as isolation devices for separating each of the bit lines of the m × n memory cell array 10 into sub bit lines. Each of the two m / 2 × n subarrays is shown. In the memory cell array 10, the sub bit line pairs of the left sub array 10a are denoted by BLx_1 and BLx_1, respectively, and the sub bit line pairs of the right sub array 10a are denoted by BLx_r and BLx_r, respectively. have. Separate control at each gate of the isolation elements for bit line pairs (ie, odd-numbered bit line pairs) connected to the sense amplifiers SA1, SA3,..., SAn-1 disposed on the right side of the memory cell array 10. A separate control signal ISO2 is provided at each gate of the isolation elements for bit line pairs (i.e., even-numbered bit line pairs) that are provided with a signal ISO1 and are connected to sense amplifiers SA2, SA4, ..., SAn disposed on the left side. Is provided. As such, the type of separation control signal provided to the gate of the isolation element of the corresponding bit line pair is determined depending on whether the sense amplifier connected to the corresponding bit line pair is located at the left or right side of the memory cell array 10.

3 shows a preferred embodiment of a circuit for generating isolation control signals ISO1, ISO2 for controlling the operation of isolation elements of a memory cell array in accordance with the present invention. In FIG. 3, / RAi represents a row address signal representing the selection of the left sub-array 10a, RAi represents a row address signal representing the selection of the right sub-array 10b, and PBLSi represents a memory cell. It is a cell array selection signal indicating the selection of the array 10. Referring to FIG. 3, the separation control signal generation circuit of the present embodiment includes first and second output terminals 1 and 2 for outputting two separation control signals ISO1 and ISO2, and three PMOS transistors. Precharge circuit 3 having charges MP1, MP2, and MP3 and precharging the output terminals 1 and 2 to an internal power supply voltage IVcc level, and PMOS and NMOS transistors MP4 and MN1, respectively. And a first output driver circuit 4 for driving the first output terminal 1 to a boosted voltage Vpp level or a ground voltage Vss level, and also PMOS and NMOS transistors MP5 and MN2. And a second output driver circuit 5 for driving the second output terminal 2 to a boosted voltage Vpp level or a ground voltage Vss level, and three NAND gates NAND1 to NAND3. And two inverters INT1 and INT2 and in response to the row address signals RAi and / RAi and the cell array selection signal PBLSi. It consists of a separate signal drive control circuit 6 which controls the operation of the first and output drive circuits 4 and 5, respectively.

4 is an operation timing diagram of a separate control signal generating circuit, in which (a) represents a / RAS signal, (b) represents / RAi and RAi signals, (c) represents a PBLSi signal, and (d) represents ISO1 and ISO2. The signals are shown respectively.

Next, the operation principle of the memory device according to the present embodiment will be described in detail with reference to FIGS. 2, 3, and 4.

First, if none of the two subarrays 10a, 10b is selected, i.e., both the / RAi signal and the RAi and PBLSi signals are low level (i.e., precharge level), referring to FIG. Since the output of each of the first and second NAND gates NAND1 and NAND2 in the control circuit 6 is at a high level (a stepped-up voltage level Vpp), the first and second inverters INT1 and INT2 and the first and second inverters NAND1 and NAND2 are respectively at high level. The output of each of the 3 NAND gates NAND3 is at a low level. As a result, the transistors MP4, MN1, MP5, and MN2 in the first and second output driving circuits 4 and 5 are all in a non-conductive state, and the transistors MP1 to MP3 in the precharge circuit 3 are turned off. All become conductive. As a result, the output terminals 1 and 2 are precharged with the internal power supply voltage IVcc.

In this way, with the output terminals 1 and 2 precharged to the internal power supply voltage IVcc, with reference to FIG. 2, for example, a service array located on the left side of the isolation elements (hereinafter referred to as 'left sub'). When a specific word line WL1 in the array 10a is selected, as shown in FIG. 4, the / RAS signal (see (a) in FIG. 4) transitions to a low level, The / RAi and PBLSi signals (see (b) and (c) of FIG. 4) transition from the precharge level to a high level, and the RAi signal (see (b) of FIG. 4) maintains the precharge level. As such, when the specific word line WL1 of the left sub-array 10a is selected, referring to FIG. 3, the output of the first NAND gate NAND1 in the separated signal driving control circuit 6 transitions to a low level. The output of the second NAND gate NAND2 remains at a high level. As a result, the output of the first inverter INT1 maintains a low level, and each of the outputs of the second inverter INT2 and the third NAND gate NAND3 transitions to a high level so that the PMOS in the first output driver circuit 4 is maintained. The transistor MP4 and the NMOS transistor MN2 in the second output driver circuit 5 are in a conductive state. Thus, the ISO1 signal transitions from the precharge level to the high level Vpp and the ISO2 signal transitions from the precharge level to the low level Vss. As a result, in FIG. 2, even-numbered sub bit line pairs BL2_r, BL4_r, / BL2_r, in the subarray (hereinafter, referred to as a 'right subarray') 10b located on the right side of the memory cell array 10. / BL4_r, ..., BLn_r, / BLn_r are electrically isolated from the corresponding sense amplifiers SA2, SA4, ..., SAn, respectively, and the remaining sub bit line pairs in the memory cell array 10 are respectively associated with the corresponding sense amplifiers. Electrically connected.

On the other hand, for example, referring to FIG. 2, when a specific word line WLm in the right sub-array 10b is selected, the output of the first NAND gate NAND1 is described with reference to FIG. 3. Is maintained at the high level, and the output of the second NAND gate NAND2 transitions to the low level. As a result, each output of the first inverter INT1 and the third NAND gate NAND3 transitions to a high level, and the output of the second inverter INT2 remains at a low level, so that the NMOS in the first output driving circuit 4 is maintained. The transistor MN1 and the PMOS transistor MP5 in the second output driver circuit 5 are in a conductive state. Thus, the ISO1 signal transitions from the precharge level to the low level Vss and the ISO2 signal transitions from the precharge level to the high level Vpp. As a result, in FIG. 2, odd-numbered sub bit line pairs BL1_1, / BL1_1, BL3_1, / BL3_r,..., BL (n-1) _1, in the left subarray 10a of the memory cell array 10. / BL (n-1) _1 is electrically isolated from the corresponding sense amplifiers SA1, SA3,..., SAn-1, respectively, and the remaining sub bit line pairs in the memory cell array 10 are connected to the corresponding sense amplifiers. Each is electrically connected.

5 shows another embodiment of a separate control signal generation circuit according to the present invention. Referring to FIG. 5, the circuit of this embodiment is one NAND gate (hereinafter referred to as a 'fourth NAND gate') that generates an ISO2 signal by taking a / RAi signal and a PBLSi signal as two inputs and performing a NAND operation. (NAND4) and another NAND gate (hereinafter referred to as a fifth NAND gate) (NAND5) that generates an ISO1 signal by receiving a RAi signal and a PBLSi signal and performing a NAND operation. In the circuit of this embodiment, the ISO1 and ISO2 signals maintain the Vpp level in the precharge period, and when the / RAi and RAi signals and the PBLSi signal are input, one of the two separate control signals (ISO1 and ISO2) sets the Vpp level. Keep one different and transition to Vss level.

6 is an operation timing diagram of the separation control signal generation circuit according to this embodiment, in which (a) represents the / RAS signal, (b) represents the / RAi and RAi signals, (c) represents the PBLSi signal, and (d Denotes ISO1 and ISO2 signals, respectively.

The operation principle of the circuit according to the present embodiment will be described with reference to FIGS. 2, 5, and 6 as follows. First, referring to FIG. 2, for example, when a specific word line WL1 in the left sub-array 10a is selected, as shown in FIG. 6, the / RAS signal ( a)) transitions to a low level, the / RAi and PBLSi signals (see (b) and (c) in FIG. 6) transition from a precharge level to a high level, and the RAi signal (b) in FIG. Maintains the precharge level. As such, when the specific word line WL1 of the left sub-array 10a is selected, referring to FIG. 5, the fourth NAND gate NAND4 outputs an ISO2 signal having a low level Vss, and the fifth NAND. The gate NAND5 outputs the high level Vpp ISO1 signal. Thus, in FIG. 2, even-numbered sub bit line pairs BL2_r, / BL2_r, BL4_r, / BL4_r, ..., BLn_r, / BLn_r in the right sub-array 10b of the memory cell array 10 are corresponding sense amplifiers. And SA2, SA4,..., SAn, respectively, and the remaining sub bit line pairs in the memory cell array 10 are electrically connected to respective sense amplifiers.

On the other hand, for example, referring to FIG. 2, when a specific word line WLm in the right sub-array 10b is selected, referring to FIG. 5, the fourth NAND gate NAND4 is high. The ISO2 signal at the level Vpp is output, and the fifth NAND gate NAND5 outputs the ISO1 signal at the low level Vss. As a result, in FIG. 2, odd-numbered sub bit line pairs BL1_1, / BL1_1, BL3_1, / BL3_r,..., BL (n-1) _1, in the left subarray 10a of the memory cell array 10. / BLn-1) _1) are electrically isolated from the corresponding sense amplifiers SA1, SA3,..., SAn-1, respectively, and the remaining sub bit line pairs in the memory cell array 10 are electrically connected to the corresponding sense amplifiers, respectively. Is connected.

Although the present invention has been described with reference to a case where the present invention is applied to a memory cell array having a folded bit line structure, the present invention can be applied to an array of other structures such as an open bit-line architecture. Those skilled in the art will appreciate that there may be various embodiments within the spirit and scope of the present invention and claims appended hereto.

Claims (6)

1. A semiconductor memory device comprising: first and second groups of isolation gate pairs that connect bit line pairs respectively controlled by first and second switching signals and belonging to neighboring memory cell arrays, respectively; A plurality of sense amplifiers each connected to only one of the bit line pairs each connected by the separation gate pairs; And control means for driving any one of the switching signals when one of the word lines belonging to the neighboring memory cell arrays is selected. The method of claim 1, wherein the control means; Precharge means for precharging the first and second switching signals, respectively; First output driving means for driving the first switching signal to a boosted voltage level or a ground voltage level; Second output driving means for driving the second switching signal to the boosted voltage level or the ground voltage level; A predetermined first row address signal representing a selection of one of the memory cell arrays, a predetermined second row address signal representing a selection of the other one of the memory cell arrays and a predetermined representation representing both the selection of the memory cell arrays And another control means for respectively controlling the operations of said precharge means, said first output drive means, and said second output drive means in response to a cell array selection signal of < RTI ID = 0.0 >. ≪ / RTI > 3. The apparatus of claim 2, wherein the other control means comprises: first NAND gate means for receiving the first row address signal and the cell array selection signal as two inputs to generate the first switching signal; And a second NAND gate means for receiving the second row address signal and the cell array selection signal as two inputs to generate the second switching control signal. A semiconductor memory device having at least one memory cell array region having m word lines and n bit lines spread in a row direction and a column direction, and at least one bit line sense amplifier region disposed adjacent to the memory cell array region. WHEREIN: A memory cell array region divided into two sub-array regions, wherein each bit line is disposed at a predetermined position of each of said bit lines spread within said memory cell array region. N isolation elements for causing the sub-bit lines of each bit line to be electrically connected to each other or to be electrically isolated from each other in response to being provided with predetermined control signals, respectively; Control means for controlling these separation elements; The control means may include a predetermined n / n of the n bit lines in response to predetermined input signals when one of the word lines in any one of the sub-array regions is selected to perform a bit line sensing operation. Control the isolation elements such that the sub bit lines of each of the two bit lines are electrically connected to each other and the sub bit lines of each of the remaining n / 2 bit lines of the n bit lines are electrically isolated from each other. Low power consumption semiconductor memory device, characterized in that. 5. The memory cell array of claim 4, wherein the control means comprises: a first isolation control signal for the isolation elements of each of the pairs of bit lines connected to a first bit line sense amplifier region disposed at one side of the memory cell array region; Precharge means for precharging a second isolation control signal for the isolation elements of each of the bit line pairs connected to a second bit line sense amplifier region disposed on the other side of the region; First output driving means for driving the first beak control signal to a boosted voltage level or a ground voltage level; Second output driving means for driving the second separation control signal to the boosted voltage level or the ground voltage level; A predetermined first row address signal representing a selection of a subarray on the left side of the memory cell array region and a predetermined second row address signal representing a selection of the sub arrays on the right side of the memory cell array region and the memory cell array region And a separate signal drive control means for controlling the operations of said precharge means, said first output drive means and said second output drive means in response to a predetermined cell array selection signal indicative of selection. Consumed semiconductor memory device. 6. The method according to claim 5, wherein said separate signal drive control means comprises: a predetermined first row address signal representing a selection of a subarray on one side of said memory cell array region as two inputs and a predetermined representation representing a selection of said memory cell array region; A first isolation for conducting / non-conducting isolation elements of each of the pairs of bit lines connected to a first bit line sense amplifier region disposed on one side of the memory cell array region by receiving a cell array selection signal and performing a NAND operation; First NAND gate means for generating a control signal; A second row address arranged on the other side of the memory cell array region by performing a NAND operation by receiving a predetermined second row address signal representing the selection of the other sub-array of the memory cell array region and the cell array selection signal as two inputs; And a second NAND gate means for generating a second switching control signal for conducting / non-conducting isolation elements of each of the pairs of bit lines connected to the 2-bit line sense amplifier region.