KR0170710B1 - Non-volatile semiconductor memory device - Google Patents

Abstract

The present invention provides a memory cell transistor connected in series with two or more in series while sharing a source and a drain with neighboring cells, a string select transistor connected in series with one end of the memory cell transistor, and a ground select transistor connected in series with the other end of the memory cell transistor. 1. A nonvolatile memory device having a first string having a second string and a second string connected to the first string through a bit line contact, wherein the first and second strings are formed in parallel with the bit line. A nonvolatile semiconductor memory device including at least one normalization dummy transistor connected in series with a cell transistor in the string. The dummy transistor has the same structure as the string select transistor. Since the transistor cell employed in the present invention is composed of only the control gate, the Vth of the dummy transistor does not change even when the voltage Vpgm is applied to the control gate. Therefore, a malfunction due to an overprogramming of the dummy transistor cell during data reading can be prevented. In addition, when the dummy cell is used, the maximum voltage for boosting the channel voltage by boosting the dummy cell when the program voltage is 20V is about 12V. When using the dummy transistor proposed in the present invention, only 12V is applied to the control gate. It is possible to boost the same voltage that the micelles can boost. In addition, if Vpgm is 15V and the Vpass voltage is 10V, the voltage to be applied to the dummy transistor has an advantage of applying a voltage lower than the Vpass voltage.

Description

Nonvolatile Semiconductor Memory Device

1 is an equivalent circuit diagram of a NAND type memory cell according to the prior art.

2 is an equivalent circuit diagram of another NANF type memory cell according to the prior art.

3 is a vertical sectional view of a semiconductor memory cell of the prior art and the present invention.

4 is an equivalent circuit diagram of a NAND type memory cell according to an embodiment of the present invention.

5 is an operating voltage characteristic diagram of a flash memory limited to malfunctions of cells B and C that are not selected.

* Explanation of symbols for main parts of the drawings

200: depletion layer 210: first dielectric film (tunnel oxide film)

220: second dielectric film 300, 400: source / drain, channel

BL1-BL3: Bit line WL1-WLn: Word line

GSL: Ground Select Transistor SSL: String Select Transistor

WLd: dummy wordline Cd: dummy transistor cell

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device capable of preventing program disturbance.

Recently, there is an increasing demand for semiconductor memory devices that can electrically write and erase data but do not require a refresh function, and in order to develop large-capacity memory devices capable of replacing and storing a large amount of data, high integration technology of memory cells has been developed. It's going on.

For this purpose, a NAND type flash memory has been proposed in which n cells are connected in series to form one string and two strings share one contact. Erase and program or write of the memory device is performed by controlling the threshold voltage of the cell while injecting or emitting electrons into the floating gate using Fowler Nordheim (FN) tunneling. .

In an EEPROM including such a flash memory, electrons are injected or emitted to a floating gate through a tunnel oxide layer during a program or erase operation. This causes a big problem in the reliability of the device.

Thus, when trying to rewrite data, the unselected cell is programmed for malfunction, the charge retention characteristics of how long the data can be retained, and the endurance of how much can be rewritten and erased. It is represented as a characteristic.

1 is an equivalent circuit diagram of a portion of a NAND type flash memory cell structure. In FIG. 1, a plurality of strings connected to three bit lines BL1 to BL3 are relatively shown. A general program operation of a NAND flash memory and an operation of programming a cell to be prevented are as follows.

Each string is common to the source side of a transistor (or cell) having a source side of a selection transistor (hereinafter referred to as an SSL transistor) MS1-MS3 for selecting individual strings connected to a bit line and a drain side having a control gate and a floating gate. Connected. The cells are arranged in series with a constant separation width, and have a ground transistor (GSL transistor) (MGS1-MGS3) for selectively connecting the source side of the end cell of the string to the ground line.

On the other hand, the data of 0 or 1 in the flash memory is distinguished by the threshold voltage Vth of the transistor in the control gate of each cell transistor, and 0V is applied to the selected word lines WL1-WLn and an unselected word. Apply voltage above Vcc to line, Vcc to SSL and GSL to make transistor conduction, detect current flowing when applying 0-Vcc voltage to bit line with source grounded The threshold voltage Vth in the on state is usually -3V or less, the off state Vth is + 1V or more, and the Vth of the programmed cell transistor is + 1V, which is the positive Vth state. to be.

A case of programming the cell A will be described with reference to FIG. To program cell A, first apply Vcc to the SSL of the select string and 0V to the unselected string. Next, 0V is applied to the selected bit line BL2 and Vcc is applied to the unselected bit lines BL1 and BL3 to form a bit line voltage, and then Vpgm is about 20V to the selected word line WL1, and the remaining n is not selected. -One word line is applied with the Vpass voltage which is a program inhibit voltage.

When the above condition is completed, the selected cell A by applying 0V to the bit line injects electrons into the floating gate by the FN tunneling phenomenon with the potential difference between the channel and the floating gate, and the threshold voltage Vth of the cell becomes positive. To complete. On the other hand, in the case of the cell B to be prevented from programming, the voltage Vpgm applied to the control gate is sequentially changed from the control gate electrode to the second dielectric film (220 in FIG. 3) and the first dielectric film (tunnel oxide film; 210 in FIG. 3). Assuming that the potential efficiency of the three capacitors formed of a silicon substrate, which is a depletion layer (200 in FIG. 3), is boosted in series with each other and the junction capacitance between the source / drain 300 is connected in parallel, For example, when Vpass = 10V, a potential of 7-8V is induced in the channel 400. Therefore, the boosted charge causes the cell B to have a small voltage difference between the floating gate and the channel, so that FN tunneling does not occur, thereby effectively preventing the program. You can.

When a malfunction occurs in the program operation as described above, a cell C in which a bit line is selected, a word line is unselected, and a cell B in which a word line is selected and a bit line is unselected are programmed.

First, in the case of an unselected cell located in the selected bit line such as cell C, if a Vpass voltage for program protection is applied instead of the Vpgm voltage, the cell C is programmed if the Vpass voltage is at least Vpgm or more. .

Therefore, the Vpass voltage should be less than Vpgm. The malfunction characteristic of the cell C according to the Vpass voltage shows the graph characteristic shown in FIG. On the other hand, as in the case of the cell B, the bit line is not selected, but when the word line is selected, the Vpgm voltage is applied to the word line and the lower the Vpass voltage is, the Vth of the transistor is changed, thereby exhibiting a malfunction characteristic as shown in FIG. 5. There is a limiting factor in program operation in flash memory.

As a method of realizing a wider operating range by improving such a problem, a method of using a dummy cell to increase the boosting voltage of the program protection cell among a plurality of cells in a string has been proposed. This is disclosed in patent application No. 95-16255 filed June 19, 1995 by the applicant. 2 shows this, and shows an equivalent circuit diagram of a NAND type flash memory cell according to the prior art. In the prior art of FIG. 2, the boosting voltage of the channel is increased by applying Vpgm to the control gate of the dummy cell. However, if it has a 16-stage cell structure, the dummy cell is programmed every time each word line is programmed. The condition is satisfied and the program continues. Therefore, electrons continue to accumulate in the floating gate, and the Vth of the dummy cell rises above the operating voltage Vcc.

This increased Vth does not turn on the dummy cell even when the control gate voltage of the dummy cell is applied to Vcc when the data of the cell is read. Therefore, the current applied from the bit line does not flow through the GSL transistor to the ground line, thereby causing a malfunction. In addition, there is a disadvantage in that a high voltage of Vpgm must be applied.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device which achieves more stable channel boosting and prevents program disturb.

That is, in the nonvolatile memory device, a non-selected cell transistor is programmed when a selected cell transistor is programmed to improve a program operation of a NAND type flash memory having a plurality of cells connected in series to form a string. It is an object of the present invention to provide a nonvolatile memory device that uses a wide Vpass voltage, which prevents malfunction, and realizes more stable circuit operation.

In order to achieve the above object, the present invention is a memory cell transistor connected to two or more in series while sharing a source and a drain with neighboring cells, a string select transistor connected in series to one end of the memory cell transistor, the memory cell transistor A first string having a ground select transistor connected in series to the other end, and a second string connected to the first string through a bit line contact, wherein the first and second strings are formed in parallel with the bit line. In a nonvolatile memory device,

A nonvolatile semiconductor memory device comprising one or more normal enhancement dummy transistors connected in series with a cell transistor in the string.

Preferably, the dummy transistor has the same structure as the string select transistor.

Also, a voltage higher or lower than a program protection voltage Vpass may be applied to the control gate of the dummy transistor to boost a potential of a channel of an unselected cell to a predetermined voltage during programming, thereby increasing the threshold voltage of the unselected cell. It is characterized by preventing the increase of Vth).

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

Looking at the conditions under which the non-selected cells (cell B of FIG. 2) inhibited by the program (inhibition) mentioned in detail in the prior art as follows.

In FIG. 2, a coupling value, which is a voltage ratio flowing into the floating gate with respect to the voltage applied to the control gate electrode, is 20 V for the Vpgm applied to the word line of the cell where the program is made, 10 V for the program prevention voltage. 0.6 and the electron injection by FN tunneling assumes that the potential difference is more than 8V, the boosting voltage induced in the channel is the voltage by Vpass (10V × 0.6 = 6V) + Vpgm ((20 × 0.6 = 12V) /n=0.75V, n = 8). Therefore, the voltage induced in the channel is 6.75V, and the potential difference with the floating gate voltage (20 × 0.6 = 12V) does not satisfy the condition that the FN tunneling occurs, thereby preventing the program. On the other hand, if the Vpass voltage, which is the program protection voltage, is 6V, the voltage maintained at the channel becomes 4.6V with the effect of 3.6V (6 × 0.6) and the program voltage ((20 × 0.6-3.6) / 8 = 1V). Thus, the condition that only FN tunneling takes place is not achieved and the program is prevented. On the other hand, if the number of cells connected to the string is increased to 16 or 32 to increase the density, the channel boosting contribution by the cells to which the program is applied is (20 × 0.6-3.6) /16=0.5V and (20 ×). 0.6-3.6) /32=0.25V, which is the condition under which the program occurs.

Therefore, in the prior art, in the case of the 16-stage cell, a dummy cell was added to apply the program voltage to the control gate in order to make the contribution by the program voltage equal to the 8-stage cell. As shown in FIG. 2, the dummy cell Cd ) Was added to apply the program voltage to the control gate. In FIG. 2, the dummy cell Cd is the same as the normal cell except that the voltage Vpgm is applied to the control gate. Therefore, when the voltage induced in the channel is increased in this structure, when 16 cells are sequentially programmed, the dummy cell enters a program operating condition and the program is continuously performed. Therefore, electrons continue to accumulate in the floating gate, and the Vth of the dummy cell is raised above the operating voltage Vcc.

This increased Vth does not turn on the dummy cell even when the control gate voltage of the dummy cell is applied to Vcc when the data of the cell is read. Therefore, the current applied from the bit line does not flow through the GSL transistor to the ground line, thereby causing a malfunction.

Therefore, the present invention is to solve the overprogram problem of the dummy cell as in the prior art of FIG. 4 is an equivalent circuit diagram of a NAND type memory cell according to an embodiment of the present invention. Comparing FIG. 4 and FIG. 2 with FIG. 1, it can be seen that another word line WLd is added between the nth word line and the GSL.

On the other hand, comparing FIG. 4 and FIG. 2, in FIG. 2, the transistor connected to the dummy word line WLd has a cell structure having a control gate and a floating gate. In FIG. 4, a dummy having the same structure as a GSL transistor is shown in FIG. The difference is that the transistor cell Cd 'is present. In addition, a voltage Vpgm is applied to the control gate of the dummy cell of FIG. 2, but a specific voltage is applied to the dummy transistor of FIG. 4.

As described above, when the dummy transistor structure proposed by the present invention is adopted, the dummy transistor cell employed in the present invention is composed of only the control gate and not the floating gate. The Vth of the dummy transistor does not change even when the voltage Vpgm is applied to the dummy transistor. Therefore, a malfunction due to an overprogramming of the dummy transistor cell during data reading can be prevented. Also, in the conventional dummy cell of FIG. 2 when the dummy cell is used, the maximum voltage at which the dummy cell boosts the channel voltage by boosting the channel voltage when the program voltage is 20 V is about 12 V. When the dummy transistor proposed in the present invention is used, Applying only 12V can boost the same voltage that the dummy cell can boost. Also, if Vpgm is 15V and Vpass voltage is 10V, the voltage to be applied to the dummy transistor is 15 × 0.6 (= 9V), which has the advantage of applying a voltage lower than the Vpass voltage.

Claims (3)

A memory cell transistor having at least two connected in series with the neighboring cells with a source and a drain, a string select transistor connected in series with one end of the memory cell transistor, and a ground select transistor connected in series with the other end of the memory cell transistor; A non-volatile memory device having a first string and a second string connected to the first string through a bit line contact, wherein the first and second strings are formed in parallel with a bit line. A nonvolatile semiconductor memory device comprising at least one normal enhancement dummy transistor connected in series with a cell transistor. The nonvolatile semiconductor memory device of claim 1, wherein the dummy transistor has the same structure as the string select transistor. The threshold voltage of the non-selected cell of claim 2, wherein a voltage higher or lower than a program prevention voltage Vpass is applied to the control gate of the dummy transistor to boost the potential of the channel of the unselected cell to a predetermined voltage during programming. Non-volatile semiconductor memory device, characterized in that to increase the (Vth).