KR0167611B1 - Method for fabricating transistor - Google Patents
Method for fabricating transistor Download PDFInfo
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- KR0167611B1 KR0167611B1 KR1019940038147A KR19940038147A KR0167611B1 KR 0167611 B1 KR0167611 B1 KR 0167611B1 KR 1019940038147 A KR1019940038147 A KR 1019940038147A KR 19940038147 A KR19940038147 A KR 19940038147A KR 0167611 B1 KR0167611 B1 KR 0167611B1
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- 238000000034 method Methods 0.000 title claims description 17
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
게이트 전극이 활성영역 전체를 덮지 않도록 형성함으로써 소자의 집적화에 기여할 수 있음과 동시에 트랜지스터의 온/오프 특성을 유지할 수 있는 트랜지스터 제조 방법에 관한 것으로, 반도체층 상에 소자분리막을 형성하고, 상기 소자분리막과 인접한 상기 반도체층 내에 불순물 도핑 영역을 형성하고, 상기 반도체층 상에 게이트 전극을 형성하되, 상기 게이트 전극과 상기 불순물 도핑 영역 사이에 상기 반도체층이 노출되도록 한 후, 상기 게이트 전극과 상기 불순물 도핑 영역 사이에 노출된 상기 반도체층 내에 이온을 주입하여 소오스 및 드레인 영역을 형성하는 것으로 이루어진다. 이에 의해 게이트 전극이 활성영역을 충분히 덮지 않고도 소자의 특성을 유지할 수 있으며, 소자의 안정성 및 집적도를 향상시키는 효과를 얻을 수 있다.The present invention relates to a transistor manufacturing method capable of contributing to the integration of a device and maintaining on / off characteristics of a transistor by forming a gate electrode so as not to cover the entire active region, wherein the device isolation film is formed on a semiconductor layer. Forming an impurity doped region in the semiconductor layer adjacent to the semiconductor layer, forming a gate electrode on the semiconductor layer, exposing the semiconductor layer between the gate electrode and the impurity doped region, and then doping the gate electrode and the impurity doped Ions are implanted into the semiconductor layer exposed between the regions to form source and drain regions. As a result, the characteristics of the device can be maintained without the gate electrode sufficiently covering the active region, and the effect of improving the stability and the degree of integration of the device can be obtained.
Description
제1도는 종래 트랜지스터의 평면도 및 단면도.1 is a plan view and a cross-sectional view of a conventional transistor.
제2a도 내지 제2c도는 본 발명에 따른 트랜지스터 제조 공정 단면도.2A through 2C are cross-sectional views of a transistor manufacturing process according to the present invention.
제3도는 제2c도의 평면도.3 is a plan view of FIG. 2C.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : P웰11 silicon substrate 12 P well
13 : 소자분리 마스트 패턴 14 : 필드산화층13: device isolation mast pattern 14: field oxide layer
15, 15' : 불순물 도핑영역 16 : 게이트 절연층15, 15 ': impurity doped region 16: gate insulating layer
17 : 게이트 전극 18 : 스페이서17 gate electrode 18 spacer
19 : 활성영역 20, 20' : 소오스 및 드레인 영역19: active region 20, 20 ': source and drain region
본 발명은 트랜지스터 제조방법에 관한 것으로, 특히 게이트 전극을 활성영역 전체를 덮지 않도록 형성함으로써 소자의 집적화에 기여함과 동시에 트랜지스터의 온/오프 특성을 유지할 수 있는 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method, and more particularly, to a transistor manufacturing method capable of contributing to integration of a device and maintaining on / off characteristics of a transistor by forming a gate electrode so as not to cover the entire active region.
SRAM(Static Random Access Memory), DRAM(Dynamic Random Access Memory)과 같은 반도체 소자에서 트랜지스터는 매우 중요한 구성요소이다.Transistors are a very important component in semiconductor devices such as static random access memory (SRAM) and dynamic random access memory (DRAM).
첨부된 도면 제1도는 종래 트랜지스터의 평면도 및 단면도를 나타낸 것이다. 제1도에 도시한 바와 같이 트랜지스터의 온/오프 특성을 유지하기 위하여 종래에는 게이트 전극(1)이 활성영역(2)을 충분히 덮도록 형성하는 '게이트 확장' 방법을 사용하였다.1 is a plan view and a cross-sectional view of a conventional transistor. As shown in FIG. 1, in order to maintain the on / off characteristics of the transistor, a 'gate extension' method in which the gate electrode 1 is formed to sufficiently cover the active region 2 has been conventionally used.
그러나, 소자의 집적도가 증가함에 따라 '게이트 확장'을 충분히 하기가 용이하지 않기 때문에 트랜지스터의 온/오프 상태를 정상적으로 유지하기 어려운 문제점이 제기되었다.However, it is difficult to maintain the on / off state of the transistor normally because it is not easy to sufficiently 'gate expansion' as the integration degree of the device increases.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 넓은 면적을 차지하는 '게이트 확장' 방법을 사용하지 않고도 트랜지스터의 온/오프 상태를 정상적으로 유지할 수 있도록 하는 트랜지스터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a transistor that can normally maintain an on / off state of a transistor without using a 'gate expansion' method that occupies a large area.
상기 목적을 달성하기 위한 본 발명은 트랜지스터 제조 방법에 있어서, 반도체층 상에 소자분리막을 형성하는 제1 단계; 상기 소자분리막과 인접한 상기 반도체층 내에 불순물 도핑 영역을 형성하는 제2 단계; 상기 반도체층 상에 게이트 전극을 형성하되, 상기 게이트 전극과 상기 불순물 도핑 영역 사이에 상기 반도체층이 노출되도록 하는 제3 단계; 및 상기 게이트 전극과 상기 불순물 도핑 영역 사이에 노출된 상기 반도체층 내에 이온을 주입하여 소오스 및 드레인 영역을 형성하는 제4 단계를 포함한다.The present invention for achieving the above object is a transistor manufacturing method, the first step of forming a device isolation film on a semiconductor layer; Forming a doped region in the semiconductor layer adjacent to the device isolation layer; Forming a gate electrode on the semiconductor layer, wherein the semiconductor layer is exposed between the gate electrode and the impurity doped region; And a fourth step of forming a source and a drain region by implanting ions into the semiconductor layer exposed between the gate electrode and the impurity doped region.
이하, 첨부된 도면 제2a 도 내지 제2c 도 및 제3도를 참조하여 본 발명의 바람직한 일시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings 2A to 2C and 3.
제2a 도 내지 제2c 도는 본 발명의 일실시예에 따른 NMOS트랜지스터 제조 공정 단면도이며, 제3도는 제2c 도의 평면도로서, 도면에서 11은 실리콘 기판, 12는 P웰, 13은 소자분리 마스크 패턴, 14는 필드산화층, 15 및 15'는 불순물 도핑영역, 16은 게이트 절연층, 17은 게이트 전극, 18은 스페이서, 19는 활성영역을 각각 나타낸다.2A to 2C are cross-sectional views illustrating a process for manufacturing an NMOS transistor according to an embodiment of the present invention, and FIG. 3 is a plan view of FIG. 2C, in which FIG. 14 denotes a field oxide layer, 15 and 15 'denote an impurity doped region, 16 denotes a gate insulating layer, 17 denotes a gate electrode, 18 denotes a spacer, and 19 denotes an active region.
먼저, 제2a도에 도시된 바와 같이 실리콘 기판(11)에 P웰(well)(12), 소자분리 마스크 패턴(13) 및 필드산화층(14)을 차례로 형성한다. 이때, 공지된 바와 같이 필드산화층(14)의 중심부는 두껍게 형성되고, 버즈비크(bird's beak)라 불리우는 필드산화층(14)의 양단은 중심부 보다 비교적 얇게 형성된다.First, as shown in FIG. 2A, a P well 12, a device isolation mask pattern 13, and a field oxide layer 14 are sequentially formed on the silicon substrate 11. At this time, as is known, the center of the field oxide layer 14 is formed thick, and both ends of the field oxide layer 14 called bird's beak are formed relatively thinner than the center.
상기 필드산화층(14)이 형성된 후, 30KeV 내지 60KeV의 엔지로 이온을 주입한다. 이때, 필드산화층(14) 중심부 아래의 상기 P웰(12) 내에는 이온이 주입되지 않고, 상기 필드산화층(14) 양단 아래의 P웰(12) 내에만 이온이 주입되어, 제2a도에 도시된 바와 같이 필드산화층(14)과 인접한 상기 실리콘 기판(11) 내에 고농도 불순물 도핑영역(15)이 형성된다.After the field oxide layer 14 is formed, ions are implanted into an engine of 30 KeV to 60 KeV. At this time, ions are not implanted into the P well 12 below the center of the field oxide layer 14, and only ions are implanted into the P well 12 below both ends of the field oxide layer 14. As described above, a highly doped impurity doped region 15 is formed in the silicon substrate 11 adjacent to the field oxide layer 14.
본 발명의 일실시예에서는 P웰(12) 상에 NMOS트랜지스터를 형성하는 과정을 예로써 설명하기 때문에 제2a도에 도시한 바와 같이 상기 고농도 불순물 도핑영역(15)을 p형으로 도시하였지만, N웰 상에 PMOS를 형성하는 경우에는 상기 고농도 불순물 도핑영역(15)은 n형이 될 수도 있다.In the embodiment of the present invention, since the process of forming an NMOS transistor on the P well 12 is described as an example, as shown in FIG. 2A, the heavily doped impurity doped region 15 is illustrated as p-type. When the PMOS is formed on the well, the highly doped impurity doped region 15 may be n-type.
제2b도 및 제2c도는 제2a도에서 하나의 필드산화층(14)과 인접한 부분을 확대하여 도시한 것이다.2B and 2C are enlarged views of portions adjacent to one field oxide layer 14 in FIG. 2A.
상기 고농도 불순물 도핑영역(15)을 형성한 후, 제2b도에 도시한 바와 같이 상기 소자분리 마스크 패턴(13)을 제거하고, 희생산화층(도시하지 않음) 형성 공정, 채널의 문턱전압 조절을 위한 이온주입 공정 등을 실시한다.After forming the highly doped impurity doped region 15, as shown in FIG. 2B, the device isolation mask pattern 13 is removed, and a sacrificial oxide layer (not shown) is formed, and the threshold voltage of the channel is controlled. An ion implantation process is performed.
이어서, 상기 P웰(12) 상에 게이트 절연층(16) 및 게이트 전극(17)을 차례로 형성한다. 이때, 상기 게이트 전극(17)의 단부는 상기 고농도 불순물 도핑영역(15)으로부터 소정거리를 두고 위치하여 상기 필드산화층(14)과 중첩되지 않는다. 즉, 상기 게이트 전극(17)과 상기, 고농도 불순물 도핑영역(15) 사이에서도 상기 P웰(12)의 표면 일부가 노출된다.Subsequently, a gate insulating layer 16 and a gate electrode 17 are sequentially formed on the P well 12. In this case, an end portion of the gate electrode 17 is positioned at a predetermined distance from the heavily doped impurity doped region 15 and does not overlap the field oxide layer 14. In other words, a portion of the surface of the P well 12 is exposed between the gate electrode 17 and the highly doped impurity doped region 15.
다음으로, 제2c도에 도시된 바와 같이 소오스 및 드레인 형성을 위하여 P웰(12) 내에 n형 불순물을 이온주입한다. 즉, 저도핑 드레인(lightly doped drain, LDD) 구조를 형성하기 위하여, 저농도의 n형 불순물을 이온주입하는 1차 n형 이온주입 공정을 실시해서 저도핑 소오스 및 드레인 영역(20)을 형성하고, 상기 1차 n형 이온주입 공정보다 비교적 농도가 높도록 2차 n형 이온주입 공정을 실시하여 고도핑 소오스 및 드레인 영역(20')을 형성한다. 이로써, 상기 게이트 전극(17)과 상기 고농도 불순물 도핑영역(15) 사이에 노출된 상기 P웰(12) 내에 저도핑 드레인 구조의 소오스 및 드레인 영역이 형성된다.Next, as shown in FIG. 2C, n-type impurities are implanted into the P well 12 to form the source and the drain. That is, in order to form a lightly doped drain (LDD) structure, a first n-type ion implantation process of ion implanting a low concentration of n-type impurities is performed to form a low-doped source and drain region 20, The second n-type ion implantation process is performed to have a relatively higher concentration than the first n-type ion implantation process to form the highly doped source and drain regions 20 '. As a result, a source and a drain region having a low doping drain structure are formed in the P well 12 exposed between the gate electrode 17 and the heavily doped impurity doped region 15.
상기 소오스 및 드레인 형성을 위한 1차 및 2차 n형 이온주입 과정에서, p형의 상기 고농도 불순물 도핑영역(15)에 n형 이온이 주입되어 저농도 불순물 도핑영역(15')으로 변환된다.In the primary and secondary n-type ion implantation processes for forming the source and drain, n-type ions are implanted into the p-type high concentration impurity doping region 15 and converted into a low concentration impurity doping region 15 '.
전술한 공정을 통하여 형성된 본 발명의 트랜지스터는 제3도에 도시된 바와 같이 적어도 게이트 전극이 활성영역(19)을 충분히 덮지 않고도 소자의 특성을 유지할 수 있으며, 소자의 안정성 및 집적도를 향상시키는 효과가 있다.According to the transistor of the present invention formed through the above-described process, as shown in FIG. 3, the characteristics of the device can be maintained without at least the gate electrode covering the active region 19 sufficiently, and the effect of improving the stability and integration of the device is improved. have.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
Claims (7)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| USD835928S1 (en) | 2014-06-13 | 2018-12-18 | Apple Inc. | Table |
| USD932814S1 (en) | 2018-07-09 | 2021-10-12 | Apple Inc. | Retail fixture |
| USD1015030S1 (en) | 2018-07-31 | 2024-02-20 | Apple Inc. | Retail fixture group |
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| USD835928S1 (en) | 2014-06-13 | 2018-12-18 | Apple Inc. | Table |
| USD907416S1 (en) | 2014-06-13 | 2021-01-12 | Apple Inc. | Table |
| USD932814S1 (en) | 2018-07-09 | 2021-10-12 | Apple Inc. | Retail fixture |
| USD1015029S1 (en) | 2018-07-09 | 2024-02-20 | Apple Inc. | Retail fixture |
| USD1015030S1 (en) | 2018-07-31 | 2024-02-20 | Apple Inc. | Retail fixture group |
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