KR0155523B1 - Secondary synchronizer of direct spread spectrum system - Google Patents

Abstract

The present invention relates to a secondary synchronizer of a direct spread spectrum system, and more particularly, to a secondary synchronizer of a direct spread spectrum system having a simpler structure and stable performance without using a loop filter or a voltage controlled oscillator of a conventional secondary synchronizer. The present invention relates to an early correlator or a late correlator for changing a sample of data to be used in a correlator from data received without using a loop filter or a voltage controlled oscillator used in a conventional secondary synchronizer. The on-time pseudo noise code used in the demodulator is directly implemented in the secondary synchronous device without generating each pseudo noise code for the present invention, so that the simple configuration and stable operation are effective.

Description

Secondary Synchronizer in Direct Spread Spectrum System

1 is a configuration diagram of a secondary synchronization device of a conventional spread spectrum system.

2 is a configuration diagram of a secondary synchronization device of a spread spectrum system according to the present invention.

3 is a detailed operation diagram of the secondary synchronizer according to the present invention.

* Explanation of symbols for main parts of the drawings

12: A / D converter 13: shift register

14: early correlator 15: late correlator

16: Subtractor 17: Input Selection Logic

18: mask memory 19: pseudo noise code generator

20: buffer 21: demodulator

The present invention relates to a secondary synchronizer of a direct spread spectrum system, and more particularly, to a secondary synchronizer of a direct spread spectrum system having a simpler structure and stable performance without using a loop filter or a voltage controlled oscillator of a conventional secondary synchronizer. It is about.

In a communication system using a spread spectrum communication method, synchronization between transceivers is very important.

In general, synchronization in spread spectrum communication is performed through a two-step process of initial synchronization and secondary synchronization. The present invention relates to secondary synchronization. The initial synchronization is to adjust the phase of the pseudo noise code of the receiver so that the pseudo noise code of the barrel and the receiver noise code are within 1/2 chip, and the secondary synchronization is used for more precise synchronization that is not achieved at the same time. It is a device that starts demodulation of data when synchronization is matched.

1 is a configuration diagram of a secondary synchronization device of a conventional direct spread spectrum system.

As shown in FIG. 1, the received signal received from the antenna passes through the power divider 1 and is identical to the multiplier 2 in the early path and the multiplier 3 in the late path. Receive data of power is supplied.

In each multiplier, the pseudo-noise code generated by the receiver itself is an early pseudo-noise code (11) that is 1/2 chip ahead of the pseudo-noise code that is actually used for demodulation of data, and a rate pseudo-noise code (10) that is 1/2 chip behind. Is supplied from the pseudo noise code generator 8 to perform a multiplication function with the received data.

The result of the multipliers 2, 3 is input to the subtractor 4 to output the difference between the early path and the rate path.

The error signal is obtained through the loop filter 5 to obtain an average value of the error signal, which is input to the voltage controlled oscillator 6.

If the early path and the rate path are different in this process, that is, if the pseudo noise codes of the transmitter and the receiver are not synchronized correctly, the subtractor generates the corresponding error signal. Since the input signal applied to the voltage-controlled oscillator is changed, the output frequency of the voltage-controlled oscillator 6 is changed, which is input to the pseudo-noise code generator 8 of the receiver and is the early pseudo-noise code 11 and the rate pseudo-noise code. By changing the phase of (10), it continues to operate until the outputs of the two correlators are the same, thereby serving as a synchronization tracking function.

When the synchronization is corrected, the demodulator 7 performs a data demodulation function with a pseudo noise code in which the transmitter and the receiver are synchronized.

In this method, the design of the multiplier and the loop filter, which are analog devices, are very difficult, and the performance of the voltage controlled oscillator must be excellent, which makes it difficult to design the whole system.

Accordingly, an object of the present invention is to provide a secondary synchronization device of a direct spread spectrum system having a simpler structure and stable performance without using a loop filter or a voltage controlled oscillator of a conventional secondary synchronization device.

In order to achieve the above object, the present invention provides an A / D converter which quantizes the data sampled by n times the data rate of the received signal to an appropriate size and converts the received signal into a digital signal; A shift register for buffering 1.5n data signals from the A / D converter; An early correlator and a rate correlator for correlating data input from the shift register with an on time pseudonoise code and a one chip backward pseudonoise code outputted from the pseudonoise code generator by a predetermined length, respectively; A subtractor for calculating a difference for the result of the correlator; Provide a different data selection value to the shift resist in accordance with the value input from the subtractor so that the shift resist sends the data to each correlator and sends data to the demodulator one half chip behind the data output to the correlator. Input selection logic; A mask memory for changing a phase of the pseudo noise code by providing a control signal and a pseudo noise code mask to the pseudo noise code generator as the position and environment of the transmitter and the receiver change; A pseudo noise code generator for receiving a control signal output from the mask memory and generating a pseudo noise code corresponding thereto; And a demodulator for detecting transmission data using the pseudo noise code generated from the pseudo noise code generator.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a configuration diagram of a secondary synchronization device of a direct spread spectrum system according to the present invention.

The first received signal is converted into a digital signal by the A / D converter 12 for digital signal processing.

The A / D converter 12 quantizes the data oversampled by n times the data rate of the received signal to an appropriate size and sends it to the shift register 13.

The shift register 13 buffers 1.5n data signals corresponding to 1.5 chips.

The shift register 13 outputs one data out of 1.5 n pieces of data corresponding to 1.5 chips to the correlator by the control signal output from the input selection logic 17, and compares it to 1/2 chip (n / 2 data). Sample) data is sent to the demodulator 21.

The data input to the early correlator 14 and the rate correlator 15 is one chip behind the on time pseudo noise code 21 (code used in the demodulator) output from the pseudo noise code generator 19. The correlation between the pseudo noise code 20 and a predetermined length is investigated.

This result is applied to the subtractor 16.

The subtractor provides the input selection logic 17 with the difference between the results of the two correlators.

The input selection logic provides different data selection values to the shift resister 13 in accordance with the input values, and the shift registers provide the corresponding data to each correlator.

In addition, it is necessary to change the phase of the pseudo noise code of the receiver as the position and environment of the transmitter and the receiver change. In this case, the pseudo noise code is provided by providing control signals to the mask memory 18 and the pseudo noise code generator 19. By providing a mask corresponding to the phase of the pseudo noise code is changed.

Through this process, the motivation tracking process is performed.

3 is a detailed operation diagram of the synchronization device according to the present invention.

When the oversampled data is input into the shift register 22, 1.5n data is always stored in the shift register 22 while the data passes through the shift register.

Each tab of each shift resist 22 is connected to switch boxes 23 and 24. This outputs only one data by the control signal provided by the input selection logic 25.

The data to be provided in the first half and the data to be provided to the demodulator should always be designed so that there is always a half chip difference.

That is, the correlator data should be in the form of 1/2 chip ahead of the demodulator data.

This principle makes it possible to implement a secondary synchronizer by using data that differs by 1/2 chip without generating early and rate pseudonoise codes.

Effects according to the present invention configured as described above are as follows.

First, it is possible to implement only a pseudo noise code generator of the receiver and a resist for a code behind one chip, without using a device having a difficult design such as an analog element or a voltage controlled oscillator of a loop filter used in a conventional secondary synchronizer. Do.

Second, all the signals are processed digitally, which results in clear results and can actually change the parameters required while the system is running, giving the system activeness, resulting in improved performance.

Claims (2)

An A / D converter for quantizing the data that is oversampled by the data rate of the received signal by n times with respect to the received signal to an appropriate size and converting the received signal into a digital signal; A shift register for buffering 1.5n data signals from the A / D converter; An early correlator and a rate correlator for correlating data input from the shift register with an on time pseudo noise code and a one chip backward pseudo noise code outputted from the pseudo noise code generator by a predetermined length, respectively; A subtractor for calculating a difference for the result of the correlator; A different data selection value is provided to the shift resist in accordance with the value input from the subtractor, the shift resist sends the data to each correlator, and sends the correlator to the demodulator a half chip behind the output data. Input selection logic; A mask memory for changing a phase of the pseudo noise code by providing a control signal and a pseudo noise code mask to the pseudo noise code generator as the position and environment of a transmitter and a receiver change; A pseudo noise code generator for receiving a control signal output from the mask memory and generating a pseudo noise code corresponding thereto; And a demodulator configured to detect transmission data using a pseudo noise code generated from the pseudo noise code generator. The display device of claim 1, wherein the shift resist comprises: a first switch box connecting only one tap to the early correlator according to a control signal provided from the input selection logic and outputting only one corresponding data; And a second switch box configured to output data, which differs by 1/2 chip, from the data output by the first switch box to the demodulator.