KR0152340B1 - Clock Synchronization System in Exchanges Accommodating Multiple Digital Trunk Lines - Google Patents

Abstract

The present invention is a system for synchronizing the clocks of an exchange by selecting one of the clocks extracted from a CO line normally operating in an exchange which accommodates a plurality of digital trunk lines, and in particular, by inputting one digital trunk line clock from the main control board of the exchange. The present invention relates to a clock synchronization system in an exchange that accommodates a number of digital trunk lines that allow clocks to be synchronized.

That is, according to the present invention, if the digital trunk line boards installed in front of each digital trunk line board are normal, only the digital trunk line board can output the clock extracted from the digital trunk line, and the clock synchronization of the exchange is Its purpose is to provide a clock synchronization system that is performed by the main control board to synchronize the clock of the exchange with the clock of one normal digital trunk line.

As a result, the number of mounting of the PLL circuit part is reduced, and the expensive clock transmission cable is unnecessary, which is very economical. Also, the characteristics of the signal are improved by transmitting the low frequency clock extracted from the digital trunk line. The processing operation can be improved.

Description

Clock Synchronization System in Exchanges Accommodating Multiple Digital Trunk Lines

1 is a block diagram of a clock synchronization system in an exchange that accommodates a general number of digital trunk lines.

2 is a block diagram of the clock output control circuit unit of the digital trunk line board in FIG.

3 is a block diagram of a clock synchronization system according to the present invention.

4 is a block diagram of a clock output control circuit unit of the digital trunk line board in FIG.

* Explanation of symbols for main parts of the drawings

10,100: Main Control Board

20-1 ~ 20-N, 200-1 ~ 200-N: Digital CO Line Board

21,110: PLL circuit part (Phase Locked Loop Circuit)

22: clock switching unit 30: clock transmission cable

300: Clock Control Cable

210: clock switching controller 220,240: end gate

250: transistor

The present invention is a system for synchronizing the clocks of an exchange by selecting one of the clocks extracted from a CO line normally operating in an exchange which accommodates a plurality of digital trunk lines, and in particular, by inputting one digital trunk line clock from the main control board of the exchange. The present invention relates to a clock synchronization system in an exchange that accommodates a plurality of digital trunk lines that allow clocks to be synchronized.

In general, an exchange accommodating digital trunk lines (E1, T1, ISDN trunk lines, etc.) synchronizes the clock of the exchange with a clock extracted from the digital trunk line, thereby operating at the synchronized clock. That is, in the digital trunk line boards 20-1 to 20-N of the exchanger to which multiple digital trunk lines are connected as shown in FIG. 1, the main clock for the operation of the exchanger is synchronized by synchronizing the clock of the exchanger with the clock extracted from the digital trunk line. Create In this way, the main clock of the exchanger synchronized with the digital trunk line clock generated by the digital trunk line boards 20-1 to 20-N is a high frequency signal of 10 MHz and a clock transmission made of a shield cable in which external noise is well blocked. The cable 30 is transmitted to the main control board 10 of the exchanger to operate the exchanger. Here, the clock transmission cable 30 is mounted while connecting each digital trunk line board 20-1 to 20-N.

On the other hand, each digital trunk line board (20-1 ~ 20-N) is the main clock of the synchronized switch and the self-generated from the other digital trunk line board to supply the normally generated main clock to the main control board (10) The main clock of the exchanger is switched according to the state of the digital trunk line clock extracted by the switch, and transmitted through the clock transmission cable 30.

In this case, the switching operation is performed by the clock output control circuit unit including the PLL circuit unit 21 and the clock switching unit 22 of FIG. 2 of each digital trunk line board 20-1 to 20-N. The CPU (Central Processing Unit) (not shown) built into the CO line boards 20-1 to 20-N monitors the clock status of the digital CO lines connected to each other. If the clock is damaged by controlling the clock switching unit 22 to be transferred to the main clock of the synchronized exchange coming from another digital trunk line board. Accordingly, the abnormal clock is not supplied to the main control board 10, and only other normal clocks are supplied to the main control board 10. Here, the main clocks of the synchronized exchanges generated by the digital trunk lines 20-1 through 20-N are generated by the PLL circuit unit 21 and output according to the operation of the clock switching unit 22.

The clock transmission in the clock synchronization system as described above is performed only through an expensive transmission cable in which external noise is well blocked due to the high frequency of the transmitted clock. In addition, it is possible to damage the clock transmitted when switching clocks in each digital trunk board, which may cause problems in the operation of the exchange.Because the high frequency clock is transmitted using a cable, the characteristics such as EMI (Electromagnetic Interference) are poor. You may.

Accordingly, in the present invention, if the digital trunk line boards mounted in front of each digital trunk line board are normal, only the digital trunk line boards can output the clock extracted from the corresponding digital trunk line, and the clock synchronization of the exchange is performed. The purpose of the present invention is to provide a clock synchronization system that is performed by the main control board to synchronize the clock of the exchange with the clock of one normal digital trunk line.

A clock synchronization system in an exchange accommodating a plurality of digital trunk lines according to the present invention for achieving the above object, synchronizes a clock of the exchange with respect to a clock in each digital trunk line extracted for operation of an exchange accommodating a plurality of digital trunk lines. In a clock synchronization system, a PLL circuit unit is generated by synchronizing a main clock for operation of an exchange in a main control board that controls the overall operation of the exchanger with a clock extracted from one of the plurality of digital trunk lines housed by the exchange. Including;

A digital trunk line board connected to a plurality of digital trunk lines each extracts a clock from a connected digital trunk line and transfers the clock according to the state of the clock through a common clock line of a back plane. Direct transmission to the circuit part, but if the digital trunk line board mounted on the front is normal, in order to output only the clock extracted from the digital trunk line board to include a clock output control circuit that controls each other through the clock control cable connected to the front do.

At this time, if the clock output from the first digital trunk line board is normal by the control operation of the clock control circuit, the output is only from the first digital trunk line board, and if an error occurs in the clock extracted from the first digital trunk line board, the clock is output from the second digital trunk line board. do. Likewise, if the clocks extracted from the first and second digital CO boards are not normal, the clock is output from the third digital CO board.

That is, the clock output control circuit section allows only one normal clock to be output to the PLL circuit section of the main control board.

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 3 is a block diagram of a clock synchronization system in an exchange which accommodates a plurality of digital trunk lines of the present invention, and FIG. 4 is a block diagram of a clock output control circuit included in the digital trunk line board in FIG.

Here, the configuration of the clock synchronization system according to the present invention includes one main control board 100 and a plurality of digital trunk lines 200-1 to 200 -N, as shown in FIG. 3.

At this time, the main control board 100 is responsible for the overall operation of the exchanger, the plurality of digital trunk line board (200-1 ~ 200-N) is configured as the number of the digital trunk line that the exchange is accommodated digital trunk line Signals through the interface to the main control board (100).

In addition, the digital trunk line boards 200-1 to 200-N extract clocks from the digital trunk lines and transmit them to the main control board 100 to generate a clock for the operation of the exchange, wherein each digital trunk line board ( 200-1 to 200-N control the clock output states of each other through the clock control cable 300 shown in FIG. 3 so that only one digital trunk line clock is output to the main control board 100. Here, the clock control cable 300 is mounted on the front of each digital trunk line board (200-1 ~ 200-N), the clock output control circuit unit (fourth) of each digital trunk line board (200-1 ~ 200-N) Are connected to each other via an input / output port (shown in FIG.).

After all, each digital trunk line board (200-1 ~ 200-N) is output to the main control board 100 without going through an expensive clock transmission cable that must cut off external noise, because the clock extracted from the digital trunk line is output directly unlike the existing Transmission is possible. That is, the digital trunk line clock is directly supplied to the main control board 100 through the common plane line of the back plane of the digital trunk line boards 200-1 to 200-N. In this way, the main control board 100 generates the main clock of the exchanger by synchronizing the clock of the exchanger with the clock of the digital trunk line boards 200-1 to 200-N. To this end, the PLL circuit unit (shown in FIG. 4), which has been conventionally configured in each digital trunk line board, should be configured in the main control board 100.

As a result, the clock output control circuits included in each of the digital trunk lines 200-1 to 200-N are configured as shown in FIG.

That is, the configuration includes the clock switching controller 210, the first and gate 220, the inverter 230, the second and gate 240, and the transistor 250.

The clock switching controller 210 is controlled by a CPU (not shown) built in each digital trunk line board 200-1 to 200 -N to change a state of an output signal, that is, a digital currently extracted. If the state of the CO line clock is normal, '1' is output, and if abnormal, '0' is output.

The first and gate 220 AND logic the output signal of the clock switching controller 210 and the clock output control signal output through the output port of the digital trunk line board mounted immediately before.

The inverter 230 inverts the output signal of the first and gate 220 and outputs the inverted signal.

The second and gate 240 is a logic circuit that is mounted immediately after the logic logic and the output signal of the output signal of the inverter 230 and the clock output control signal output through the output port of the digital trunk line board mounted immediately before. Output as a clock output control signal.

The transistor 250 is switched according to the state of the output signal of the first and gate 220 to transmit a clock extracted from the digital trunk line to the PLL circuit unit 110 of the main control board 100.

The operation of the clock output control circuit unit configured as described above will be described with reference to the first digital trunk line board 200-1 and the second digital trunk line board 200-2. Here, the configuration codes of the clock output control circuit unit in the digital trunk line boards 200-1 and 200-2 will be described in the same manner as those of the digital trunk line boards 200-1 and 200-2.

In this case, the clock extracted from the first digital trunk line board 200-1 is normal and abnormal.

If the clock extracted from the first digital trunk line board 200-1 is normal, the CPU of the first digital trunk line board 200-1 detects this and then controls the clock switching controller 210-1 to control '1'. To output. This is input to the first and gate 220-1, where the other input signal to be a logic target is always '1'. As a result, the output signal of the first and gate 220-1 becomes '1' to drive the transistor 250-1. The main control board as the digital trunk line clock input to the emitter stage according to the driving of the transistor 250-1 is output through the common clock line of the back plane of the first digital trunk line board 200-1. This is input by the PLL circuit unit 110 of (100). At the same time, the signal of '1' output from the first and gate 220-1 is inverted through the inverter 230-1 and input to the second and gate 240-1. The other input signal of the second and gate 240-1 is a signal that always maintains a state of '1' other than the signal of the clock switching controller 210-1 input to the first and gate 220-1. The resulting signal is '0'. The signal output as described above is input to the first end gate 220-2 of the second digital trunk line board 200-2 as a clock output control signal of the second digital trunk line board 200-2. As it is '0', the transistor 250-2 is not driven as the output of the first gate 220-2 becomes '0' regardless of the output signal of the clock switching controller 210-2. In addition, the output signals through the inverter 230-2 and the second and gate 240-2 also become '0', so that the clock is also applied to all the digital trunk lines mounted on the rear of the second digital trunk line board 200-2. There is no output. As a result, when the clock is output from the first digital trunk line board 200-1, the clock is not output from all other digital trunk lines.

On the other hand, when an error occurs in the clock extracted from the first digital trunk line board 200-1, the clock switching controller 210-1 outputs '0' under the control of the CPU. The output of 220-1 is '0'. As a result, the transistor 250-1 is not driven and the clock is not output.

At the same time, the signal output through the inverter 230-1 and the second and gate 240-1 becomes '1'. Accordingly, when the clock extracted from the second digital trunk line board 9200-2 is normal, the transistor 250-2 is driven by the clock output control signal output from the first digital trunk line board 200-1 so that the clock is driven. Is output. At the same time, the output control signal output through the inverter 230-2 and the AND gate 240-2 becomes '0' so that the clock is not output from the next digital CO board.

As described above, each digital trunk line board can supply a clock only from the digital trunk line board if the digital trunk line boards installed in the front in the order of mounting are normal. In other words, the digital trunk clock extracted from the digital trunk board mounted last is normal and cannot be output first.

As a result, an abnormality occurs in the exchange due to clock damage that occurs when the clock is transferred from the digital clock board from which the abnormal clock is extracted to the normal clock of another digital trunk board to transmit all normal clocks except the abnormal click. This eliminates the need for expensive clock transmission cables to transfer the main clock of the synchronized exchanges to the main control board.

As described above, according to the present invention, if the digital trunk line boards mounted in the front in the order of mounting in each digital trunk line board are normal, only the digital trunk line board can output the clock, and the clock synchronization of the exchange is By using the main control board, the number of mounting of the PLL circuit part is reduced, and the expensive clock transmission cable is unnecessary, which is very economical, and the signal characteristics are also improved by transmitting the low frequency clock extracted from the digital trunk line. It is possible to improve the signal processing operation of the exchange.

Claims (2)

In a clock synchronization system for synchronizing the clock of an exchanger with a clock of each digital trunk line extracted for the operation of an exchange accommodating a plurality of digital trunk lines, the exchanger in the main control board 100 controlling the overall operation of the exchange. And a PLL circuit section (110) which generates by synchronizing the main clock for the operation of the clock with the clock extracted from one of the plurality of digital trunk lines housed by the exchange; The digital trunk line boards 200-1 to 200-N, to which a plurality of digital trunk lines are connected, extract clocks from the connected digital trunk lines and convert the clocks according to the state of the clocks to the common clock of the back plane. Directly transmitted to the PLL circuit unit 110 of the main control board 100 via a line, but if the digital trunk line board mounted on the front is normal, the clock control cable connected to the front to output only the clock extracted from the digital trunk line board And a clock output control circuit unit for controlling each other through 300. A clock synchronization system in an exchange accommodating a plurality of digital trunk lines. According to claim 1, wherein the clock output control circuit unit and the clock switching control unit 210 to change the state of the output signal under the control of the CPU embedded in each digital trunk line board (200-1 ~ 200-N) and ; A first and gate 220 for AND logic an output signal of the clock switching controller 210 and a clock output control signal output through an output port of a digital trunk line board mounted in front of the clock switching controller 210; An inverter 230 for inverting and outputting the output signal of the first and gate 220; And outputs the clock output control signal output through the output port of the digital trunk line board mounted immediately before and the output signal of the inverter 230 to output as a clock output control signal of the digital trunk line board mounted immediately next. Two-and-gate 240 and; And a transistor 250 that is switched according to the state of the output signal of the first and gate 220 to transmit the clock extracted from the digital trunk line to the PLL circuit unit 110 of the main control board 100. Clock synchronization system in an exchange that accepts multiple digital trunk lines.