KR0150857B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device, comprising: a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines in order to increase atmospheric storage capacity and speed. A plurality of redundant memory cells, data transfer lines, a first decoder configured to receive at least one of a plurality of word lines in response to a first address signal, a word line selected by the first decoder A plurality of memory circuits for holding data read in a plurality of memory cells provided at intersections of the plurality of data lines, and data read in a redundant memory cell provided at an intersection of a word line selected by the first decoder and a redundant data line. Redundant memory circuits to maintain, between multiple memory circuits and data transmission lines A coupled transmission circuit, a redundant transmission circuit coupled between the redundant memory circuit and the data transmission line, a bad address memory circuit holding a defective address for a defective data line among a plurality of data lines, a second address signal receiving a second address signal; An address counter for performing a counting operation by outputting a counting address with the address of? Control the transfer circuit to transfer the data to the data transfer line, and when the defect address and the count address match, control the transfer circuit so that none of the data in the multiple memory circuits are transferred to the data transfer line, Before redundant to transmit to the data transmission line It has a circuit for controlling the circuit.

By using such a semiconductor memory device, atmospheric storage capacity and speed are increased.

Description

Semiconductor memory device

1 is a circuit functional block diagram showing one embodiment of a multi-port memory according to the present invention.

2 is a layout diagram showing one embodiment of the multi-port memory.

3 is a block diagram showing an embodiment of a specific internal configuration of the one memory mat MATO.

4 is a specific circuit diagram showing one embodiment of the memory mat.

FIG. 5 is a circuit diagram showing one embodiment of a column decoder and a predecoder (for both of driving circuits).

6 is a conceptual diagram showing one embodiment of address allocation in the multi-port memory according to the present invention.

7 is a circuit diagram showing one embodiment of a serial address counter SAMAC and a gray code counter GCC.

8 is a specific circuit diagram showing one embodiment of the memory mat.

9 is an explanatory diagram of a code conversion operation in the code conversion circuit.

Fig. 10 is a block diagram showing one embodiment of a redundancy method of bit lines in the multi-port memory.

Fig. 11 is a block diagram showing another embodiment of the redundancy method of bit lines in the multi-port memory.

Fig. 12 is a block diagram schematically showing the main parts of another embodiment of a multi-port memory according to the present invention.

Fig. 13 is a schematic timing diagram for explaining the transfer operation.

Fig. 14 is a block diagram schematically showing the main parts of another embodiment of a multi-port memory according to the present invention.

Fig. 15 is a schematic timing diagram for explaining the transfer operation.

16 is a block diagram showing another embodiment of a multi-port memory according to the present invention.

FIG. 17 is a circuit diagram showing yet another embodiment of the multi-port memory according to the present invention. FIG.

18 is a circuit diagram showing yet another embodiment of the multi-port memory according to the present invention.

19 is a schematic block diagram for explaining one embodiment of a normal mode and a regeneration mode in the semiconductor memory device according to the present invention.

20 is a schematic block diagram for explaining another embodiment of the normal mode and the reproduction mode in the semiconductor memory device according to the present invention.

21 is a circuit diagram showing one embodiment of a page mode recognition signal generation circuit.

22 is a timing diagram showing an example of the operation.

23 is a timing diagram showing another example of the operation.

24 is a timing diagram showing another example of the operation.

25 is a timing diagram showing another example of the operation.

Fig. 26 is a timing diagram showing another example of the operation.

27 is a timing diagram showing another example of the operation.

28 is a timing chart for explaining an example of the operation of the gray code counter GCC.

29 is a timing chart for explaining another example of the operation of the gray code counter GCC.

30 is a block diagram showing an essential part of one embodiment of the serial port portion in the semiconductor memory device according to the present invention.

FIG. 31 is a block diagram showing an essential part of another embodiment of the serial port portion in the semiconductor memory device according to the present invention; FIG.

32 is a circuit diagram showing one embodiment of a bad address memory circuit and an address comparison circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to semiconductor devices and, for example, relates to a technique effective for use in a multi (or dual) port memory having a random input / output port and a serial input / output port.

A multi-port memory having both a random access port and a serial access port is described in, for example, Niigai Electronics, page 243-264, published on March 24, 1986, issued by Nikkei McGraw-Hill.

With the development of computer graphics technology, there is a demand for the development of a multi-port memory, which has been designed to speed up the storage capacity in order to display high resolution colors.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a multi-port which aims at increasing the storage capacity and speed.

Another object of the present invention is to provide a semiconductor memory device suitable for increasing the storage capacity and speed.

It is still another object of the present invention to provide a semiconductor memory device capable of realizing an improvement in the manufacturing efficiency of a multi-port memory which aims at increasing the storage capacity and speed.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Brief descriptions of representative ones of the inventions disclosed herein are as follows.

(1) a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of data lines, (B) a redundant data line and the plurality of word lines. A plurality of redundant memory cells provided at the intersection, (C) a data transmission line, (D) a first decoder for receiving at least one of the plurality of word lines by receiving a first address signal, and (E) the first decoder A plurality of memory circuits for holding data read in a plurality of memory cells provided at intersections of the word lines selected by the plurality of data lines and (F) the intersection of the word lines selected by the first decoder with the redundant data lines. A redundant memory circuit for holding data read from the redundant memory cell provided in the unit; (G) between the plurality of memory circuits and the data transmission line; A combined transmission circuit, (H) a redundant transmission circuit coupled between the redundant memory path and the data transmission line, (I) a bad address memory circuit holding a combined address for a defective data line among the plurality of data lines, (J) an address counter that receives a second address signal and performs a counting operation with the second address as an initial value and outputs a counting address; (K) compares the combined address with the counting address, The transfer circuit is controlled to transfer data of a predetermined memory circuit corresponding to the count address to the data transfer line when the count address does not match, and when the defect address and the count address match, So that none of the data in the memory circuit is transmitted to the data transfer line. And simultaneously it controls the transmission circuit is a semiconductor memory device having a redundancy circuit for controlling the transmission circuit to transmit to the data transmission line to the information of the redundant storage circuit.

(2) When the serial input / output selection signal corresponding to the bad bit is detected, the semiconductor memory device selects the data latch corresponding to the redundant bit line instead.

According to the above means, even when the storage capacity is increased, the load is reduced according to two divisions of the serial I / O line, and high speed serial I / O can be executed. Responsiveness can be improved by outputting the head data outputted serially through the random access selection circuit. By using the gray code, the speed and the coupling noise can be minimized. Manufacturing efficiency can be improved by controlling the defect of a bit line. The memory mat is divided up and down two times in the direction of the serial input / output line, and the high and low division of the memory mat enables high speed. High integration can be achieved by using bit lines and sense amplifiers of non-selected memory mats as parallel transmission paths. The storage capacity can be increased by the bit lines for parallel data transfer which are commonly used for several memory mats. The power consumption can be reduced by the internally generated reproduction signal.

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated with an Example.

In addition, in all the drawings for demonstrating an embodiment, the thing which has the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

1 is a block diagram of one embodiment of a multi-port memory according to the present invention.

1 is a block diagram functionally expressed, and is not particularly limited, but the memory array MARY for random access has a storage capacity of 1024 (row) x 512 (column) = about 500K. When eight such memory arrays MARY are accessed in parallel, they are stored in units of color data consisting of x8 bits. Therefore, by using two such multi-port memories, color image data of 256 colors can be stored at a high resolution such as 1024x1024 or the like.

The address terminal consists of 10 bits of A0 to A9, and the address signal of the row system and column system is a low address strobe signal. And column address strobe signal In time, the row address signal is fetched into the row address buffer RAB, and the column address signal AYi is fetched into the column address buffer CAB or the serial address counter SAMAC. At this time, the address signal A9 of the most significant bit is invalid because there are only 512 column addresses as described above.

The serial address counter SAMAC performs the counting operation in synchronization with the serial clock pulse with the input column address as an initial value. This counting output is input to a gray code counter GCC, where it is converted to a gray code. The serial address signal converted into the gray code becomes the selection signal of the serial selection circuit SS.

The serial access memory SAM consists of a data latch circuit, and the series select circuit SS is provided between the input / output node and the serial input / output line extending in the vertical direction in the same drawing. The input / output node is connected to a 512 bit line of the memory array MARY via a transfer gate TRG. Therefore, data transfer is executed in parallel between the random access memory array MARY and the serial access memory SAM in units of 512 bits.

The serial main amplifier SMA is composed of eight unit circuits and amplifies the serial data transmitted through the serial input / output line and is output from the serial data terminals SI / O 0 to 7 through the serial output circuit SOB.

The serial write data input at the serial data terminals SI / O 0 to 7 are transferred to the serial input / output line via a serial input circuit SIB, which is written to each address of the serial access memory SAM designated by the serial select circuit SS. .

The address signal occupied in the low address buffer RAB is input to the row decoder RDEC, which is read out to select one word line of the memory array MARY.

The address signal fetched in the column address buffer CAB is input to the column decoder CDEC and decoded therein to form a selection signal of one bit line of the memory array MARY. Although omitted in FIG. 1, the column decoder CDEC is controlled by a column switch according to the selection signal to connect a pair of bit lines to a random input / output line. The main amplifier MA amplifies the signal of the random input / output line and inputs it to the random data output circuit DOB. The random data output circuit DOB outputs the read signal at the random data terminals RI / O 0 to 7.

The random write data input from the random data terminals RI / O 0 to 7 are transferred to the random input / output line through a random input circuit DIB, and to the bit line pair of the memory array MARY through the selected column switch circuit. Since one memory cell is coupled to the bit line pair by a word line selection operation, writing is performed.

In this embodiment, a signal path is provided in which the output signal of the random main amplifier MA is transmitted to the input of the serial data output circuit SOB. The reason is that the head data at the time of serial output is transmitted in parallel to the serial access memory SAM through the above-described transfer gate TRG, and then transferred to the input of the output circuit SOB through the serial selection circuit SS and the main amplifier SMA. This delays the output of the head data. In this embodiment, therefore, the column address signal for designating the head address is also fetched into the column address buffer CAB to execute the column selection operation by the column decoder CDEC. As a result, the data of the designated head address is output at high speed through the random column switch circuit and the main amplifier MA. This signal is transmitted to the input of the serial output circuit SOB via the signal path. As a result, the serially output data is output at high speed. By using this, the output preparation of the next data is executed by the serial circuit. Therefore, the selection operation of the head data in the serial output operation is dummy or omitted.

In this embodiment, pipeline full speed is executed between the serial address counter SAMAC and the gray code counter GCC which receives the same and forms a gray code signal in order to realize a high speed serial output operation. That is, when SAMAC sends out a binary address signal and GCC accepts it, SAMAC immediately executes a +1 increment operation. A decoder circuit is provided at the output of the GCC to form a selection signal for selecting one series selection circuit SS. Here too, pipeline transmission is performed as described using FIG. 7 below. Although not shown, a data latch circuit is provided at the output of the serial main amplifier SMA. As a result, when data output from the main amplifier SMA is fetched into the data latch, the main amplifier SMA immediately starts amplifying operation of serial data to be output next. In parallel with this amplification operation, the serial data output circuit SOB executes pipeline processing for outputting data fetched in the data latch.

By the above three stages of pipeline processing, the serial output operation can be speeded up.

In addition, when the storage capacity is increased as described above, the probability of generating a bad bit increases accordingly. The row-based bad address memory circuit RRDC stores a bad address in accordance with the presence or absence of cutting of a fuse or the like. This bad address and the low address fetched in the address buffer RAB are input to the address comparison circuit RAMRAC. When the address comparison circuit RAMRAC detects that the memory access is to a bad word line, its detection output is inputted to the low decoder RDCE, and the address selection operation of the bad word line is prohibited and the operation is switched to the selection of the spare word line. do. In this way, the defect bit of the row system can be saved.

In the conventional multi-port memory, no bit line defects such as bit line breaks or short circuits have been considered in order to perform serial serial input / output of data. However, when the storage capacity of about 4M bits as described above is attained, the probability of defects inevitably increases, and if left unchanged, manufacturing efficiency of the product is deteriorated. In this embodiment, therefore, redundant circuits are also provided in the column system.

In the column-based bad address memory circuit CRDC, a bad address is programmed in the same manner as described above with or without cleavage such as fever. In the serial mode, this bad address and the address signal generated by the serial address counter SAMAC are input to the address comparison circuit RAMCAC, and when it is detected that the memory access to the bad bit line is performed as described above, it is input to the serial selection circuit SS. Then, the serial access memory SAM corresponding to the bad bit line is prohibited and the SAM corresponding to the spare bit line is selected. In the random mode, this bad address and the address fetched in the address buffer CAB are input to the address comparison circuit RAMCAC, and if the memory access to the bad bit line is prohibited, the column selection corresponding to the bad bit line is prohibited, Select the corresponding column switch. In this way, the defect repair is also performed for the bit line failure, thereby increasing the product manufacturing efficiency of the multi-port memory.

Timing generation circuit TG is a control signal supplied from external terminals. , , , It receives the DSF, QSF, SC and SE, determines its operation mode, and simultaneously generates the operation timing signal of the internal circuit. signal Is the low address strobe signal, Is the column address strobe signal, Is the light enable signal, Is the data transmission control signal, SC is the serial clock signal, Is a serial enable signal.

2 is a layout diagram of one embodiment of the multi-port memory. Each circuit block and terminal in Fig. 2 is shown in accordance with the geometric arrangement on the actual semiconductor chip. In this embodiment, the four memory mats MAT0 to MAT3, which are divided into two at the right and left centering on the timing generating circuit TG for the purpose of high speed operation while achieving the above-described atmospheric storage capacity, are divided into two equal portions around the serial input / output line. It is divided up and down as much as possible. By such division, the length of the input / output line extending in the longitudinal direction in FIG. 2 is halved. As a result, the parasitic capacitance of the input / output lines is reduced, thereby making it possible to increase the transfer speed of data input and output in series.

A bus is provided by dividing the memory mats MAT0 to MAT3 up and down. These buses consist of an address bus, a data bus, and a control bus that carries various control signals. A circuit corresponding to each terminal, for example, BRAS or BAD, is an input buffer corresponding thereto, and DIB / DOB is an input / output buffer. The address buffers RAB, CAB, SOB, and the like are constituted by the corresponding input buffer or input / output buffer. In the case of performing the above two divisions, the random input / output operation can also be speeded up.

In addition, in order to execute only the serial high speed operation, the random access unit does not need to be divided into two top and bottom as described above. That is, it goes without saying that the random input / output unit may be provided only on the upper part or the lower part.

3 is a block diagram of a specific internal configuration of the one memory mat MATO. The other memory mats MAT1 to MAT3 also have the same configuration as the memory mat MAT0 shown as the representative example.

The memory mat MAT0 is divided into two in the horizontal direction, and two memory arrays MARY00 and MARY01 and two memory arrays MARY02 and MARY03 are arranged on the left and right sides of the two serial selection circuits SSOA and SSOB. Four serial access memories SAM00 to SAM03, sense amplifiers SA00 to SA03, transfer gates TRG00 to TRG03, and column decoders CDEC00 to CDEC03 are provided according to the memory arrays MARY00 to MARY03.

Low decoders RDEC0 to RRDEC3 are provided above the memory arrays MARY00 to MARY03. As the serial I / O lines extending in the vertical direction are divided into two at the midpoint for high speed operation, the main amplifiers SMA0L, SMA0U, and the random main amplifiers MA0L, MA0U are provided above and below the memory mat MATO. do.

GCCOB and GCCOA are gray code counters corresponding to the series selection circuits SSOA and SSOB. CPD00 to CPD03 are column predecoder, and RPD0 is a low predecoder.

4 is a detailed circuit diagram of one embodiment of the memory mat.

4, a detailed circuit diagram of the memory array MARY00, the sense amplifier SA00, the transfer gate TR00, and the serial access memory SAM00 is shown.

The sensor amplifier SA00 uses a known CMOS sense amplifier and performs an amplification operation of the memory cell by supplying operating voltages to the common source lines P00 and N00.

The memory cells arranged in a matrix in the memory array MARY00 consist of an address selection MOSFET and an information storage capacitor. The gate of the address selection MOSFET is connected to the word line WL, and the drain, which is an input / output node thereof, is connected to one of the pair of complementary bit lines arranged in parallel. HVC is the half precharge voltage of the bit line, and PC is the precharge signal. The serial access memory SAM is composed of the same CMOS latch circuit as the sense amplifier SA00.

5 is a circuit diagram of one embodiment of a column decoder and a predecoder (combining a drive circuit). The signals YR0 and YR1 are redundancy selection signals, and when they are formed, selection of the bad bit lines is inhibited and the operation is switched to the selection operation of the spare bit lines provided in each decoder.

6 is a conceptual diagram of one embodiment of address allocation in the multi-port memory according to the present invention.

FIG. 6 corresponds to memory mats MAT0 to MAT3 in the layout diagram shown in FIG. That is, in Fig. 6, row (x) addresses are assigned in the horizontal direction, and column addresses are assigned in the vertical direction. The address allocation of 512 in the column system is divided into two parts up and down as shown in FIG. 6, and one serial selection circuit performs data transfer in series of four bits. Therefore, serial data input / output can be performed in units of 8 bits in total in the vertical direction.

7 is a circuit diagram of one embodiment of a serial address counter SAMAC and a gray code counter GCC.

The outputs SY0 to SY8 of the serial address counter SAMAC are converted to gray codes SG0 to SG7 by an exclusive OR gate circuit. These gray codes are input to a predecoder circuit comprising a logic gate circuit and the predecode signal is fetched to an output latch circuit. When the predecode signal is fetched to this output latch circuit, the increment of +1 of the address counter SAMAC is started. By prioritizing the counting operation of the address counter in this manner, high-speed serial transmission is enabled by equivalently performing the pipeline operation of the address generation operation and the output of the predecode signal.

By forming the predecode signal with the gray code as described above, the signal changing per one address increment is unified, so that the speed and the coupling noise can be reduced. In addition, low power consumption can be achieved by unifying the changing signals.

The redundant outputs SR0 and SR1 are supplied to the predecoder to select the SAM corresponding to the reserved bit line in addition to the prohibition of the output.

8 is a specific circuit diagram of one example of the memory mat.

Since memory is accessed in units of 4 bits in correspondence with dividing the memory mat up and down as described above, the memory array MARY and the serial I / O line S100, , And random input / output line R100, , Is connected in correspondence with a four-bit bit line. Therefore, the redundant circuit is also provided with two pairs of four pairs of bit lines corresponding to redundant output SR0 and SR1 as described above.

9 is an explanatory diagram of the code conversion operation of the code conversion circuit.

Addresses 0 to 511 specified by the binary counter addresses SY0 to SY8 are converted to the same gray codes as SG0 to SG8. In this case, since only one bit is changed for one address increment operation, high-speed operation is possible because there is no need to provide a time margin as in the case of fetching the predecode output or the fetch of the binary signal. Become. In addition, since only one signal changes, the coupling noise between the signal lines can be minimized and power consumption can be reduced.

Fig. 10 is a block diagram of one embodiment of the bit line capacitance method in the multi-port memory.

In accordance with the above-mentioned storage capacity increase, the defect occurrence rate of the bit lines in the memory cell array is high, and in order to increase the manufacturing efficiency of the product, it is indispensable to perform defect repair on the bit lines. In this embodiment, the memory cell array RAM is divided into blocks, and two redundant bit lines are prepared for each. By using two blocks as a pair, an address of 0 to 4 is assigned to the redundant bit line. This utilizes the condition that the redundant bit line of another block is not used. That is, the redundant bit lines can be used between blocks. As a result, when there is no defect in one side, up to four pairs of bad bit lines can be saved in the other block.

11 is a block diagram of another embodiment of the redundancy method of bit lines in the multi-port memory.

In FIG. 11, a redundant word line is also provided in the word line. Similarly to the bit line, the redundant word line can be shared in two blocks, thereby improving the defect repair efficiency.

12 is a block diagram of another embodiment of a multi-port memory according to the present invention. 13 is a schematic timing diagram of the transfer pupil.

In this embodiment, several memory arrays are provided side by side for the serial access memory SAM for high storage capacity and high integration. In this way, a plurality of memory arrays can be associated with one SAM, thereby simplifying the circuit.

In this embodiment, when the memory array is selectively activated only, that is, only one word line is selected for the SAM, and data is transferred in parallel over the unselected memory array, the unselected memory array Is used as a signal line. In this case, since the drains of the address selection MOSFETs of several memory cells are connected to the bit lines, they have a relatively large parasitic capacitance. Therefore, since the signal transmission speed is delayed, the non-selected sensor amplifier is similarly inactive and is used as an amplifying circuit. That is, in FIG. 13, the sense amplifier SA is activated by the timing pulses SE1 and SE2 for transmission as shown in (a) and (b). Here, SH1 to SH4 are shared selection signals, and TE1 and TE2 are transmission signals provided for transmission as described above, and are turned low in the normal mode to turn off the corresponding switch MOSFETs.

In this configuration, since the column decoder CDEC and the serial access memory SAM can be arranged on the left and right side with several memory arrays interposed therebetween, the circuit can be greatly simplified, which is suitable for storage capacity. The SAM is provided with the above-described series selection circuit or register.

14 is a block diagram of another embodiment of a multi-port memory according to the present invention. Fig. 15 is a schematic timing diagram of the transfer operation.

In this embodiment, a dummy sense amplifier for transmission is provided in a portion for connecting between a pair of memory arrays centered on a shared sense amplifier. As a result, amplifying amplifiers can be provided at equal intervals with respect to the transmitted signal path.

16 is a block diagram of another embodiment of a multi-port memory according to the present invention.

In this embodiment, four memory arrays MARY0 to MARY3 and four memory arrays MARY4 to MARY7 are provided on the left and right of the serial selection circuit SS. Column decoders CDEC0 and CDEC1 are arranged on the left and right, and are responsible for column selection of the four memory arrays divided into two. As described above, when the serial selection circuit SS (SAM) is provided in common for a plurality of memory arrays MARY, parallel data transfer can be performed using bit lines or sense amplifiers of the other non-selected memory arrays MARY as described above.

However, when the bit line is used as the signal transmission path as in the above embodiment, a relatively large parasitic capacitance is added to the bit line by combining several memory cells. As a result, the signal transmission speed is delayed, and when the sense amplifier is operated as described above, the current consumption increases.

Therefore, in this embodiment, a signal line for parallel transmission as described below is provided.

17 is a circuit diagram of yet another embodiment of a multi-port memory according to the present invention. In this embodiment, a main bit line MBL0 or the like penetrating several memory arrays MARY0 to MARY3 or MARY4 to MARY7 for parallel transfer of data as described above is provided, and a memory cell or a sense amplifier is coupled to a sub bit line SBL0 or the like. . Then, a transfer switch MOSFET 09 or the like is provided between the main bit line MBL0 and the sub bit line SBL0 and the like to control the switch by the signal DT0.

In this configuration, since several memory cells are not connected to the main bit line, the parasitic capacitance can be reduced. As a result, the propagation delay time on the signal line can be reduced, so that signals can be transmitted at high speed. Although not particularly limited, the use of multiple metal wirings and the like can be configured to substantially overlap with the negative bit lines, so that the degree of integration is not impaired.

18 is a circuit diagram of yet another embodiment of a multi-port memory according to the present invention. In this embodiment, adjacent ones of the main bit lines as described above are shared. Data transmitted in parallel is divided into odd bits and even bits, and is time-divisionally transmitted in synchronization with the transmission signals DTOA and DTOB. In this configuration, the number of main bit lines can be reduced to about 1/2.

19 is a schematic block diagram for explaining one embodiment of the normal mode and the regeneration mode in the semiconductor memory device according to the present invention.

In this embodiment, both of the divided memory arrays MARY are activated during read and write operations in the normal mode NORMAL. As a result, the sense amplifier SA is also activated. On the other hand, in the regeneration mode REFRESH, an internally generated address counter is formed with one bit as a reproducing address. As a result, only one of the two memory arrays MARY is activated to select a word line for a reproducing operation. In response to this, only one of the sense amplifiers is also activated, so that the power consumption can be reduced in the regeneration mode.

20 is a schematic block diagram for explaining another embodiment of the normal mode and the reproduction mode in the semiconductor memory device according to the present invention.

In FIG. 20, the memory array MA has its word line divided at the center. The sense amplifier is also divided up and down in accordance with the division of this word line. Specifically, the common source line for activating the sense amplifier is provided separately in correspondence with the upper and lower sense amplifiers. In the reproducing mode, as shown in the upper left of the figure, one of the word lines is selected and the sense amplifier SA corresponding thereto is activated. On the other hand, as shown in the lower left of the figure, in the normal mode, word lines to which the same address is assigned among the divided word lines are selected together. Accordingly, both sense amplifiers SA are activated. In the case where the word lines are divided as described above, the driving circuit is provided by dividing the word lines up and down corresponding to each of the word lines. According to the division of the word line, the number of memory cells coupled to the word line is halved. This means that the load on the word line is reduced. Therefore, the circuit of the word line can also be made smaller in circuit size. As a result, for example, the pitch of the word line is narrowed due to the miniaturization of elements and wirings for the purpose of increasing the storage capacity. There is an advantage to lay out to fit.

In the upper right of the figure, a conventional memory array MA and a sense amplifier are shown for comparison. In the configuration in which the memory array MA and the sense amplifier SA are provided in one-to-one correspondence as in the related art, the current consumption cannot be reduced as in the regeneration mode. This is because in the dynamic memory cell, the memory capacitor is destructively read by the charge count with the bit line by the word line selection operation. Therefore, the dynamic memory cell requires a rewrite operation of amplifying the signal amount of the bit line by the sense amplifier at the time of reading and returning it to the original memory state. Therefore, when the word line is selected, it is necessary to activate the sense amplifier in a one-to-one correspondence accordingly.

As a means for dividing and operating the sense amplifier, a power supply line and a ground line are disposed on both sides of the sense amplifier, in addition to the arrangement for providing a common source line as described above, and a power switch MOSFET is provided for each unit circuit, and the gate It is good also as a structure which divides and provides the switch control signal supplied.

21 is a circuit diagram of one embodiment of a page all recognition signal generation circuit.

In the page mode, a column address must be input for the address that has conventionally been inputted as a row address. Therefore, it should be recognized that it is in page mode. The circuit for creating a signal which is activated only in the page mode is the circuit of FIG. The page mode signal PM Is at low level Changes from a low level to a high level as a result of changing from low level to high level. And Wow When both become high levels, the page mode signal PM is cleared to a low level. In this page mode, the signal PM is used to switch between the address pin, the I / O pin, and the address latch.

Address and mask data are input from the address pin and the I / O pin. However, since this data is input time-divisionally and the pins are used for several purposes, it becomes important to know which pins and when to fetch the data. Therefore, the signal PM is used. When inputting pixel data, it is convenient to add a function of masking with a specific bit for changing or correcting color. By providing a function of applying a mask (not changing) to a specific bit among such 8-bit pixel data, color change and the like are simplified.

22 is a timing diagram showing an example of the operation.

In Figure 22 In synchronization with the falling of the signal, the row address signal is fetched from the address terminal and the column address from the I / O pin. As the signal falls, the mask data is fetched from the address terminal. To identify this behavior Becomes high level.

23 is a timing diagram showing another example of the operation.

In the first cycle in FIG. In synchronization with the falling of the signal, the row address signal is fetched from the address terminal and the column address from the I / O pin. As the signal falls, the mask data and the remaining column addresses are fetched from the address terminal. From the second cycle, input only at the address terminal.

24 is a timing diagram showing another example of the operation.

In Figure 24 When the signal falls, the row address is input at the address pin and the column address is input at the I / O pin as described above. And then the signal If is at the high level, all data of the I / O pins are written to the memory cells (non mask). Signal about this Is low level The write operation is not executed except in the case where the address pin is at a high level in synchronization with the falling of (mask).

25 is a timing diagram showing another example of the operation.

In Figure 25, in the lead cycle When the signal falls, the row address is input at the address pin and the column address is input at the I / O pin. The input of the address may be reversed.

26 is a timing diagram showing another example of the operation.

In Figure 26, the column address is larger than the number of I / O pins. Input from the address pin at the lower of. When falling, the address pin coexists with the mask data and the column address. Other than that is the same as that of the said FIG.

27 is a timing diagram showing another example of the operation.

In Figure 27, the portion of the column address that is greater than the number of I / O pins When d is lowered, the same as in the case of Fig. 25 except that the input is made at the address.

The portion where the oblique line is added in the above operation waveform diagrams means Don't Care.

28 is a timing diagram for explaining an example of the operation of the gray code counter GCC.

For the above-described pipeline processing, a latch for holding the output of the predecoder is provided, and it is controlled by timing pulses? A and? B in a double configuration. As a result, as shown in FIG. 28, the time leg can be formed by only one gate.

29 is a timing chart for explaining another example of the operation of the gray code counter GCC.

FIG. 29 shows an example in which the nth address is defective and is switched to the redundant bit line. By using the gray code counter GCC as shown in FIG. 29, the redundancy circuit can be switched while maintaining regular periodicity of the serial output operation.

30 is a block diagram of an essential part of one embodiment of the serial port portion in the semiconductor memory device according to the present invention.

In this embodiment, spare arrays SARY0 and SARY1 are provided for the memory array MARY in order to correct the defect of the bit line. Corresponding to these spare arrays SARY0 and SARY1, a spare transfergate, a data register SDR (SAM) and a series selection circuit are provided.

When the address formed in the serial address counter SAM and the bad address are compared by the address comparison circuit COMP, and an access to the bad address is detected, a signal SRE0 or SRE1 is generated and a decode formed by the output of the gray code counter GCC. The output, that is, the selection signal of the serial selection circuit is invalidated and the preliminary serial selection circuit is switched to select the spare bit line instead of the bad bit line.

Such a serial port portion can be applied to a semiconductor memory device having only a serial port in addition to a multi-port memory.

31 is a block diagram of an essential part of another embodiment of the serial port portion in the semiconductor memory device according to the present invention.

In this embodiment, as in the above embodiment, spare arrays SARY0 and SARY1 are provided for the memory array MARY in order to remedy the bit line failure. Corresponding to these spare arrays SARY0 and SARY1, a spare transfergate, a data register SDR, and a serial selection circuit are provided.

In this embodiment, the selection signal of the serial selection circuit is formed by the shift register SR instead of the gray code counter GCC. That is, the serial selection circuit is sequentially selected by inputting logic 1 as the selection signal to the shift register SR and shifting it to the clock pulse.

In this configuration, the serial I / O line SIOi, And a switch circuit between the serial I / O buffer SIB / SOB. When the address formed by the serial address counter SAM and the bad address are compared by the address comparison circuit COMP, and an access to the bad address is detected, a signal SER0 or SRE1 is generated to turn the switch circuit to the OFF state. The switch circuit provided between the input / output buffers SIB / SOB is turned ON to connect the spare bit lines. As a result, the bad register is selected by the shift register SR and the continuity thereof is maintained, and the access of the bad bit is switched to the reserved bit when viewed in the input / output buffer SIB / SOB.

In addition to the multi-port memory, such a serial port unit can apply only a serial port to a semiconductor memory device.

32 is a circuit diagram of one embodiment of the above bad address memory circuit and the address comparison meeting. The storage of the defective address is not particularly limited, but a fuse means made of polysilicon or the like is used. The defective address is stored by selectively cutting the fuse means with a laser beam or the like. The stored bad addresses RY00 to RY08 and the counter outputs SY0 to SY8 formed by the serial address counter SAMAC are compared by a digital comparison circuit using a CMOS multiplexer. If both signals match, this comparison output goes to high level (logic 1). If all bits (0 to 8) of the address signal are coincident with each other, the coincidence detection signal SR0 passed through the NAND gate circuit and the inverter circuit is at a high level. As a result, the output of the predecoder of FIG. 30 or 31 is invalid or a serial input / output line SIOi, The switch circuit between the controller and the serial I / O buffer SIB / SOB. The spare bit line is selected by the signal SRE0.

The memory circuit and the comparison circuit of the defective address are the same in the redundant circuit of the row system.

The working effect obtained in the above embodiment is as follows.

(1) By dividing at least the serial I / O lines in the middle and providing the input / output circuits at both ends, the load on the serial I / O lines of the multi-port memory can be reduced, and the effect of achieving high storage capacity and high speed operation can be realized. Obtained.

(2) In the serial read mode, the column selection circuit for random access is also operated simultaneously and outputted through the serial output circuit using a readout that has passed through the column selection circuit for random access as the leading data output in series. The effect of speeding up the serial output is obtained.

(3) By serially switching the serial selection circuit to a serial input / output by the selection signal formed by the gray code counter, it is possible to achieve high speed, low coupling noise, and low power consumption.

(4) The combination of the serial input / output function and the random input / output function using the gray code counter achieves the effect of configuring a multi-port memory that realizes high speed operation.

(5) When the serial input / output selection signal corresponding to the bad bit is detected, the remedy can also be performed on the bad bit line by selecting a data latch corresponding to the redundant bit line instead. Therefore, a semiconductor memory device having a serial pod is provided. The effect of raising the manufacturing efficiency of the product is obtained.

(6) It has a random input / output function and a serial input / output function, and divides a memory mat up and down in the direction of a serial input / output line, and arranges an amplification circuit and a data bus corresponding to the divided serial input / output lines on the upper and lower portions of the memory mat. By doing so, the effect of realizing higher speed and higher storage capacity can be obtained.

(7) A bit line in an unselected memory mat provided between the selected memory mat and the serial input / output circuit is used as a signal transmission path, and the sense amplifier of the unselected memory mat is operated as an amplifier circuit. In this configuration, since the serial input / output circuit can be shared by a plurality of memory mats and special signal wiring for them is unnecessary, an effect of enabling storage capacity and high integration can be obtained.

(8) By providing serial input / output circuits for a plurality of memory mats and providing parallel data transfer bit lines commonly used for the plurality of memory mats, high integration and high speed can be achieved.

(9) The bit lines for parallel data transfer can share the adjacent ones, time-division, and achieve high integration and high speed.

(10) The effect of reducing current consumption in the reproducing mode is obtained by generating the reproducing address signal internally and reducing the number of memory mats which are simultaneously activated in the reproducing mode as compared with the normal mode.

As mentioned above, although the invention made by the present inventors was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary. For example, each of the above embodiments may not be applied only to a multi-port memory, but may be applied to a semiconductor memory device having only a serial access port or a semiconductor memory device having only a random access port in accordance with the features of each embodiment.

The present invention can be widely used as a semiconductor memory device.

Claims (5)

(A) A memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of data lines, (B) At the intersection of redundant data lines and the plurality of word lines A plurality of redundant memory cells, (C) a data transmission line, (D) a first decoder for receiving at least one of the plurality of word lines in response to a first address signal, and (E) a first decoder selected by the first decoder A plurality of memory circuits for holding data read from a plurality of memory cells provided at intersections of word lines and the plurality of data lines, (F) redundancy provided at intersections of word lines selected by said first decoder and said redundant data lines; A redundant memory circuit for holding data read from a memory cell, (G) between the plurality of memory circuits and the data transmission line A combined transmission circuit, (H) a redundant transmission circuit coupled between the redundant memory circuit and the data transmission line, (I) a bad address memory circuit holding a combined address for a data line having a coupling among the plurality of data lines, ( J) an address counter which receives a second address signal and performs a counting operation with the second address as an initial value and outputs a counting address; (K) compares the combined address and the counting address to the defective address and the The transfer circuit is controlled to transfer data of a predetermined storage circuit corresponding to the count address to the data transfer line when the count address does not match, and the plurality of memories when the defect address and the count address match. So that none of the data in the circuit is transmitted to the data transmission line The semiconductor memory device and at the same time control the transmitting circuit having a circuit for controlling the transmission circuit to transmit the redundant data to the transmission line the information of the redundant storage circuit. The memory device of claim 1, wherein the first address signal is a row address, the second address signal is a column address, the first decoder is a row decoder, and the plurality of memory cells and the plurality of redundant memory cells. Is a dynamic memory cell, and the plurality of memory circuits and the redundant memory circuit are static memory circuits. 3. The transmission circuit of claim 2, wherein the transmission circuit comprises a plurality of column switches having a transmission path between each of the plurality of memory circuits and the data transmission line, wherein the redundant transmission circuit is between the redundant memory circuit and the data transmission line. A semiconductor memory device comprising a redundant column switch having a transmission path. 4. The memory array of claim 3, wherein the memory array is a random access memory, the plurality of stored serial access memories, the transmission line is a serial input / output line, and the semiconductor memory device is a serial data terminal and the serial input / output line and the serial port. And a serial main amplifier coupled between the data terminals. A semiconductor memory device for selecting a data latch corresponding to a redundant bit line instead of detecting a serial input / output selection signal corresponding to a bad bit.