KR0142784B1 - Thin film transistor and their manufacture - Google Patents

Abstract

The present invention relates to a thin film transistor and a method of manufacturing the same, to form a thin film transistor structure that can reduce the leakage current and increase the operating speed.

The present invention relates to an island-type active layer, an upper gate formed through an insulating film on the active layer, and an edge gate formed through an insulating film on the side of the active layer, and an edge source formed on both sides of the upper gate on the active layer. And a source and a drain comprising an edge drain, wherein the transistor including the upper gate and the upper source and the drain has a predetermined channel length LT, and the edge gate and the edge source and the drain are formed. By providing a thin film transistor, wherein the transistor has a channel length L longer than the channel length LT, a thin film transistor-liquid crystal display device reduces leakage current of a transistor, lowers a threshold voltage of a gate, and increases mobility. Behavior of It makes it possible to increase the FIG.

Description

Thin film transistor and its manufacturing method

1 is a process flowchart showing a conventional thin film transistor manufacturing method

2 is a structure diagram of a conventional thin film transistor

3 is a conventional thin film transistor equivalent circuit diagram

4 is a plan view of a thin film transistor according to an embodiment of the present invention

5 is a structural diagram of a thin film transistor according to an embodiment of the present invention

6 is a plan view of a thin film transistor according to another embodiment of the present invention

7 is a plan view of a thin film transistor according to still another embodiment of the present invention

8 is a structural diagram of a thin film transistor according to another embodiment of the present invention

* Explanation of symbols for main parts of the drawings

1: Substrate 2: Buffer Layer

3: Active layer island 4: Gate saving film

5: gate electrode 6: source and drain regions

7: Insulation layer 8: Source and drain electrode

ST: Source transistor top DT: Drain top transistor

GT: Gate of upper transistor SE: Source of edge transistor

DE: Drain of edge transistor GE: Gate of edge transistor

L: Channel length of edge transistor LT: Channel length of upper transistor

The present invention relates to a thin film transistor (TFT) and a method for manufacturing the same, and more particularly, to a thin film transistor structure capable of reducing leakage current and increasing operating speed, and a method of forming the same.

The thin film transistor manufacturing process required for manufacturing an active matrix liquid crystal display is similar to the semiconductor device manufacturing process.

Referring to FIG. 1, a conventional thin film transistor manufacturing method will be described.

First, as shown in FIG. 1A, a buffer oxide film 2 is formed on a transparent insulating substrate 1, such as glass, quartz, sapphire, or sapphire, and the active layer 3 is formed thereon. As a silicon layer is formed. In this case, the silicon layer may be formed directly on the substrate without forming the buffer oxide film.

The silicon active layer 3 is formed of amorphous silicon, polysilicon or single crystal silicon by LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PRECVD (Remote CVD) or epitaxial process.

Next, as shown in FIG. 1B, the silicon active layer 3 is patterned in an island form.

Subsequently, as shown in FIG. 1C, a gate oxide film 4 is formed on the active layer island 3, and then a conductive layer such as doped polysilicon or aluminium is formed on the active layer island 3 to pattern the gate electrode. (5) is formed. As shown in the plan view shown in FIG. 1C, the active layer island 3 and the gate electrode 5 are formed to cross each other perpendicularly.

Next, as shown in FIG. 1 (d), the photoresist PR is used to cover a region other than the region where n ⁺ region is to be formed, and then ion implantation, for example, P (phosphorus) as an n-type impurity As shown in FIG. 1 (e), the source and drain regions 6 are formed in the active layer 3 of the Henry land type, and an n ⁻ channel transistor is formed. In the same manner, a P-channel transistor can also be formed, in which case B (Born) is used as an impurity. Then, an insulating film 7 is formed on the entire surface of the substrate, and then the insulating film is selectively etched to form the source and drain regions 6. After exposing the metal, the metal is deposited and patterned to form the source and drain electrodes 8 to complete the CMOS thin film transistor.

The most critical parameter for determining the performance of the thin film transistor fabricated as described above is the channel length L shown in FIG. The shorter the channel length L, the faster the operation speed of the device and the smaller the power capacity.

However, if the channel length is shortened, the channel leakage current increases rapidly, and the current thin film transistor is manufactured to have a channel length of 8-15 mu m.

In addition, longer channel lengths reduce channel leakage current, but degrade device performance.

On the other hand, drain leakage of short-channel transistors is known to occur due to edge transistors (see IEEE Transactions on electfon devices, VOL, ED-25, NO. 8, 1978).

Looking at the thin film transistor of FIG. 1 (e) in detail, as shown in FIG. 2, three transistors are formed on one island. The upper source S _T and the upper drain D _T and the upper gate G _T form an upper transistor, and the edge source S _E and the edge drain D _E and the edge gate G _E ) Forms two edge transistors on both edges of the island. The one upper transistor and the two edge transistors are connected in parallel as shown in FIG.

In this case, when the threshold voltage of any one of the two edge transistors is lowered, the edge transistor is turned before the edge transistor is turned on, thereby increasing the leakage current.

The present invention is to solve this problem, the channel of the upper transistor is formed short but the channel of the edge transistor is formed long to reduce the leakage current and increase the operating speed of the device to provide a thin film transistor and a method of manufacturing the same. Its purpose is to.

In the thin film transistor of the present invention for achieving the above object, the upper transistor including the upper gate, the upper source, and the drain has a predetermined channel length L _T , and the edge transistor including the edge gate, the edge source, and the drain includes: It is characterized by having a channel length (L) longer than the channel length (L _T ).

According to an aspect of the present invention, a method of manufacturing a thin film transistor includes forming an active layer on a substrate, patterning the active layer in an island shape, forming a gate insulating layer on the active layer, and forming a gate on the gate insulating layer. Forming a source and a drain region in each of the active charge regions on both sides of the gate by implanting the same, and forming the source and drain regions on both sides of the active layer rather than the entire width of the source and drain regions formed on the active layer. It is made so that the width is formed narrow.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

4 (a) and 4 (b) show a plan view of a conventional n-channel device and an n-channel device of the present invention, respectively. The present invention reduces the length of the channel by reducing the channel length L of the conventional thin film transistor. An edge gate portion having a length L _T and a mask pattern PR used in an ion implantation process for forming an n ⁺ region, which is a source and drain region 6, as shown in FIG. Is covered to a length L or more and then implanted to form source and drain regions.

5 shows a transistor structure of the present invention formed as described above, wherein a gate electrode 5 is formed over an active layer island 3 and an ion implantation process using the mask pattern PR on both sides of the gate electrode. As the source and drain regions are formed, the upper transistor formed on the active layer island 3 has a channel length LT, and the source S _E and the drain D _E of the edge transistor formed on the side of the active layer island have an upper portion. The transistor has a narrower width than the source S _T and the drain D _{T of the} transistor, and has a channel length L longer than the channel length L _T of the upper transistor.

The mask pattern PR may be formed as shown in FIG. 6 to form a channel of an edge transistor inclined to one side with respect to the gate 5.

When the transistor is manufactured as described above, the channel length of the edge transistor is formed to be long, so that the leakage current is reduced, and the channel length of the upper transistor is formed to be short, so that the operation speed of the device is increased.

On the other hand, as another embodiment of the present invention, as shown in Fig. 7 by changing the pattern of the gate electrode 5 can be obtained the same effect as the above embodiment.

In other words, the gate pattern 5 is formed to have a width L in the edge transistor region and a width L _T in the upper transistor region that is narrower than the gate width L of the edge transistor, and then an ion implantation process is performed. And a drain region.

FIG. 7 (a) The gate of the edge transistor is formed to be wider by the same length on both sides of the gate of the upper transistor, and FIG. 7 (b) shows the gate of the edge transistor on one side of the gate of the upper transistor. That is, it is formed wider only on the drain side.

In the transistor of the present invention formed as described above, the channel length L of the edge transistor is long as shown in FIGS. 8A and 8B, so that the leakage current is reduced, and the channel length L of the upper transistor is reduced. _{Since T} ) is short, the operation speed of the device can be increased.

The method of applying these two embodiments to the n ^- channel transistor has been described so far, but the effect of increasing the operation speed of the device to be applied in the same way to the p ^- channel transistor can be obtained.

As described above, according to the present invention, in the thin film transistor, since the channel length of the edge transistor is formed long and the channel length of the upper transistor is formed short, the leakage current of the transistor is reduced, thereby lowering the threshold voltage of the gate and moving it. By increasing the mobility, it is possible to increase the operating speed of the thin film transistor liquid crystal display. This allows operation with a small battery and extends battery life.

In addition, the increase in the operation speed and mobility of the thin film transistor-liquid crystal display device contributes to the improvement of the performance of the HDTV to which the thin film transistor-liquid crystal display device is applied.

Claims (13)

An island-type active layer, an upper gate formed through an insulating film on the active layer, and an edge gate formed through an insulating film on the side of the active layer, an upper source and an upper drain respectively formed on both sides of the upper gate above the active layer And a source and a drain each comprising an edge source and an edge drain formed on both sides of the edge gate on the side of the active layer, wherein the transistor including the upper gate and the upper source and the drain has a predetermined channel length (L). _{And T} ), wherein the transistor comprising the edge gate, the edge source, and the drain has a channel length (L) longer than the channel length (L _T ). The thin film transistor of claim 1, wherein the length of the upper source and the drain is longer than the length of the edge source and the drain. The thin film transistor of claim 1, wherein a channel of the transistor including the edge gate, the edge source, and the drain is formed to be biased toward one side of the gate. The thin film transistor of claim 1, wherein a width of the upper gate is smaller than a width of the edge gate. The thin film transistor of claim 4, wherein the edge gate is formed to be wider than the upper gate by a predetermined length only on one side of the upper gate. The thin film transistor of claim 4, wherein the edge gate is formed to be wider than the upper gate width by a predetermined length on both sides of the upper gate. Forming an active layer on a substrate, patterning the active layer in an island shape, forming a gate insulating film on the active layer, forming a gate on the gate insulating film, and ion implantation on both sides of the gate Forming a source and a drain region in the active layer region, respectively, but having a smaller width of the entire source and drain regions formed on both sides of the active layer than the width of the entire source and drain regions formed on the active layer. Thin film transistor manufacturing method. 10. The method of claim 7, wherein in the forming of the source and drain regions, ion and implantation of impurities are performed by using a mask pattern which blocks the active layer region including the gate portions on both sides of the active layer and exposes the other active layer regions. A thin film transistor manufacturing method comprising forming a region. The method of claim 8, wherein the mask pattern is formed to be symmetrical in both directions of a source and a drain region with respect to a gate. The thin film transistor manufacturing method of claim 8, wherein the mask pattern is formed to be biased in one of source or drain regions with respect to a gate. The method of claim 7, wherein the gate is formed to have a predetermined width L _T on the active layer and a width L larger than the width L _{T on} the side of the active layer. . The method of claim 11, wherein the gate portion formed on the side surface of the active layer is formed to be wider than the gate portion formed on the active layer so as to be symmetrical in both source and drain regions with respect to the gate. 12. The method of claim 11, wherein the gate portion formed on the side surface of the active layer is formed to be wider than the gate portion formed on the active layer only in one of a source or a drain region with respect to the gate. .