KR0140465B1 - Disk device of head positioning detection using phase servo pattern - Google Patents

Abstract

The peak detection of the servo frame read signal by the peak detection circuit is set in synchronization with the clock rising section, and the zero cross generation circuit section detects and resets the zero cross point of the read signal of the phase servo pattern to generate a duty pulse. . The position pulse is generated by integrating the duty pulse. Since there is a shift in timing between peak detection and zero cross detection, the duty ratio is measured to be adjusted to 50% in the on-track state of the target cylinder, and the timing of the reference clock and zero cross detection pulse is delayed.

Description

A disk device for reading the phase servo pattern to detect the position of the head.

1 is an explanatory diagram of a conventional phase servo pattern.

FIG. 2 is a timing chart showing the duty pulses in the first and third fields EVEN1 and EVEN2 when the head is located on each track of cylinder numbers 1, 2 and 3 in FIG.

FIG. 3 is a timing chart showing the duty pulse in the second field ODM when the head is located on each track of cylinder numbers 2 and 3 in FIG.

4 is a block diagram showing a hardware configuration of the present invention.

5 is a structural diagram of the disk enclosure of FIG.

6 is a side cross-sectional view of the head actuator of FIG. 4.

7 is a block diagram showing the function of the present invention.

8 is a flowchart showing the product shipment processing of the disk apparatus of the present invention.

9 is a flowchart showing the overall processing operation of the disk apparatus of the present invention.

10 is a configuration diagram of the position signal generating circuit of FIG.

11A to 11D are explanatory diagrams of magnetic recording of the servo pattern.

12 is a circuit diagram of the peak detection circuit of FIG.

13A to 13G are timing charts of the peak detection operation of FIG.

14A to 14C are timing charts showing problems in detecting peaks of phase servo readout signals.

FIG. 15 is a circuit diagram of the zero-cross detection circuit of FIG.

16A to 16D are timing charts of the zero cross detection operation of FIG.

17 is an explanatory diagram of the servo frame of the present invention recorded on the servo surface.

18A and 18B are explanatory diagrams of magnetic recording patterns in the training section and the marker section of FIG. 17;

FIG. 19 is an explanatory diagram of a magnetic recording pattern in the guard band index portion of FIG. 17; FIG.

FIG. 20 is an explanatory diagram of a magnetic recording pattern of two first half fields in the servo pattern section of FIG. 17; FIG.

FIG. 21 is an explanatory diagram of a magnetic recording pattern of the latter two fields in the servo pattern section of FIG.

22A to 22I are timing charts showing eight types of write signals having even numbers used for writing servo patterns.

23A to 23J are timing charts showing eight types of write signals having a radix number used for writing a servo pattern.

24 is a circuit block diagram of the master clock preparation circuit of FIG.

25 is a combination explanatory diagram of phase numbers of write signals used for writing a servo surface.

FIG. 26 is an explanatory diagram of a combination of phase numbers of a master clock used for cylinder switching. FIG.

27A to 27J are judgment state timing charts of the servo frame by the coincidence determination circuit shown in FIG.

28A to 28E are timing charts showing position detection during on-track.

FIG. 29 is a circuit diagram showing an integrated circuit of FIG.

30A to 30J are timing charts of the position detection operation by the integrating circuit of FIG.

31A to 31F are timing charts showing differences in duty ratios due to peak detection and zero cross detection.

32 is a circuit block diagram of the integral control unit of FIG.

33A to 33D are timing charts showing the duty ratio measurement operation by the integrating controller in FIG.

34 is a circuit diagram of the shifter shown in FIG.

35A to 35F are delay timing charts for the shifters in FIG. 34. FIG.

36 is a circuit diagram of the variable delay circuit of FIG.

37A and 37B are timing charts of delay operation of the 36th variable delay circuit.

FIG. 38 is an explanatory diagram of a delay time of a delay element used in the variable delay circuit of FIG.

FIG. 39 is an explanatory diagram of table information for determining a delay time of the variable delay circuit of FIG. 36; FIG.

40A to 40E are timing charts of delay adjustment to 50% duty ratio by the shifter and variable delay circuit of FIG.

41 is a flowchart of the duty adjustment process of the present invention.

42 is a flowchart of processing for setting delay time for a variable delay circuit.

43A to 43I are timing charts for duty pulse generation used for error measurement of an integrated circuit.

44A and 44B are timing charts for measuring integration error according to the present invention.

45 is a timing chart of a cylinder gain measurement operation according to the present invention.

46 is a flowchart of an integrated circuit adjustment process according to the present invention.

47 is an explanatory diagram of position prediction using only the velocity component.

48 is an explanatory diagram of a position side including the acceleration component of the present invention.

49 is a timing chart of a prediction process of acceleration components using the VCM drive current of the present invention.

50 is a flowchart of a searching process in the disk apparatus of the present invention.

51 is a flowchart of a position prediction subroutione of the present invention.

52 is an explanatory diagram of a head moving speed having a speed range of +4 cylinder to -4 cylinders.

Fig. 53 is an explanatory diagram showing the relationship between the cylinder number and master clock phase number used for cylinder switching.

FIG. 54 is a combination explanatory diagram of master clock phase numbers used in each field of FIG. 52; FIG.

55 is an explanatory diagram of a head moving speed having a speed range of +6 cylinders to -2 cylinders.

FIG. 56 is a combination explanatory diagram of master clock phase numbers used in each field of FIG. 55; FIG.

57 is an explanatory diagram of a head moving speed having a speed range of +7 cylinders to -1 cylinders.

FIG. 58 is a combination explanatory diagram of master clock phase numbers used in each field of FIG. 57; FIG.

59 is an explanatory diagram of a head moving speed having a speed range of +10 cylinders to +4 cylinders.

FIG. 60 is a combination explanatory diagram of master clock phase numbers used in each field of FIG. 59; FIG.

61 is an explanatory view of a shift pattern of the search speed according to FIGS. 52, 55, 57, and 59;

62 is a flowchart of a cylinder switching process in accordance with the search speed of the present invention.

63 is a servo frame explanatory diagram of a data plane of the present invention.

64 is an explanatory diagram of magnetic recording pantones in the first to third fields of the servo pattern portion in FIG.

65 is an explanatory diagram of a magnetic recording pattern in the fourth field of the servo pattern portion in FIG. 63;

FIG. 66 is an explanatory diagram showing a contrast between the first field of FIG. 64 and the fourth field of FIG. 65;

FIG. 67 is an explanatory diagram showing contrast between the second and third fields of FIG. 64; FIG.

68 is an explanatory diagram of position detection by a servo head on a servo surface.

FIG. 69 is an explanatory diagram for explaining a problem when the same pattern as the servo surface is recorded on the data surface and the position is detected by the readhead; FIG.

70 is an explanatory diagram of position detection by a servo pattern of the data surface of the present invention.

71 is a combination explanatory diagram of write signal phase numbers used to write the servo pattern of the data plane of the present invention.

72 is a combination explanatory diagram of master clock phase numbers used to read a servo pattern of the data plane of the present invention.

73 is a flowchart of a write operation of a servo pattern on a data surface according to the present invention.

74A to 74F are timing charts showing a phase servo pattern and read operation of data bit 0 according to the present invention.

75A to 75F are timing charts showing a phase servo pattern and a read operation of data bit 1 according to the present invention.

76 is a flowchart of the write processing of the present invention using a phase servo pattern.

77 is a flowchart of reading processing of the present invention using a phase servo pattern.

78 is an explanatory diagram of the yaw angle and the data head.

79 is an explanatory diagram of a write head and a read head mounted on a data head.

80A to 80B are offset explanatory diagrams of the read head at the maximum yaw angle of the inner and outer cylinders.

81 is an explanatory diagram of a change by linear interpolation of an offset with respect to a yaw angle.

82 is a flow chart of the yaw offset measurement of the present invention.

FIG. 83 is an explanatory diagram of an offset correction table created by the yaw angle offset measurement of FIG. 82; FIG.

84 is a flowchart of read processing involving yaw offset correction.

85 is a configuration diagram of a VCM drive circuit system in the present invention.

86 is an explanatory diagram of the center value measurement operation of the D / A converter for VCM.

87 is a flowchart of the center value adjustment process of the D / A converter for VCM according to the present invention.

88 is a flowchart of rezero processing according to the present invention.

Fig. 89 is a characteristic diagram of the relationship with the adjustment value when the evaluation function is the absolute position error integral value.

90 is a characteristic diagram of the relationship with the adjusted value when the evaluation function is a coarse time.

91 is a characteristic diagram of the servo system automatic adjustment according to the present invention in which the adjustment function is determined by the sum of the position error absolute integral value and the course time.

92A to 92C are timing charts showing absolute position error integrals and course time in search control.

Fig. 93 is an explanatory diagram showing the relationship between a write head and a read head mounted on a data head for an adjacent cylinder.

FIG. 94 is an explanatory diagram of an on-track slice value expanded by the padding process of the present invention. FIG.

95 is a flowchart of the padding process of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk apparatus for detecting the position of the head by determining the phase of servo information recorded on the disk surface. In particular, the disk apparatus for detecting the head position by detecting a zero-cross of the servo information reading waveform. It is about.

A magnetic disk device is a memory device that reads data from a track of a magnetic disk by a magnetic head and writes data to the track by positioning the head on a target track using the head in the radial direction of the rotating magnetic disk. In this magnetic disk device, it is indispensable to improve the recording density, especially the track density, in order to increase the storage capacity and to realize miniaturization. In order to realize a high processing speed, the search time of the head is required to be about 10 msec. Therefore, a digital circuit using a high speed processor is used for the positioning circuit of the head. With this digital servo circuit, the position needs only to be detected at sampling timing. The position detection circuit of the servo head also requires a circuit different from the analog servo position detection circuit.

In general, the two-phase servo pattern, which has been widely used, has a problem that the frequency band of the demodulation circuit of the position signal is increased and the noise is easily affected as the track density of the magnetic disk increases. In the two-phase servo pattern, the peak of the waveform obtained by reading the surge information recorded on the servo surface of the magnetic disk is detected, and the position is detected based on the height of the detected peak. The height of the peak is obtained continuously, but there is a problem that the influence of noise and level fluctuation on the magnetic disk medium surface directly affect the detection amount of the position.

Therefore, US Pat. Nos. 4,549,232, 4,642,562 and the like have proposed a method of recording a servo pattern as phase information and detecting and processing a position signal by the phase difference of the servo information.

1 shows a conventional phase servo pattern. The phase servo pattern divides the servo surface of the magnetic disk into four cylinder units of No. 0, No. 1, No. 2 and No. 3 and records servo information of different phases in the circumferential direction of each cylinder. That is, one phase servo pattern is divided into a first field EVEN1, a second field ODD, and a third field EVEN2. The servo pattern of the same phase is recorded in the first and third fields EVEN1 and EVEN2, and the reverse phase pattern is recorded in the second field ODD so that the position of the moving head can be read from the center position of the second field ODD.

2 shows detection of phase difference in the first and third fields EVEN1 and EVEN2. In this case, the servo patterns are recorded with one cycle of four reference clocks. That is, the case where a position in four cylinders of 0-3 can be detected is taken as an example. If the reference phase of the reference clock is set to the phase indicated by the thick line in the figure, the phase difference between the clock reference phase and the read pulse of the phase servo pattern is as shown in the phase difference signal 610 when the head is located at the position 600 which is the center of the second cylinder. 1/2 of the servo pattern period. When the head is at the position 620 which is the center of the first cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern is 1/4 period as indicated by the phase difference signal 630. When the head is located at the position 640 which is the center of the third cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern is 3/4 period as indicated by the phase difference signal 650. When the head is in the center of cylinder 0, the phase difference between the claw reference phase and the read pulse of the servo pattern is zero or one period.

3 shows the detection of the phase difference in the second field ODD. For example, when the head is located at the position 660 at the center of cylinder 2, the phase difference between the claw reference phase and the read pulse of the servo pattern is 1/2 cycle as indicated by the phase difference detection signal 670. When the head is at the position 680 which is the center of cylinder 3, the phase difference between the claw reference phase and the read pulse of the servo pattern is 1/4 period as indicated by the phase difference detection signal 690. Therefore, by detecting this phase difference, it is possible to detect where the magnetic head is in cylinders 0-3.

In the detection of the head position using this phase servo pattern, the peak of the read waveform from the servo surface is detected, the phase difference with respect to the clock reference phase is detected a plurality of times, and the phase difference is used as the position signal. Since the phase signal is detected a plurality of times, the position signal cannot be obtained continuously, but the device is hardly affected by noise by averaging. If the level fluctuation of the disk medium surface is small enough not to fluctuate the peak detection, the position detection can be precise. In the digital positioning control of the head, since position information is obtained for each sampling period, continuous information is not required. Therefore, position detection using a phase servo pattern is suitable.

In the conventional apparatus, a clock source having a fixed phase such as a crystal oscillator is used. Therefore, if the rotation of the disk varies, the phase difference with the servo pattern cannot be detected accurately, and the position detection accuracy is lowered. In crystal oscillators, the oscillation frequency varies with temperature. Therefore, the phase of the clock reference fluctuates, so that the phase difference with the servo pattern cannot be detected accurately, resulting in a low position detection accuracy. In the conventional apparatus, since the position detection processing by calculating the average value after detecting the phase difference is executed by a dedicated processor, when the search speed is increased, the processing speed of the processor cannot follow this, and thus high speed search is difficult.

In addition, in the conventional apparatus, when the head is moved in the range of 0 to 3 four cylinders, the phase difference changes in the range of 0 to 1 period (4 clocks). Therefore, in the case of the center cylinder 2, the phase difference has a continuous range of change by 4 clocks, but in the cylinders 0, 1, and 3, the change in phase difference is small. Therefore, the detection range of the head position becomes narrow in the course control, so that the search control is difficult.

In order to solve this problem, the inventors have proposed a servo position detection device for a disk device of US patent application Ser. No. 08/194663. In this disk apparatus, a training region in which timing information is recorded in front of the servo region of the disk is formed, and the PLL circuit serving as the clock generator is phase-locked to generate a reference clock synchronized with the servo pattern of the disk. Therefore, it is possible to generate a reference clock on the prescribed phase regardless of the disc rotational change or the environmental temperature change, thereby accurately detecting the phase difference with the servo pattern, thereby improving the detection accuracy of the head position. In the position signal detection process, the duty ratio is converted into a duty pulse in which the duty ratio varies from 0 to 100% in accordance with the head position in the first to third fields. Using this duty pulse, the capacitor is switched to the charging mode, the discharge mode, and the charging mode in the order of the first, second, and third fields, and integrated to detect the head position signal as the integrated voltage of the capacitor.

In this case, the phase servo information is such that the sum of the first and third fields is approximately equal to the second field. In the track state on the target cylinder, the duty ratio of the first, second, and third fields is 50%, 50%, 50% and the integral voltage is zero. By detecting the analog position signal by the integrating circuit, the processor only needs to A / D convert and read the integral signal, so that the position detection corresponding to the high-speed search operation can be performed. In addition, so-called cylinder switching for selecting a reference clock corresponding to the target cylinder from a plurality of phase clocks having different phases is automatically executed. Therefore, even if any of the 0 to 3 cylinders becomes the target cylinder, a phase signal is always obtained in which the target cylinder changes as a center cylinder in the range of ± 2 cylinders, so that the course control and the on track control can be surely executed.

In the proposed disk device, the position signal of the head is generated by detecting the peak of the read signal of the phase servo information obtained from the servo head. However, the peak detection is susceptible to the influence of noise and the jitter is easily generated. There is. In other words, the peak detection is performed by level-slicing the read signal obtained from the servo head and then differentiating the signal. Accordingly, there is a problem in that peak detection is performed at an incorrect timing due to noise mixed in the read waveform, and jitter causing the phase to be changed easily occurs. As a result, the positioning accuracy of the head is lowered.

In the proposed disk device, the duty signals obtained from the servo information in the on-track are ideally 50%, 50% and 50% in duty ratio in the first to third fields. In practice, however, it is not 50% due to the delay of the circuit. Therefore, in the on-track state, the duty ratio is 40%, 40%, 40%, for example, so that the duty pulse is reduced, or the duty ratio is 60%, 60%, 60%, and the duty pulse is enlarged. In on-track control, the head

(Excellent field)-(base field) = 0

Be on track on condition of. Therefore, even if the duty ratio is always 60% or 40%, there is no problem in the degree of on-track control. However, in the case of executing the search operation, if the duty ratio is 50% in the on-track state, the search operation can be performed in the range of -50% to + 50%, while for example, if the duty ratio is 40% in the on-track state, the search operation is performed. Can only run in the range of -40% to + 60%, which reduces the margin for fast search operation.

Since the analog integrating circuit is used, there is an error between the charging and discharging current of the capacitor, and even if the duty ratio is 50%, the integral voltage does not become zero, thereby lowering the position detection accuracy.

On the other hand, in the phase servo pattern, only the position detection in the range of 4 cylinders of the front and rear two cylinders centering on the target cylinder is possible, for example, the moving speed of the head defined by the number of moving cylinders for each sampling period of position detection. There is a problem in that the high speed search operation is not possible because the search speed is limited because it is suppressed within 4 cylinders.

In the course control in the case of detecting the head position at each sampling period, the next head position is predicted from the previous and current head position and the target speed is set. However, since the course control is executed according to the target speed patterns of acceleration, constant speed, and deceleration, the prediction based on simple speed only increases the deviation between the predicted position and the actual position, which may lead to a failure in position prediction and a search error.

In addition, a conventional disk apparatus using a two-phase servo pattern writes servo information to a specific cylinder on the data surface in order to realize temperature offset measurement or yaw angle offset measurement. Therefore, even when the phase servo pattern is used, it is necessary to write the phase servo pattern in the specific cylinder of the data plane as well. In this case, two data heads for writing and reading data planes are provided for the servo head for reading servo information on the servo plane. In particular, the read head uses a small MR head using a magnetoresistive element. Therefore, there is a problem that a continuous head position signal is not obtained from the read signal by the small MR head even when the phase servo pattern such as the servo surface is recorded on the data surface.

In addition to the above problems, the following various problems for securing the performance of the disk device must be solved. In other words, measurement and correction of the yaw offset, adjustment of the center value for the D / A converter installed in the driving system of the voice coil motor (VCM), rezero operation as an initialization process accompanying power-on-start, Automatic adjustment to the optimum state of the servo system, and the optimization of the on-track slice value during erasing.

The present invention provides a disk device that can detect a position using phase servo information and is resistant to noise and jitter. The disk apparatus of the present invention records phase servo information on the servo surface of the disk medium. That is, a plurality of servo frames are arranged in the circumferential direction of each cylinder with four cylinders on the servo surface as one unit. Each servo frame forms a training area, a marker area, an index / guard band area, and a servo area. The servo area is divided into a first field (EVEN1), a second field (ODD1), a third field (ODD2), and a fourth field (EVEN2). In the first and fourth fields EVEN1 and EVEN2, servo information having a phase change in position is recorded.

Timing information is recorded in the training area in front of the servo area in the rotation direction, and marker information defining the servo area is recorded in the marker area. In addition, a plurality of index information and guard band information are simultaneously recorded in the guard / index area. In the index / guard band region, one of the pieces of information is detected in accordance with the majority of the read results of the plurality of index information and the guard band information.

The read pulse is detected by the read pulse detection circuit section from the read signal of the servo frame read by the servo head. The read pulse detection circuit section is composed of, for example, a peak detection circuit section and a zero cross detection circuit section.

The detection circuit section detects the peak timing of the read waveform of the timing signal in the training area, the marker signal in the marker area, and the guard band signal in the index / guard band area to generate a read pulse (peak detection pulse).

The zero cross detection circuit section detects the zero cross timing of the servo information read signal and generates a zero cross detection signal used for head position detection. In addition, a low pass filter is installed in all stages of the zero cross detection circuit unit. The recording pattern of the phase servo information according to the present invention is recorded with a different pitch of phase 0.5 cylinder. The read signal waveform of the target cylinder is reduced because it is affected by the recording patterns on both sides recorded with the deviation of 0.5 cylinder. The peak becomes dull and jitter occurs in the peak detection pulse as a demodulation signal at the time of pig detection. Therefore, in the read signal of the phase servo information, a zero cross point is detected and a demodulated signal is obtained. In zero cross detection, a zero cross detection pulse can be obtained as a demodulation signal which is exactly synchronized with the phase pattern without being affected by dull peaks due to adjacent phase patterns. In addition, by providing a low pass filter at all stages, the noise of the read signal can be reduced, and the zero cross section can be immediately increased to increase the accuracy of the demodulated signal synchronized with the recording pattern of the phase servo.

Zero cross points of all read signals in the training area, the marker area, the index / guard band area, and the servo area can be detected. In addition, the peaks of all read signals can be detected.

The clock generation circuit section generates a reference clock having a reference phase which is in phase synchronization with the timing signal of the training area. The master clock creation circuit section sets the reference clock from the clock issue as a reference phase, creates a plurality of master clocks having different phases, selects a master clock of a phase corresponding to a target cylinder to position the servo head on the track, Outputs the selected master clock (cylinder switching function).

In the head position signal detection, the duty pulse generator circuit generates a duty pulse having a duty ratio corresponding to the phase difference between the reference phase of the master clock and the zero cross detection pulse. The integrating circuit unit integrates the duty pulse to generate a position signal indicating the position of the servo head.

The present invention provides a disk device capable of obtaining a duty pulse having a duty ratio of 50% in an on track state even when there is a circuit delay. In the initialization step immediately after the power is turned on, a duty measurement circuit section for measuring the duty ratio of the duty pulse in the on-track state of the servo head for a specific target cylinder is provided. The duty measurement circuit section may obtain an integrated signal indicating the duty ratio by inverting the duty pulses corresponding to the first and third fields of the servo information and output to the integration circuit section. The measurement result of the duty measurement circuit portion is sent to the duty adjustment circuit portion to adjust the duty ratio of the duty pulse to 50% in the on-track state of the target cylinder. The duty adjustment circuit section includes a first delay circuit section for delaying the reference timing of the master clock to reduce the duty ratio and a second delay circuit section for delaying the timing of the zero cross detection pulse to increase the duty ratio.

The first delay circuit section has a shifting circuit for delaying the master clock step by step at a predetermined time within one period of the reference clock, and selects one of the shift step outputs of the shifting circuit to give a desired delay amount to the master clock. do. The second delay circuit section includes a plurality of delay components (delay lines) having a fixed delay amount, selects the plurality of delay components, connects them in series, and gives a desired delay amount to the zero cross detection pulse clock.

In the present invention, when the reference clock is synchronously controlled by peak detection and the servo information is detected at the zero cross point, the duty ratio of the duty pulse due to phase difference detection in the on-track state inevitably deviates from 50%. However, by measuring the duty ratio and performing delay adjustment so that the duty ratio is 50%, the offset of the position signal obtained by the integrating circuit in the on-track state can be eliminated. This delay adjustment can also correct the deviation of the duty ratio due to the circuit delay.

The adjustment for setting the duty ratio of the duty pulse to 50% is applied as with the detection of the head position by the servo information recorded on the data plane. In other words, the duty ratio is measured and the duty ratio is delayed to 50% as in the state where the head is switched from the servo head by the selection circuit unit.

The present invention provides a disk device that maintains the integral circuit in an optimal state by removing various errors associated with the integral operation. Integral error measurement circuit section and integral error correction circuit section for integral error measurement are provided for the circuit adjustment of the integral circuit section. The integral error measuring circuit section measures the integral error by supplying a duty pulse corresponding to an on track state for moving the servo head to an arbitrary target cylinder position on the servo surface during the initialization of the power-on start. In other words, a duty pulse in which the duty ratio is 50% in the first to fourth fields of the servo information is simulated, and the duty pulse is supplied to the duty pulse generator circuit as a zero cross detection pulse (read pulse). After the initialization processing, the integral error correction circuit section corrects the position signal obtained from the integral circuit section based on the measured integration error to obtain an accurate position signal. As described above, the position can be detected with high accuracy by correcting to remove the change of the integral circuit from the position data obtained by the measurement of the integral error signal and A / D converted.

The integral error measuring circuit section measures a cylinder gain indicating the amount of head movement for each cylinder. The measurement during the initialization process of the power-on start corresponds to a state in which the servo head is moved in one direction by the distance of one cylinder from the generation of the duty pulse corresponding to the on-track state in which the servo head is moved to an arbitrary target cylinder. Switching to the generation of the duty pulse or the generation of the duty pulse corresponding to the state in which the servo head is moved in the opposite direction by the distance of one cylinder, the position change is measured by the integrating circuit section, respectively. Based on the above measurement results, the amount of change in position for each cylinder is obtained and used as the cylinder gain used for the head position control after the initialization process. In other words, the duty pulse generator circuit generates a duty pulse at which the duty ratio of 50% of the entire first to fourth fields of the servo information is 50% at the target cylinder position, and the duty ratio is 25%, 75 at the position where the head is moved by -1 cylinder. Generate duty pulses varying by%, 75%, and 25%, and duty pulses varying by 75%, 25%, 25%, and 75% in duty ratio at the position where the head is moved by +1 cylinder.

The present invention provides a disk device capable of a high-speed search operation of a head moving speed exceeding four cylinders per sampling period. In search control using phase servo information, the head position detection signal is obtained separately. Therefore, the search control circuit unit predicts the head position at the next sampling point for each sampling period and the speed detecting circuit unit for detecting the head moving speed during the search operation for each sampling period for producing the position signal, and causes the clock selection circuit unit to predict this position. The position prediction circuit part which selects the reference clock of the phase corresponding to the target cylinder obtained by this is provided.

The position prediction circuit section switches the target cylinders in each of the first to fourth fields of the servo region by the headlight moving speed during the search operation so that the clock selection circuit section selects the master clock of the corresponding phase. In the switching of the target cylinders, as the head moving speed increases, the number of switching stages in the first to fourth fields and the number of changes in the target cylinder in each switching operation increase.

For example, if the head moving speed defined by the number of moving cylinders in the sampling period is within the number of repeating cylinders of the servo information, the position prediction circuit section may cause the claw selection circuit section to switch the first to fourth fields without switching the target cylinder. Select the master clock of the corresponding phase in. That is, when the number of repetition cylinders of servo information is 4 cylinders, when the head moving speed is within the range of -4 cylinders to +4 cylinders, the master of the phase corresponding to the center target cylinder in the first to fourth fields without switching the target cylinders. Select the clock.

If the head moving speed defined by the number of moving cylinders in the sampling period exceeds the repetition cylinder of the servo information, the position prediction circuit divides the field into first, second, third and fourth fields and divides the target cylinder into two stages. Switch to select the master clock of the corresponding phase. For example, if the number of repeating cylinders of the servo information is 4, when the head moving speed is within the range of -2 cylinders to +6 cylinders, the first and second fields switch the target cylinders to target cylinders one cylinder smaller than the center cylinder. .

In the third and fourth fields, the target cylinder is switched to the target cylinder one cylinder larger than the center cylinder, and the master clock of the corresponding phase is selected.

In addition, when the head moving speed increases, the position prediction circuit separates the target cylinder into four stages of each of the first to fourth fields so as to select a master clock having a corresponding phase. In this case, it is only necessary to increase the number of switching cylinders in the head moving direction as 1, 2, 3 --- as the head moving speed increases.

Therefore, by switching cylinders in the first to fourth fields according to the head speed during the search operation, the head position can be accurately detected even when the range of the ± 4 cylinder, the limit of the position signal detection, is exceeded, thereby achieving a high speed search operation. .

The present invention provides a disk device capable of accurately predicting the position according to the movement of the head. In order to improve the position prediction accuracy in the search control, the position prediction circuit unit detects the acceleration of the head movement and predicts the head position at the next sampling point. For example, in the prediction including acceleration, the prediction position is calculated by adding the number of moving cylinders according to the acceleration of the head to the current position based on the head driving current. Therefore, by including the change of the head position due to the acceleration, the position can be detected more accurately and the search error due to the large deviation of the position prediction can be prevented. The present invention provides a disk apparatus for recording a phase servo pattern suitable for a small MR head (read head) mounted on a data head on a data surface. To this end, a data surface servo writing circuit section for writing servo information on the data surface is provided. In the data view input / output circuit section, the servo information having the phase change of position in the first and fourth fields EVEN1 and EVEN2 among the four separate fields is applied to the reverse phase change in the second and third fields ODD1 and ODD2. The servo information is recorded in each of the plurality of servo frames arranged in the circumferential direction of the specific cylinder of the data plane to form a servo area. In this example, since the MR head less than the servo head is used as the read head of the data head, even if the servo information such as the servo surface is recorded, the position signal which changes linearly with the head movement cannot be obtained. Therefore, for example, in the case where the servo information is recorded on the servo plane at the pitch of 0,5 cylinders, the data plane read-in circuit section writes the servo information at the pitch of 0.5 cylinders as the servo plane, and also the first field (EVEN1) and the first field. The servo information of the fourth field EVEN2 and the phase information of the second field ODD1 and the third field ODD2 are written so as to shift only by a pitch of 0.25 cylinders from each other.

As described above, in order to enable the servo information to be written on the servo surface, a write phase pulse of 16 phases is generated in synchronization with the leading and trailing edges of the reference clock. Searching the head by 0,25 cylinders at a time, the write pulse of the phase number in the first to fourth fields corresponding to each of the cylinder positions is selected and the servo pattern is written. In general, when the number of cylinder repetitions of the servo information recorded on the servo plane is N, the data plane servo write circuit section has a 1 / N difference in the reference clock frequency by (1/4) N periods from the phase of the reference clock at that time. A write pulse of (4N) type is generated by the write pulse obtained by dividing by. The data plane servo write circuit also selects a write pulse of a predetermined phase specified by the write cylinder from among the write pulses, and writes servo information corresponding to the servo information of the servo plane into the servo area of the data plane.

The present invention provides a disk apparatus capable of reading / writing data bits 0 and 1 from / to a specific cylinder outside the user area of the data surface by using the phase servo information by the head position detecting circuit section. In order to realize such a function, a data writing circuit section for writing data using servo information to a specific cylinder outside the user area of the data plane, and a data reading circuit section for reading the servo information written by the data writing circuit section and restoring the data. Install.

The data write circuit unit writes servo information using duty pulses having different duty ratios of the first and fourth fields and duty ratios of the second and third fields corresponding to the write data 0 and 1. For example, a duty pulse of 25%, 75%, 75%, 25% is written in the duty ratio of the first to fourth fields in correspondence with the write data bit 0. The servo information is written using duty pulses of 75%, 25%, 25%, and 75% of the duty ratio of the first to fourth fields in correspondence with data bit 1.

The data reading circuit section supplies the read signal of the servo information on the data plane to the duty pulse creating circuit section to generate the duty pulse. Or the integrating circuit section recovers data bits 0 or 1 from the signal obtained by integrating the duty pulse. Servo information of the data plane is written to an outer cylinder outside the user area of the data plane and used for off-track measurement of the data plane. The servo information is also written to the innermost cylinder and used to measure the yaw offset of the head drive mechanism.

The present invention provides a disk device capable of measuring and correcting the yaw offset of the read head when the data head is rotated by the head arm to be located in the cylinders of the inner and outer circumferences. During the power-on start initialization process, a data head having a write head and a read head integrally is positioned on each of the outer and inner cylinders of the data plane based on the servo information of the servo plane, and based on the servo information of each cylinder. The yaw offset of the read head caused by the rotation of the head arm is measured. The measured angle offsets of the inner and outer circumferences are used for the interpolation calculation to find the offset of the angle at each cylinder position. Create a correction table with the cylinder address as an index. The correction table may store the yaw angle offset in units of predetermined cylinders. The yaw offset offset correction corrects the yaw offset when, for example, a reading error of the data plane occurs, and executes a retry operation.

In the disk device of the present invention, the drive signal is supplied to the VCM according to the polarity and magnitude of the converted signal of the D / A converter for the VCM with respect to the reference voltage giving the midpoint. Therefore, there is a possibility that an error occurs between the output center value obtained by the D / A conversion center value of the input drive data and the reference voltage. Therefore, at the beginning and at the beginning of power-on start, the head drive data for the D / A converter is changed from the center value to find the error until the A / D converted output signal matches the reference voltage. After the initialization process, the device is calibrated to eliminate the center error by measuring the error from the head drive data supplied to the D / A converter.

The gain that determines the acceleration / deceleration of the target speed pattern used for speed control is the variable time from the course control to fine control by the search operation for the automatic adjustment of the servo system. Measure while doing. In the search operation, the absolute integration value of the phase error from the control mode to the fine control and the head on-track is measured while varying the gain that determines the acceleration / deceleration of the target speed pattern used for the speed control as an adjustment value. The servo system is automatically adjusted by detecting the optimum adjustment value as the minimum value using the sum of the course time and the integral value of the position error obtained from this measurement.

The on track slice value for determining the on track state at the time of erasing is changed to an enlarged value with respect to the on track slice value at the time of reading and writing.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description with reference to the drawings.

EXAMPLE

[Hardware Configuration]

In FIG. 4, the disk apparatus of the present invention is composed of a disk enclosure 10 and a drive controller 12. As shown in FIG. The disk enclosure 10 is provided with a spindle motor 14 for rotating the disk and a voice coil motor (hereinafter referred to as VCM) 16 for moving the head. The servo head 18 and the servo head IC22 are provided for reading the information of the servo surface of the magnetic disk. In addition, data heads 20-1 to 20-n and data heads IC24 are provided to read and write information on a plurality of data surfaces. Each of the data heads 20-1 to 20-n is provided with the write head and the read head integrally with the head portion. A magnetic head is used as the write head, and an MR head using a magnetoresistive element is used as the read head.

In this example, the core width of the servo head is the largest among the core widths of the servo head 18, the write heads provided in the data heads 20-1 to 20-n, and the read head, and then the core width of the write head is next. The core width of the readhead (MR head) is the smallest. For example, when the track pitch of the data surface is set to 7 µm, the core width of the servo head 18 is set to 7 µm which is approximately equal to the track pitch. In contrast, the core width of the write head provided in the data head is 6 m. In addition, the core width of the MR head as the read head is about 3 m, which is half the core width of the write head.

The drive controller 12 is provided with a control processor 26 as an overall control unit. The control processor 26 is coupled to the upper disk control unit via the interface circuit 28 so that a search command, a read command, a write command and the like receive various commands and execute corresponding processes. Below the control processor is installed a drive processor that executes head positioning control. As the drive processor 30, a digital signal processor is used. A position signal generation circuit 36 is provided to detect the head position with respect to the drive processor 30.

The read signal of the servo head 18 is input to the position signal generation circuit 36. In the present invention, phase servo information is recorded on the data surface of a disk medium. Based on the readout signal of the phase servo information, the position signal generation circuit 36 creates a position detection signal indicating the head position. The position signal from the position signal generation circuit 36 is converted into digital data by the A / D converter 38 and sent to the drive processor 30. The drive processor 30 controls the spindle motor 14 through the D / A converter 32 and the driver 34. The drive processor 30 also drives the VCM 16 through the D / A converter 40 and the driver 42 to perform head position control.

The positioning control of the head by the drive processor 30 performs search control for moving the head to the destination cylinder based on a search command and on track control for maintaining the on track state when the head reaches the destination cylinder. Search control consists of course control and fine control. The course control is a control for moving the head just before the target cylinder according to the target speed pattern. Fine control is control which switches the control mode from the speed control to the position servo control and pulls the head to the target cylinder when the course control reaches just before the target cylinder, for example, 0.5 cylinder.

On the other hand, an encoding / decoding circuit 44, a demodulation circuit 48, and a bias current control circuit 46 are provided to read and write data on the data surface of the disc medium. As a circuit of these read / write systems, a well-known circuit can be used as it is.

In addition, in the present invention, an equivalent phase servo pattern corresponding to a phase servo pattern of a servo surface in a specific cylinder of a data surface of a disk medium, that is, an inner circumference guard band region located at the end of the inner circumference with respect to the user region and an outer circumference guard band region located at the outer circumference It is recorded. In order to detect the position of the head by reading the phase servo pattern of the data plane with the read head provided in the data head, the position signal generation circuit 36 reads the read signal from the data head 24 via the demodulation circuit 48. ).

5 shows the internal structure of the disk enclosure of FIG. The eleven magnetic disks 50-1 to 50-11 are rotatably assembled by the support of the rotating shaft 54, and are rotated by a spindle motor (not shown) installed below. The head actuator 58 is provided on the right side of the magnetic disks 50-1 to 50-11.

The head provided at the tip of the head actuator 58 is integrally movable in the radial direction of each medium surface of the magnetic disks 50-1 to 50-11. In this embodiment, a disk of 5.25 inches in diameter is used as the magnetic disks 50-1 to 50-11, respectively.

6 is a longitudinal cross-sectional view of the head actuator of FIG. The head actuator 58 rotatably mounts the block 62 to the shaft 60 fixedly installed through the upper and lower bearings 56-1 and 56-2. On the right side of the block 62, the coil 64 of the VCM 16 is mounted. Eleven arms 66-1 to 66-11 are integrally provided on the left side of the block 62. Each tip of the arms 66-1 to 66-11 supports two heads through a pair of spring arms. In this embodiment, two heads are provided for the eleven magnetic disks 50-1 to 50-11. The upper nine heads are the data heads 20-1 to 20-19, and then the servo heads 18 are provided. The remaining ten heads following the servo head 18 are the data heads 20-1 to 20-19. The disk surfaces of the magnetic disks 50-1 to 50-11 that the data heads 20-1 to 20-19 face are the data surfaces for reading and writing data. On the other hand, the medium surface on the upper side of the magnetic disk 50-6 in which the servo head 18 is located becomes the servo surface in which servo information is recorded in all tracks. In the present invention, the phase servo pantone is recorded on this servo surface. The reason why the medium surface that the servo head 18 of the magnetic disk 50-6 in the center of the magnetic disks 50-1 to 50-11 opposes is the servo surface is that the magnetic disk is farthest from the servo surface. This is to minimize the offset amount as the position variation in each data plane with respect to the servo plane due to mechanical deformation due to temperature change by minimizing the distance to (50-1 to 50-11).

Configuring disk unit features

7 shows various control functions centered on positioning control of the head in the disk apparatus of the present invention. The hardware directly related to the control function of the drive processor 30 is the VCM 16, the servo head 18, the dare head 20, the D / A converter 32 for the VCM 16, and the position signal generating circuit ( 36 and the A / D converter 38 are shown. The data head is actually provided with a plurality of data heads, but for the sake of simplicity, one data head 20 is represented as a representative. Since the position signal generation circuit 36 creates the phase servo pattern of the servo surface or the phase servo pattern of the data surface, this switching is represented by the virtual switching switch 68.

The drive processor 30 of the drive controller 12 includes a servo system automatic adjustment unit 70, a data plane phase information write unit 72, and a data plane bit data write reader 74 as processing units for realizing the control function of the present invention. , Yaw offset measurement unit 76, yaw offset correction unit 78, DAC center value adjustment unit 80 for VCM, rezero processing unit 82, duty delay adjustment processing unit 84, integrating circuit adjustment processing unit 86, The cylinder switching control unit 90, the position prediction processing unit 92, the temperature offset measuring unit 94, the temperature offset correcting unit 96, and the padding processing unit 98, which are functions of the search control unit 88, are provided. Details of each processing unit installed in the drive processor 30 will be apparent in the following description, but the outline of these processing units will be described as follows.

The servo system automatic adjustment unit 70 inclines the acceleration and deceleration at the target speed pattern used for the course control in the final stage of the production process in which the phase servo pattern has been written by a dedicated device such as a servo writer on the servo surface. Adjust the value to determine the speed gain to the optimal value through the search simulation.

The data plane phase information writing unit 72 corresponds to the servo information of the servo plane in a specific cylinder of the inner circumferential guard band and the outer circumferential guard band of the data plane by using a write head (magnetic head) provided in the data head 20. By reading the read head (MR head) of the data head, a phase servo pattern unique to the data plane on which a position signal can be written is written. Writing of the phase servo pattern to this data surface is also executed in the final manufacturing process of the disk apparatus.

The data plane bit data writing and reading unit 74 stores data such as various setting data of the disk device or machine defense, etc. in a single state in which the drive controller 12 of FIG. 12 is not coupled to the upper disk control unit. Read / write from the blank area other than the user area using the write and read function of the phase servo information. The function of this data plane bit writing and reading unit 74 is also used at the final stage in the production process of the disk apparatus or at the construction of the system at the installation site.

The yaw angle offset measuring unit 76 uses a phase servo pattern written in the inner circumferential guard band region and the outer circumferential guard band region of the data plane by the data plane phase information writing unit 72 to control the head of the head by driving the VCM 16. The offsets at the innermost and outermost positions are measured. The yaw angle offset correction unit 78 corrects the offset of the read head upon reading the data surface by the read head based on the measurement result of the yaw angle offset measuring unit 76. The measurement processing by the yaw angle offset measuring unit 76 is executed at the time of the initialization processing by the power-on start.

The VAC DAC center value adjusting unit 80 adjusts the center value of the D / A converter 32 used to supply the drive current to the VCM 16 during the initialization process of the power-on start.

The rezero processing unit 82 executes a rezero operation, for example, to move the head located in the innermost contact start / stop region to the outermost side.

The duty delay adjustment processing unit 84 causes the duty ratio of the duty pulse generated at the time of on-track from the position signal generation circuit 36 to detect the read signal of the phase servo information by zero cross detection, and the deviation is 50%. Adjust the point so that you can create a duty pulse of 50% duty ratio on-track at all times.

The integrating circuit adjustment processor 86 adjusts the integral error of the integrating circuit for performing the integral operation based on the duty pulse provided in the position signal generating circuit 36 and the cylinder gain for displaying the amount of change in the head position signal per cylinder. Execute measurement.

The cylinder switching control unit 90 of the search control unit 88 switches the target cylinder for determining the pseudo master clock used to generate the position signal by the position signal generation circuit 36 based on the search speed. The position prediction processing section 2 needs to know the target cylinder where the head is located at the next sampling time and switch to the corresponding master clock at the next sampling time. Predict accurate location, including acceleration.

In the search control unit 88 of the present invention, a predetermined sampling period determined by the position period of the position signal generation of the position signal generation circuit 36 without using the track crossing pulse as in the conventional head position control by the two-phase phase servo. Each time, the course control (speed control) is executed using discrete head position signals.

As described above, the course control without using the track crossing pulse is disclosed in the specification of the head positioning control apparatus and control method for the disc driver according to International Application No. W092 / 11636 filed on June 27, 1991. In brief, the drive processor 30 calculates the head moving speed from the current head position and the previous head position, and predicts the head position at the next sampling to calculate the remaining number of cylinders for the target cylinder. The drive cylinder obtains the target speed from the target speed pattern preset by the remaining number of cylinders, calculates the current value of the VCM 16 corresponding to the difference between the actual speed and the target speed at that time, and converts the VCM ( 16).

The temperature offset measuring unit 94 searches for the data head in the phase servo pattern written in the outer guard band region of the data plane, and detects equally 16 offsets per cylinder, for example, according to the temperature fluctuation of the device. Create a temperature offset correction table with the rotation position as the address. The temperature offset correction unit 96 corrects the position control signal output to the D / A converter 32 during the on-track control by using the correction table created by the temperature offset measurement unit 94. Although it may be performed according to a predetermined time schedule at the time of power-on start and after power-on start performed by the temperature offset measuring unit 94, in the present invention, the disk device does not receive a command (idle state). ), The temperature offset processing is executed when it is assumed that there is no command execution.

When the padding processing unit 88 receives an erase command for a specific cylinder from the upper disc control unit, the on-track slice value indicating the allowable range of the head positioning signal in the erase operation is compared with the normal read operation or the write operation. Changes to an enlarged on track slice value. Therefore, even when the off track is large, the erasing operation is continued as long as possible in the range that the adjacent track is not erased.

FIG. 8 shows a series of processes executed in the final stage of the assembly process before product shipment in the processing unit of the drive processor 30 of FIG. In the final stage of the production process before shipping the product, first, in step S100, the phase servo pattern writing process for the servo surface is executed. The write processing of this phase servo pattern is normally performed using a dedicated servo writer. After the phase servo pattern is written on the servo surface, in step S200, the servo system auto-composing unit 70 is used to automatically adjust the servo system, that is, to optimize the adjustment value of the acceleration / deceleration of the target speed pattern in the course control. Run the process. After the automatic adjustment processing of the servo system is finished, the data surface phase information writing unit 72 is used to write the phase servo pattern for the data surface in step S300. In the following step S400, the data plane bit data writing and reading unit 74 is used to phase-serv the various data necessary for the disk unit alone into empty cylinders of the outer guard band area OGB1 and the inner guard band area IGB1 of the data plane. A write process for writing using the pattern is executed. In step S500, the data head is sequentially searched for the inner guard band region IGB1 and the outer guard band region OGB1 of the data surface on which the phase servo pattern is written, and is provided in the data heads in the innermost and outermost regions. The yaw offset of the read head (MR head) is measured, the yaw offset at each user position is calculated by the linear interpolation method, and the yaw offset processing is performed to create a correction table. The above processing is the processing at the final stage of the assembly process before shipment of the product. Processing other than this is executed through the initialization processing following the power-on start after the disk device is installed, the search control based on the high-order command after the completion of the initialization processing, and the read / write operation.

9 shows the overall processing operation in the operational state of the disk apparatus of the present invention. When the power-on start by the low power supply of the disk device is executed, first, basic initialization processing including program load initialization diagnosis and the like is executed in step S1. In step S2, the center value adjusting process of the D / A converter 32 for VCM is executed by the VCM DAC center value adjusting unit 80.

In step S3, the rezero processing unit 82 is operated to search for the head in the outer guard band region OGB1 to execute the rezero operation to find the absolute value of the cylinder address. Next, the flow advances to step S4 to execute the delay adjustment process of adjusting the duty ratio of the duty pulse at the time of on-track in the position signal generation circuit 36 to 50% using the duty delay adjustment processing unit 984. In the next step S5, the integrating circuit adjustment processing unit 86 is started to generate an error correction value by detecting the integral error at the time of on-track when the position signal of the integrating circuit provided in the position signal generating circuit 36 becomes zero. Further, the adjustment process of the integrating circuit is executed including the measurement of the cylinder gain which indicates the amount of change in the position signal when the head is moved by one cylinder. When the processing accompanying the series of wave-on start of the abnormal steps S1 to S5 is completed, the disk device is ready and waits for a command from the upper disk control unit in step S6.

In step S6, when an instruction accompanying the execution of the input / output instruction in the upper disk control unit is received, the instruction is decoded in step S7. In the case of a normal input / output request, a search command is first received, and therefore, the search operation is executed in step S8 to search control the head to the target cylinder to bring the head to an on track state. When the search operation is completed, the read operation or the write operation accompanying the read command or the write command subsequently obtained in step S9 is executed. If it is determined in step S10 that there is an error at the end of the read or write operation, the flow returns to step S9 to retry the read operation or the write operation. If there is no error, the status response indicating normal completion is returned to the upper disk control unit in step S11 to end the processing, and the flow returns to step S6 again. On the other hand, the disk device is idle while the device waits for the command in step S6. In the idle state, the flow advances to step S12 to determine whether or not the predetermined measurement device can execute the measurement process. If it is determined that the state where no command is received continues to be measured, the flow proceeds to step S13. In the present invention, the temperature offset measurement process by the temperature offset measurement unit 94 is executed.

Position signal creation circuit

FIG. 10 shows the position signal generation circuit 36 provided in the drive controller 12. FIG. The read signal of the servo surface read by the servo head 18 is amplified by the AGC amplifier 1000. The low pass filter (hereinafter referred to as LPF) 1010 removes noise of the amplified read signal, equalizes the waveform, and supplies the processed signal to the peak detection circuit 100 to detect the peak timing of the read waveform. Generate a read pulse). The magnetic writing and reading operations for the servo and data surfaces of the disc will be described below. Fig. 11A also shows a write signal. In the leading edge of the write signal, the polarity of the medium of FIG. 11B is magnetized to the N pole, and in the falling edge of the write signal, the polarity of the medium is magnetized to the S pole. In the read signal of Fig. 11C which reads the magnetization state of the medium, a positive read waveform is obtained at the magnetization part of the N pole of the medium, and a negative read waveform is obtained at the magnetization part of the S pole. In the actual servo pattern, since the gap between the N pole and the S pole is very short, the shape of the read waveform becomes a continuous sinusoidal waveform. FIG. 11D is a schematic diagram showing the magnetization state of the medium of FIG. 11B. The magnetization portion of the N pole is indicated by the solid line 212, and the magnetization portion of the S pole is indicated by the dotted line 214. The track recording state of the following phase servo pattern is represented by the solid line 212 indicating the N pole magnetization state and the dotted line 214 indicating the S pole magnetization state.

The peak detection circuit 100 of FIG. 10 detects the peak timing of the read waveform of the read signal of FIG. 11C and generates a peak detection pulse rising from the peak timing. Specifically, the peak detection circuit 100 creates a peak detection fence based on the gate signal and the differential pulse obtained by slicing the read waveform to a predetermined level.

12 shows one embodiment of the peak detection circuit 100. The operational amplifiers 1020 and 1030 constitute a sliding circuit. The operational amplifiers 1020 and 1030 are supplied with a read signal EO1 which is amplified by the AGC amplifier 1000 of FIG. 10 and whose noise is removed by the LPF 1010. The operational amplifiers 1020 and 1030 have a fixed slice voltage V _S applied to them. The operational amplifier 1020 for non-inverting amplification sets the slice voltage V _S on the positive side with respect to the midpoint voltage OV and generates EO 3 which slices the positive amplification portion of the input read signal EO 1 with the slice voltage V _S. . On the other hand, the inverted amplification operational amplifier 1030 sets the slice voltage to -V _S based on the midpoint voltage OV and the slice signal EO4 obtained by slicing the negative read waveform of the input read signal EO1 to the slice voltage -V _S. Occurs. On the other hand, the read signal EO1 is differentiated into the differential circuit 1040 and supplied to the zero cross detection circuit 1050. The differential waveform obtained by differentiating the read signal EO1 has a zero cross point at the peak portion of the read signal EO1, and thus the zero cross point is detected by the zero cross detection circuit 1050. The zero cross detection signal EO5 becomes a signal for detecting the peak timing of the read signal EO1.

The slice signal EO3 is supplied to the D terminal of the D-FF (D flip-flop) 1060, and the slice signal EO4 is similarly supplied to the D terminal of the D-FF 1070. In this example, the clock terminal C of the D-FF 1070 becomes an inverting input terminal. Each clock terminal of the D-FFs 1060 and 1070 is given a zero cross detection signal. Slice signals EO3 and EO4 respectively function as gate signals. After the slice signal EO3 rises to the logic level 1, when the zero cross detection signal EO5 rises to the logic level 1 as well, the set operation of the D-FF 1061 is performed so that the Q output becomes the logic level 1. On the other hand, if the slice signal EO4 rises to logic level 1 and the zero cross detection signal EO5 falls to logic level 0, the set operation of the D-FF 1070 is performed so that the Q output becomes logic level 1. The OR circuit 1080 takes the OR of the Q outputs of the D-FFs 1060 and 1070 to trigger the one-shot multivibrator 1090 to generate the peak detection signal EO6 of a predetermined pulse width. The peak detection signal EO4 is fed back to each reset terminal R of the D-FFs 1060 and 1070 and reset for the next peak detection.

The operation of this peak detection circuit will be described next.

The read signal from the servo head causes waveform distortion as shown in FIG. 13A, but the read signal becomes the filter output signal EO1 in FIG. 13B and is supplied to the peak detection circuit by passing through the filter 1010 in FIG. For the filter output signal EO1, the slice voltages + V _S and -V _S are set in the operational amplifiers 1020 and 1030. Accordingly, the operational amplifier 1020 generates the slice signal EO3 of FIG. 13d as a gate signal. The operational amplifier 1030 similarly generates the slice signal EO4 of FIG. 13E as a gate signal. On the other hand, the differential signal EO2 from the differential circuit 1040 has a zero cross point at the peak timing of the read signal of Fig. 13C. The differential signal EO2 is supplied to the zero cross detection circuit 1050 to generate the zero cross detection signal EO5 of FIG. 13f synchronized with the zero cross point. The zero-cross detection signal 1050 is regarded as inputting the differential signal EO2 of FIG. 13c to the positive input terminal and the signal inverting the differential signal EO2 to the negative input terminal when viewed from the midpoint voltage which becomes OV. As a comparison output between the input signal of the positive input and the negative input, the zero-cross detection signal EO5 of FIG. 13f which rises to logic level 1 in the positive half cycle of the differential signal EO2 is generated.

When the zero-cross detection signal EO5 rises to logic level 1 while the slice signal EO3 is at logic level 1, the Q output of the D-FF 1060 becomes logic level 1 and passes through the OR circuit 1080 to form a single yarn multivibrator ( 1090, one of the peak detection pulses is generated. Subsequently, after the slice signal EO4 rises to logic level 1, when the zero cross detection signal EO5 falls to logic level 0 in the next zero cross detection, the set operation of the D-FF 1070 is performed so that the Q output becomes the logic level 1 and the OR circuit. Through 1080, the single yarn multivibrator is triggered to generate the next peak detection pulse EO6.

The output of the peak detection circuit 100 is given to the PLL circuit 102 and the marker detection circuit 104. The PLL circuit 102 oscillates the reference clock in synchronization with the peak detection pulse based on the reading of the timing signal recorded in the training region at the head of the servo frame, which will be apparent from the following description. The oscillation frequency of the PLL circuit 102 is 20 MHz in this embodiment, so that one clock period? Is 50 nsec. The marker detection circuit 104 detects a marker signal of the marker region following the training region of the servo frame.

The guard band index detection circuit detects a guard band signal and an index signal of the guard band index area following the marker area. The marker detection circuit 104 receives the marker search signal E1 and enters into an operating state. On the other hand, the guard band index detection circuit 105 also receives the guard band search signal E3 to enter the guard band detection state and receives the index search signal E4 to enter the index detection state.

The marker detection circuit 104 generates a marker detection signal E2. The guard band index detection circuit 105 generates a first outer guard band detection signal OGB1, a second outer guard band detection signal OGB2, and an index signal INDEX.

The PLL counter 106 counts the number of clocks of the PLL circuit 102 from the time point at which the marker detection signal E2 is obtained from the marker detection circuit 104. Therefore, the value of the PLL counter 106 provides a coefficient value indicating the information recording position in the guard band index portion and the servo pattern portion thereafter based on the marker detection time.

On the other hand, the output of the servo head 18 is given to the zero cross detection signal 112 which functions as part of the read pulse detection section via the selection circuit 116. In the present invention, the zero cross detection is performed instead of the peak detection of the read signal of the phase servo provided at the end of the servo frame. This is because the peak detection of the read signal of the phase servo information is weak in noise and jitter easily occurs. Explain in more detail why. The phase servo information recorded on the servo plane is a pattern in which the phase shift is, for example, 0.5 cylinder. The read signal by the servo head is affected by an adjacent servo zone, and the amplitude of the signal is reduced or the peak portion is blunted. 14A shows the read signal 1160 of the phase servo pattern of the Mokpo cylinder, the pattern read signal 1170 of the adjacent cylinder shifted by +0.5 cylinder, and the pattern read signal 1180 of the adjacent cylinder shifted by -0.5 cylinder. In fact, the read signal obtained from the servo head becomes the read signal 1200 of Fig. 14B which combines these three signals. Therefore, the read signal 1200 is differentiated as shown in FIG. 14C to detect the peak from the zero cross point of the differential signal 1210. However, as the enlarged waveform portion 1220 is shown, waveform distortion at which the slope of the waveform is blunted at zero cross point 1230 causes a phase jitter. As a result, there exists a problem that the positioning accuracy of a head falls. In the present invention, zero cross detection is performed on the phase servo read signal instead of peak detection, so that even if noise is mixed, the read signal of the phase servo can be reliably detected.

15 shows one embodiment of the zero cross detection circuit 112. As shown in FIG. The zero cross detection circuit 112 has an operational amplifier 1150 and is pre-staged through the capacitors 1110 and 1120 to the non-inverting input terminal (plus input terminal) and the inverting input terminal (negative input terminal) of the operational amplifier 1150, respectively. The read signal EO1 from the LPF 1010 is received by AC coupling. A constant reference voltage Vref is applied as a bias voltage through the resistors 1130 and 1140 to the input of the operational amplifier 1150 following the capacitors 1110 and 1120.

The operation of the zero cross detection circuit 112 will be described next. The read signal in FIG. 16A is a signal before passing through the LPF 1010 and causes waveform distortion in which the zero cross point is blunted. When the read signal passes through the LPF 1010, as shown in FIG. 16B, the rising speed of the zero cross can be increased. The read signal EO1 is supplied as a differential signal of two signal lines. When the read signal EO1 supplied to the operational amplifier 1150 by the AC coupling of the capacitors 1110 and 1120 is a midpoint voltage set to the reference voltage Vref, the non-inverting input terminal (plus) side becomes the signal waveform of FIG. 16b. . On the other hand, the inverting input terminal (negative) becomes the inverting input signal of FIG. 16C. As a result, the operational amplifier 1150 operates as a comparator for comparing the non-inverting input signal with the inverting input signal inverting the non-inverting input signal. As a result, a 16d-degree zero cross detection purse E16, which is a logic level 1, is generated over a period of half cycle in which the non-inverting input signal exceeds the inverting input signal. The zero cross detection circuit of FIG. 15 has the same structure as the zero cross detection circuit 1050 used for the peak detection circuit of FIG.

In the zero cross detection of the read signal of the phase servo information, the zero cross timing between the positive read waveform of the N pole and the negative read waveform of the S pole in the read signal of Fig. 11C is detected. Therefore, in peak detection of the read waveform, the detection timing of zero cross detection necessarily has a phase delay with respect to the detection timing of peak detection of the read waveform. That is, synchronous control by peak detection is performed on the reference clock by the PLL circuit 102, and a read pulse by reading the phase servo is also required to synchronize with the clock of the PLL circuit 102. However, zero crossing inevitably leads to phase delay with respect to the reference clock.

The phase delay by the zero cross detection enables the creation of a duty pulse having a duty ratio of 50% in which the integral voltage becomes zero in the track state adjusted by the variable delay circuit 114 and the shifter 108. In this example, the shifter 108 divides the rising edge of the pulse signal obtained by dividing the reference clock of the PLL circuit 102, which is obtained as the second bit output of the PLL counter 106 into quarters, in the range of three stages of 0? Adjust delay digitally. On the other hand, the variable delay circuit 114 delays the rising timing of the zero cross detection circuit 112 analogously to the selective connection of the plurality of analog delay elements. Delay adjustment by the shifter 108 and the variable delay circuit 114 will be described in detail below.

The master clock preparation circuit 110 generates a master clock with a period 4π divided by a quarter of a reference clock having a phase determined in correspondence with the target cylinder and is generated as a master clock signal E10. The switching of the master clock having the phase corresponding to the target cylinder is executed by the cylinder switching signal E30 from the drive processor 30. In the on-track control, the master clock of the phase corresponding to the target cylinder in which the head is currently located is selected by the cylinder switching by the cylinder switching signal E30. In search control, on the other hand, the actual speed obtained from the previous head position and the current head position, and also the acceleration are applied, and the master clock of a phase corresponding to the target cylinder at the next predicted position is selected.

The duty pulse generator circuit 120 is a set / reset circuit and is set in the rising section (reference phase) of the master clock signal E10 corresponding to the target cylinder from the master clock generator circuit 110 and through the selection circuit 118. It is reset in the falling section (detection phase) of the obtained zero-cross detection pulse. The duty pulse generation circuit 120 performs the first field EVEN1, the second field ODD1, the third field ODD2, and the fourth field EVEN2 of the phase servo pattern in the on-track state of the servo head 18. A duty pulse E19 is generated in which the duty ratio is 50%, 50%, 50%, 50%.

Duty pulse E19 from duty pulse generation circuit 120 is given to integrating circuit 124. The integrating circuit 124 basically consists of a condenser 126 and four switch elements 128, 130, 132, 134 bridged to the condenser 126. The ON / OFF operation of the switch elements 132 and 134 below the capacitor 126 is controlled by the duty pulse E19. On the other hand, switching of the switch elements 128 and 130 on the upper side of the capacitor 126 is controlled according to the first to fourth fields of the phase servo pattern.

In this example, as shown in the polarity of the position signal taken out from both ends of the capacitor 126, when the right side is positive and the left side is negative, switching of the switch elements 128, 130, 132, and 134 in the first to fourth fields is performed. The integral operation by is as follows. First, in the first and fourth fields EVEN1 and EVEN2, the switch element 128 on the upper side of the capacitor 126 is turned on and the switch element 130 is turned off. The switch element 130 is turned on and off by the duty pulse E19 in this state. As a result, the capacitor 126 is charged through a path indicated by a solid line so that the position signal seen from the voltage at both ends of the capacitor 126 increases to the negative side. On the other hand, in the second and third fields ODD1 and ODD2, the switch element 130 on the upper side of the capacitor 126 is turned on and the switch element 9328 is turned off so that the switch element 132 is turned on by the duty pulse E19 in this state. Is off. Therefore, the capacitor 126 is charged through the path indicated by the broken line so that the position signal increases to the positive side at the polarity shown.

The duty pulse E19 created in the on-track state of the target cylinder is 50% duty ratio in all fields, and the number of pulses in each field is the same. Therefore, the integral voltage of the capacitor 126 becomes zero when the integration operation of the four field duty pulses is finished. When the servo head is shifted from the on-track state to the target cylinder, the duty ratio deviates from 50%, and a voltage according to the change of the duty ratio is obtained in the capacitor 126.

Specifically, when the servo head 18 moves in the negative direction, that is, outward with respect to the target cylinder, the duty ratios of the first and fourth fields EVEN1 and EVEN2 decrease, and conversely, the second and third fields ODD1 and ODD2. ) Will increase the duty ratio. On the other hand, when the servo head 18 moves in the positive direction, that is, inward with respect to the target cylinder, the duty ratio of the first and fourth fields EVEN1 and EVEN2 increases, and the duty of the second and third fields ODD1 and ODD2 is increased. The rain is reduced.

The switching control for each field of the switch elements 128 and 130 on the upper side of the condenser 126 in the integrating circuit 124 is performed by the output signals E5, E6, E7, and E8 from the coincidence detection circuit 122. . The coincidence detection circuit 122 determines the coincidence between the count value of the PLL counter 106 and a predetermined predetermined value, and generates a signal corresponding to each coincidence position. In other words, the demodulation mode in which the first to fourth fields are displayed by the demodulation mode generating unit 122-1 in addition to the respective search signals E1, E3, and E4 for the marker detection circuit 104 and the guard band index detection circuit 105. Generate signal E5. The half mode generator 122-2 generates a half mode signal E6 indicating the point of time when the position signal detection, which is the boundary between the second and third fields, is displayed. The data window generator 122-3 generates a data window signal E7 for validating the duty pulse for the integrating circuit 124 in the first to fourth field periods.

The discharge control unit 122-4 also generates a discharge control signal E8 for discharging the capacitor 126 at a timing other than the duty pulse generation period over the first to fourth fields. The discharge reset by this discharge control signal E8 turns off the switch elements 128 and 130 provided in the integrating circuit 124 and turns on the switch elements 133 and 134.

The position signal E40 obtained as the voltage between both ends of the condenser 126 of the integrating circuit 124 is transmitted to the drive processor 30 by an interrupt signal E9 obtained at the end timing of the servo frame by the A / D converter 38. It is fetched.

On the other hand, in the present invention, the phase servo pattern is written in the inner guard band region IGB1 and the outer guard band region OGB1 of the data plane. In order to enable detection of the head position by the phase servo pattern of the data plane, the zero cross detection circuit 112 receives the read signal of the read head 410 provided in the data head 20 through the selection circuit 116. Supply to. The selection circuit 116 is switched by the control signal E31 from the drive processor 30. That is, in the servo control normally, the selection circuit 116 is switched to the servo head 18 side. On the other hand, when reading the phase servo pattern of the data plane, the data head 20 is switched in units of a predetermined number of servo frames during one rotation of the cylinder. That is, the phase servo information of the data surface is read out while switching to the data head 20 discretely on-track by the phase servo information of the servo surface, and for example, temperature offset measurement and yaw offset offset measurement are performed.

In addition, in the present invention, since the servo device writes the phase servo pattern on the data plane after the phase servo information is written on the servo plane, the write signal for writing is transferred to the master clock creation circuit 110. The servo information is written and supplied to the write head 400 of the data head 20 to write the servo information on the data surface.

In addition, a selection circuit 118 is provided to generate a duty pulse having an arbitrary duty ratio simulated by the duty pulse generator circuit 120 to obtain a position signal to the integrator circuit 124. The selection circuit 118 switches the simulated read pulse from the drive processor 30 and the zero cross detection pulse obtained by the zero cross detection circuit 112 by the control signal E32. The creation of the duty pulse by the generation of the simulated read pulse by the drive processor 30 is based on the duty ratio of the actual duty pulse used to adjust the 50% duty performed by the shifter 108 and the variable delay circuit 114. Used for measurement.

[Servo Frame]

17 shows the servo information of the cylinder recorded on the servo surface of the disk apparatus of the present invention on a straight line. The servo region 154 for one revolution of the disk is divided into, for example, 216 sections to form 216 servo frames. In this example, the number of clocks in the servo area 154 for one disc is fixed. One servo frame 156 is composed of a training section 158, a marker section 160, a guard band index section 162, and a servo pattern section 164, as shown in an enlarged manner. If the start position of the servo frame 156 is 0, each area has the following count value as a count value of the 20 MHz reference clock. That is, the training unit 158 has 0 to 1128, the marker unit 160 to 1128 to 1160, the guard band index number unit 162 to 1160 to 1268, and the servo pattern unit to have a coefficient value of 1268 to 1512, respectively.

18A, 18B, 19, and 21 are views of the training unit 158, the marker unit 160, the guard band index unit 162, and the servo pattern unit 164 provided in the servo frame 156. Indicates the magnetic recording state. In this example, for the training section 158 of FIG. 18A, the marker section 160 of FIG. 18B, and the guardband index section 162 of FIG. 19, the reference clock 166 is represented by a scale of 4τ, which is a four clock period. have. On the other hand, the servo pattern section 164 of FIG. 20 and FIG. 21 shows the reference clock 166 on the scale of 1 (tau) which becomes one clock period.

The training section 158 of FIG. 18A records timing signals for synchronizing the phase of the PLL circuit 102 of FIG. By reading the timing signal of this training section 158 and obtaining the peak detection pulse at 4 ?, the PLL circuit 102 can perform synchronous oscillation of 1? = 50 nsec, i.e., 20 MHz, synchronized with the actual disk rotation.

18B illustrates the marker unit 160 following the training unit 158. The marker unit 160 plays a role of determining the position in the servo frame and starts counting operation of the PLL counter 106 installed in FIG. 10 by the marker detection of FIG. 10, by the coincidence detection circuit 122. Various coincidence determinations are made. Although the read signals I and HHHHLHLHLH are obtained from the marker unit 160, marker detection is performed by coincidence detection of 6 bits of I, □ HH □ L □ L □ L □ as shown in these read signals. .

19 shows the guard band index portion 162. FIG.

According to the present invention, the guard band index unit 162 is divided into three areas of the first majority unit 174, the second majority unit 176, and the third multiple unit 178, and the same signal is repeatedly recorded in each region. have. When two or more matching information is obtained from the first to third multiplexing units 174, 176, and 178 obtained from the read signal of the guard band index unit 162, the guard band index detection circuit 105 of FIG. The detection performance of the guard band and the index is improved by determining that the detection is performed. The servo surface is radially inward from the inner circumferential guard band region (IGB1) 180, a user region 182, a first outer circumferential guard band region (OGB1) 184, and a second outer circumferential guard region (OGB2) 186. Divided by. The index information 188, 190, 192 is recorded in the inner guard band region 180, the user region 182, and the first and second outer guard band regions 184, 186.

20 and 21 show details of the servo pattern portion 164 recording the phase servo pattern. The servo pattern unit 164 is composed of a first field 200 shown in FIG. 20, a second field 202, a third field 204 shown in FIG. 21, and a fourth field 206. As shown in FIG. In the following drawings, as shown by (), the first field 200 is (EVEN1), the second field 202 is (ODD1), the third field 204 is (ODD2), and the fourth field 206. Is set to (EVEN2).

The length of each region of the first to fourth fields has the same length except for the unused portions 194, 196, 208, and 201. Specifically, when 4τ for four cycles of the reference clock is referred to as a reference length, each field has a length of (4τ × 10). The first and fourth fields 200 and 206, which become (EVEN1) and (EVEN2), write the pattern of shifting the phase of 1? Phase in 8? Periods every time the head is moved by 0.5 cylinder in the increase direction (inner direction) of the plus side of the cylinder number. . On the other hand, the second and third fields 202 and 204 which become (ODD1) and (ODD2) are written so as to perform reverse phase shift. Each phase servo pattern is repeated every four cylinders.

[Write of phase servo pattern]

The phase servo patterns shown in Figs. 20 and 21 are written using a dedicated servo writer. Since the disk apparatus of the present invention has a function of writing a phase servo pattern on the data plane after writing the phase servo pattern on the servo plane, the phase servo pattern on the servo plane is assumed as a premise of the phase servo pattern on the data plane. The writing principle is explained next.

FIG. 22A shows a reference clock, which is the same as the clock by the PLL circuit 102 of FIG. 22B is bit 2 output when the clock from the PLL circuit 102 is counted by the PLL counter 106, and this output is a pulse signal divided into quarters of the PLL clock. This pulse signal becomes the write signal of phase 0 position. 22A to 22I are signals obtained by sequentially phase shifting the write signal of phase number 0 by 1? Of clock period, and become the write signals of phase numbers 2, 4, 6, 8, 10, 12, and 14. For the writing of the servo pattern on the servo plane, a combination of eight write signals having an excellent phase number in FIGS. 22B to 22I is used.

23A to 23I are write signals having the odd phase numbers 1, 3, 5, 7, 9, 11, 13, and 15, which are needed more when the disk device of the present invention writes the phase servo pattern on the data plane. Indicates. That is, the clock shown in Fig. 23A is a clock inverting the PLL clock of Fig. 22A, and the timing of falling of the clock before inversion is set as the rising timing. By performing the phase shift of the bit 2 output of the PLL counter 106 of FIG. 23b by 1? Using the inverted PLL clock of FIG. 23a, a write signal having the odd phase number of FIGS. 23c to 23i can be obtained. In the following description, the hexadecimal representation of A, B, C, D, E, and F is given for phase numbers 10, 11, 12, 13, 14, and 15.

FIG. 24 shows a circuit for creating the write signals of phase numbers 0 to 16 in FIGS. 22A to 22I and FIGS. 23B to 23i. This circuit is realized as the master clock circuit 110. The PLL clock is supplied to the shift circuit 500 as a shift pulse. On the other hand, the inversion PLL clock inverted by the inversion circuit 520 is supplied to the shift circuit 510 as a shift clock. Each of the shift circuits 500 and 510 is supplied with the bit 2 output of the PLL counter 106. The shift circuit 500 sequentially generates eight types of write signals, each of which is a phase number 0, 2, 4, 6, 8, A, C, and E, in synchronization with the PLL clock. On the other hand, the shift circuit 510 sequentially generates a write signal of an odd phase number of which the phase numbers 1, 3, 5, 7, 9, B, D, and F have a delay of 0.5τ with respect to the shift circuit 500. do. The multiplexer 530 selects any one of 16 types of write signals generated with a phase shift of 0 and 5? With respect to the shift circuits 500 and 510.

FIG. 25 shows the write signal phase numbers when the phase servo patterns of FIGS. 22A to 22I and 23B to 23I are written while searching for the servo head by 0.5 cylinders. In the present invention, the same phase number combination is repeatedly used in four cylinder units. Such a servo pattern on the servo surface is not executed by the disk device itself, but the disk device itself writes the phase servo pattern on the data surface. That is, the phase servo information written by the servo head can be read and the position of the servo head can be determined, but the disk device itself can write the phase servo pattern on the data surface.

FIG. 26 shows a phase number for master clock selection used for switching the master clock corresponding to the Mokpo cylinder at the time of reading the phase servo pattern written on the servo surface according to FIG. The writing of the phase servo pattern is repeated in units of 0.5 cylinders and in units of 1 cylinder for the master clock corresponding to the target cylinder. Therefore, if the cylinder number from the inner side to the outer side is 0 to 3, a master clock corresponding to the cylinder numbers 0 to 3 serving as the target cylinders and different from the pattern of the corresponding phase number is created by the master clock creation circuit 110. Specifically, the circuit shown in FIG. 24 is provided in the master clock preparation circuit 110, and the drive processor 30 sends the selection signal of the phase number corresponding to the cylinder number of the target cylinder at that time to the pattern of FIG. Therefore, the multiplexer 530 may be selected for each of the first and fourth fields. In this way, when detecting the position by reading the phase servo information on the servo surface, four types of phase numbers 0, 4, 8, and 12 are used among the 16 types of master clock signals shown in FIGS. 22A to 22i and 23B to 23i. The combination of is used.

[Position Detection by Reading Phase Servo Pattern]

Each signal generated from the position detection circuit 122 in FIG. 10 when the phase servo pattern of the servo surface is read by the disk apparatus of the present invention will be described next. When the synchronization of the PLL circuit 102 by the timing signal read out from the first training region by the reading of the servo frame is completed, the marker detection signal E2 in FIG. 27B is generated from the marker detection arc 104 by the detection of the marker region. By this marker detection signal, as shown in Fig. 27C, the PLL counter 106 is put into an operating state, and the count of the clock signal E0 from the PLL circuit 102 is started. In this example, the period from the marker detection signal to the reading of the position signal at the end of the frame is set to 180H in the hexadecimal count value of the PLL counter 106. Therefore, the counter operation is performed for a period until the hexadecimal count value 180H is obtained. The marker search signal E1 in FIG. 27A, which validates the detection operation of the marker detection circuit 104, also occurs during the same period.

The guardband index detection signal E3 in FIG. 27d is then obtained in hexadecimal count values over a period of 0 to BOH. The guard band index search signal E4 in FIG. 27E, which is currently valid, rises to prohibit the detection operation of the guard band index detection circuit 105. The hexadecimal count value where the guard band index search signal E4 rises to the H level is a period of BOH to 148H, which becomes the reading period of the servo pattern unit 164. During the readout period of the servo pattern section 164, the coincidence detection circuit 122 demodulates FIG. 27f for converting the first field EVEN1, the second and third fields ODD1, ODD2, and the fourth field EVEN2. Generates the mode signal E5. As a result, the integrating circuit 124 selectively turns on and off the switch elements 128 and 130 on the upper side of the capacitor 126 in each field period. In addition, the integrating circuit 124 generates a half-mode signal E6 giving a position detection point which is an intermediate point of the servo pattern portion 164 of FIG. 27G.

An interrupt signal E9 of FIG. 27H is generated between the time when the servo pattern section 164 ends and the next training section 158. At this timing, the drive processor 30 draws out a position signal determined by the voltages of both ends of the capacitor 126 of the integrating circuit 124 converted to the A / D converter 38. As shown in FIG. 27I, the discharge control signal E8 becomes effective during the period other than the generation period of the servo pattern section 164 and the interrupt signal E9 to reset the capacitor 126 of the integrating circuit 124. State, that is, zero voltage state.

In the disk apparatus of the present invention, the change of the phase servo pattern based on the zero-cross detection, the duty cycle of the servo plane, the master clock, and the read pulse, and the terminal voltage of the capacitor 126 of the integrating circuit 124 based on the duty pulse The change of is described next. In FIG. 28A, the servo pattern of the servo surface is repeated every four cylinders of cylinder numbers 0-3. It is now assumed that the servo head 18 is located on the track at the center cylinder 2, and in this state, the master clock having the reference phase advanced by 4? Relative to the phase servo pattern recorded in the cylinder number 2 is selected. Therefore, the duty pulse E19 in FIG. 28B is set to the rising interval of the reference clock in FIG. 28A every 4? And is reset by reading the phase servo pattern by the servo head 18. FIG. Since the head is in an on-track state, the duty ratio is 50% in any of the first to fourth fields EVEN1, ODD1, ODD2, and EVEN2. In this state of 50% duty ratio, the terminal voltage of the condenser 126 of the integrating circuit 124 is set as shown in 28E. First, the capacitor 126 is charged in the negative direction in the first field EVEN1. Subsequently, the second field ODD1 is charged in the positive direction. When the terminal voltage passes through OV, the capacitor 126 is charged in the positive direction in the third field (ODD2). Finally, the fourth field EVEN2 is charged in the negative direction similarly to the first field EVEN1. The capacitor voltage becomes a zero voltage indicating an on track when the reading of the phase servo pattern is completed.

When the servo head seeks in the negative direction and tracks on cylinder number 1 or 0, the duty pulse E19 with a 50% duty ratio is similarly selected by selecting the master clock on the reference phase with a high 4? Phase for the phase servo pattern of each track. Obtained. This point also applies to the case where the servo head 18 is searched for the cylinder number 3 in the positive direction. Therefore, it is possible to create a head position signal that changes linearly in correspondence with the head position at the position of ± 2 cylinders relative to the on-track cylinder position.

[Measurement of duty ratio and delay adjustment]

FIG. 29 shows one embodiment of the integrating circuit 124 of FIG. The integration circuit 124 operates with the first power supply + Vdd1 and the second power supply + Vdd2. In the present embodiment, the first power source + Vdd1 to the second power source + Vdd2 are created by a circuit consisting of a resistor R20, a transistor Q1, a constant current source 138, and a transistor Q2. In this example, transistors Q1 and Q2 act as diodes for ensuring the voltage between the base and emitter. If the constant current of the constant current source 138 is i, and the voltage between the base and emitters by the transistors Q1 and Q2 is V _BE , the second power supply voltage Vdd2 is given by the following equation.

Vdd2 = Vdd1-{(R20 × i) + V _BE }

That is, the second power supply voltage Vdd2 is obtained by subtracting the voltage drop of the resistor R20 caused by the constant current i from the first power supply voltage Vdd1 and the voltage V _BE between the base and the emitter. The eight transistors Q3, Q4, Q5, Q6, Q7, Q8, Q9 and Q10, acting as current switches, are connected in parallel to these supply voltages via resistors R1, R2, R4, R5, R6, R7, R9, R10. . Among these transistors Q3 to Q10, transistors Q3 and Q4, Q5, Q6, Q7 and Q8, Q9 and Q10 form a differential circuit. The constant current sources 140, 142, 144, 146 are connected to the common emitter side of these differential circuits. The control signals E20, E21, E22 and E23 are supplied to the transistors Q3, Q6, Q7 and Q10 of the differential circuit from the integral control circuit section shown in FIG. That is, the control signal E20 controls the transistor Q3, the control signal E21 controls the transistor Q7, the control signal E22 controls the transistor Q6, and the control signal E23 controls the transistor Q10. In this manner, each of the transistors Q4, Q8, Q5, and Q10 differentially connected to the transistors Q3, Q7, Q6, and Q10 controlled by the control signals E20, E21, E22, and E23 performs reverse ON / OFF operation. Transistors Q11 and Q12 are connected to each of transistors Q6 and Q7, and a capacitor 126 is connected therebetween.

For this reason, the bridge type switching circuit shown in the integrating circuit 124 of FIG. 10 is constituted by transistors Q11, Q12, Q6 and Q7. Servo transistors Q3 and Q4 and Q9 and Q10 for controlling transistors Q1 and Q2 located above the capacitor 126 are provided in the demodulation mode generating unit 122 provided in the coincidence detection circuit 122 shown in FIG. The demodulation mode signal E5 from -1) is controlled according to the first to fourth field periods. Therefore, the control signal E20 for the transistor Q3 and the control signal E23 for the transistor Q10 are created from the demodulation mode signal. On the other hand, the ON / OFF operation of the two transistors Q6 and Q7 located below the capacitor 126 is controlled by the control signals E21 and E23 based on the duty pulse E19 from the duty pulse generation circuit 120 shown in FIG. do. That is, in the first and fourth fields, the control signal E21 changes according to the duty pulse and the constant current follows the path of the transistor Q11, the capacitor 126, the transistor Q7, and the constant current source 144 by the ON / OFF operation of the transistor Q7. The capacitor 126 is charged. On the other hand, in the second and third fields, the control signal E22 is changed by the duty pulse to turn on or off the transistor Q6, and supply a constant current through the path of the transistor Q12, the capacitor 126, the transistor Q6, and the constant current source 142. The capacitor 126 is charged.

The terminal voltage of the capacitor 126 is supplied to the differential amplifier 152 through operational amplifiers 148 and 150, which operate as voltage followers, and resistors R1 and R2. The gain of the differential amplifier 152 is determined by the center voltage Vc supplied from the drive processor 30 via a feedback resistor R33 and a resistor R34. In addition, a reference voltage Vref is provided to each base of the transistors Q4, Q5, Q8, and Q9 to set a reference voltage as an intermediate junction that gives a relative charging voltage from the power supply voltage. Therefore, the terminal voltage of the capacitor 126 is charged and discharged to the positive side or the negative side around the reference voltage Vref.

An integration operation based on the control signals E20, E21, E22, and E23 supplied in the don track state of the servo head of the integration circuit 124 in FIG. 29 will be described next. A phase servo pattern of four cylinders is simplified and shown in FIG. 30A. In response to the read of the phase servo pattern, the control signal E20 in Fig. 30B becomes H level in each of the first and fourth fields EVEN1 and EVEN2, turning on the transistor Q3 and turning off the transistor Q4, thereby turning on the transistor Q11. The control signal E23 in FIG. 30C becomes H level in the second and third fields ODD1 and ODD2 to turn on the transistor Q10 and turn off the transistor Q9 to turn on the transistor Q12. 30A shows an on track state in which the servo head 18 is located on cylinder number 2. FIG. The clock pulse of FIG. 30d is selected as the master clock and the read pulse of FIG. 30e is obtained. Therefore, duty pulse E19 in FIG. 30f becomes a 50% duty bar in any of the first to fourth fields. With respect to such a control signal E21, the control signal E21 of FIG. 30g changes in response to the duty pulse E19 in the first and fourth fields EVEN1 and EVEN2 and turns the transistor Q7 ON or OFF via the transistor Q11 in the ON state at this time. The integration operation is performed by supplying a constant current from the constant current source 144 to the capacitor 126.

On the other hand, the control signal E2 in FIG. 30h is changed in accordance with the duty pulse E19 in the second and third fields ODD1 and ODD2 and is turned on or off by the transistor Q6 to the constant current source 142 via the transistor Q12 in the ON state at this time. Integral operation is performed by supplying the condenser 126 determined in the reverse direction. The data window signal E7 shown in FIG. 30i is used for the actual integration operation. The charging operation in one direction and the reverse direction of the capacitor 126 is performed by the control signals E21 and E22 during the period in which the data window signal E7 is at the H level. At this time, since the servo head 18 is in the on-track state at cylinder number 2, the voltage across the capacitor when the integration operation of the first to fourth fields is completed is OV.

[Difference of Duty Ratio in On Track State]

The duty ratio of the duty pulse generated based on the reading of the phase servo pattern operating the integrating circuit 124 of FIG. 29 is ideally 50% in the on-track state. However, as shown in the embodiment of FIG. 10, the synchronization of the PLL circuit 102 is performed by peak detection of the read signal, while the phase servo pattern is detected by zero cross detection. Therefore, the timing of the cross detection is inevitably unable to obtain a duty pulse having a duty ratio of 50% in the track state shifted from the timing of the reference phase.

The difference between the duty ratios in the case of peak detection of the reading of the phase servo pattern and in the case of zero cloth detection as in the present invention will be described next. As shown in FIG. 31A, if the servo head 18 is located on the track of the cylinder of cylinder number 2 in the four cylinders, the set in the duty pulse creation circuit 120 is selected by selecting the master clock which becomes the reference phase in FIG. 31B. Timing is obtained. In the case of peak detection, as shown in FIG. 31C, a peak detection timing that matches the magnetic write timing of the servo pattern is obtained. In this case, the duty pulse is 50% in the duty ratio in each of the first to fourth fields as shown in FIG. 31D.

However, in the zero cross detection of the present invention, as shown in FIG. 31E, the zero cross detection timing has a delay time with respect to the peak detection timing. As a result, the duty ratio of the duty pulse becomes 75% in the on-track state as shown in FIG. 31f. The reason why the duty ratio does not become 50% in the on-track state is that it is caused randomly by a circuit delay in the analog circuit system in addition to the zero cross detection, and each disk device has various duty ratios that deviate from 50% in the on-track state.

Therefore, in the disk apparatus of the present invention, the duty ratio of the duty pulse obtained in the on-track state is first measured. In order to set the measured duty ratio to 50%, the delay amount of the shifter 108 and the variable delay circuit 114 shown in FIG. To produce.

FIG. 32 shows one embodiment of the integral control section that forms part of the integral circuit 124 of FIG. 29 with the function for measuring the actual duty ratio of duty pulse E19 obtained in the on-track state. This integrating control unit is provided with an inverting circuit 312, AND circuits 314, 322, 324, OR circuits 318, 320, 326, 328, and an exclusive OR circuit (EOR) 316 for measuring the duty ratio. . In this circuit, the duty signal obtained by inverting the pulses of the second and third fields ODD1 and ODD2 of the duty pulse E19 output from the duty pulse generator circuit 120 is obtained based on the ODD region inversion signal E20 from the drive processor 30. . Circuit portions excluding the inversion circuit portion of this ODD region are shown in Figs. 30B, 30C, and 30G by using the demodulation mode signal E5, the data window signal E7, and the discharge control signal E8 from the coincidence detection circuit 122 located at the front end. And control signals E20, E23, E21 and E22 in FIG. 30h.

The integral operation of the duty pulse and the condenser when the ODD area inversion signal E20 from the drive processor 30 is disabled and enabled is as follows. 33A shows the duty pulse E19 obtained in the non-measured state of the duty ratio and shows, for example, a pulse train exceeding 50% of the duty ratio during the first to fourth fields. 33B shows the change of the integral voltage due to the duty pulse E19 at the time of not measuring the duty ratio, that is, the voltage across the capacitor 126. Even if the duty ratio is shifted from 50%, there is basically no problem for position control at the time when the final integrated voltage becomes zero voltage. However, it should be possible to detect the position when the position signal changes within the range of ± 2 cylinders. Therefore, if the duty ratio on track is 75%, the duty ratio varies from -50% to + 50% in the range of two cylinders. Therefore, the change in duty pulse is in the range of + 25% to + 125%. If the duty ratio exceeds + 125% and 100%, position detection becomes impossible. On the other hand, if the duty ratio is lower than 50%, for example 25%, the duty ratio in the range of 4 cylinders is likewise varied in the range of -50% to + 50%. The duty ratio of the resulting duty pulse is in the range of -25% to + 75%. If the duty ratio reaches a negative value, position detection is disabled. For this reason, it is necessary to keep the duty ratio of the duty pulse at 50% on track.

33C shows an output signal E24 generated from the EOR circuit 316 when the ODD area inversion signal E20 from the drive processor 30 is enabled for the discharge control unit of FIG. 30 and a capacitor based on the output signal E24 ( 126) is an integral voltage. In this case, duty pulse E19 in FIG. 33A is inverted during the periods of the second and third fields ODD1 and ODD2. As the integral voltage finally obtained, the duty ratio measurement voltage changed to the negative side by the increase of the duty ratio by 50% with respect to the zero voltage of the duty ratio 50% can be obtained. 33C and 33D show examples of cases where the duty ratio is increased. If the duty ratio is less than 50%, the final measured voltage is the positive voltage. By such a measurement voltage, the drive processor 30 can actually measure the duty ratio of the duty pulse E19 generated from the duty pulse generator circuit 120.

34 shows one embodiment of the shifter 108 of FIG. The shifter 108 is composed of D-type flip-flops (D-FF) 300, 302, 304 and a selection circuit 306. The three D-FFs 300, 302 and 304 constitute a shift resistor by series connection. In the first stage D-FF, a bit 1 output from the PLL counter 106 provided at the front end, that is, a divided pulse obtained by dividing the PLL clock EO of 20 MHZ in half is input. The PLL clock EO is supplied to the D-FFs 300, 302, and 304 as a shift clock. When the oscillation frequency is 20 MHZ, the clock cycle 1τ of this PLL clock EO is 50 nsec. The output signals E12, E13 and E15 of the D-FFs 300, 302 and 304 constituting the bit 1 output and the shift resistance of the PLL counter are input to the selection circuit 306. The bit 1 output of the PLL counter is shown as signal E15. The selection circuit 306 receives the selection signal E11 for delay control determined based on the measurement result of the drive processor 30, selects one of the inputs, and outputs one of the inputs to the master clock generation circuit 110 as a reference clock. .

The delay adjustment by the shifter 108 will be described next. 35a shows the PLL clock EO. In the case of 20 MHZ, 1? Is 50 nsec. The bit 1 output of the PLL counter in Fig. 35B is a pulse obtained by dividing the PLL clock EO in half. As indicated by signal E15 in FIG. 35f, this bit 1 output is directly given to the selection circuit 306, in which case the delay amount is 0 nsec. 35C shows the output signal E12 of the D-FF 300. The output signal E12 is a signal delayed by only 1 n minutes, i.e., 50 nsec, of the PLL clock EO. 35d shows the output signal E13 of the D-FF 302 of the 2nd stage. This output signal E13 is a signal delayed by only 100 nsec. 35E shows the output signal E14 of the D-FF 304 in the third stage. This output signal E14 becomes a 150 nsec delayed signal. In this way, the shifter 108 of FIG. 32 gives the PLL clock EO a digital delay amount of 0, 50, 100, or 150 nesec. Here, the delay amount digitally set by the shifter 108 is referred to as tau d1. FIG. 36 shows one embodiment of the variable delay circuit 114 of FIG. The variable delay circuit 114 is composed of eight delay elements 308-1 to 308-8 and eight selection circuits 310-1 to 310-8. Direct connection from the front end of the delay elements 308-1 to 308-8 to the input terminal of the selection circuits 310-1 to 310-8 and two paths via the delay elements 308-1 to 308-8. Connect the inputs respectively. Therefore, by selecting one of the two inputs as the selection circuits 310-1 to 310-8, the number of delay elements necessary for the output terminal from the input terminal can be connected in series. Each of the selection circuits 310-1 to 310-8 is controlled by the selection signal E17 from the drive processor 30. As the delay elements 308-1 to 308-8, for example, a delay element having a delay time of 12 nsec is used for the delay elements 308-1 to 308-6, and a delay time is used for the delay elements 308-7 and 308-8. A delay element of 5 nsec is used.

The selection signal E17 from the drive processor 30 is composed of 8-bit signals b7 to b0 corresponding to the delay elements 308-1 to 308-8. These bit signals b0 to b7 are sequentially input in order of the selection circuits 310-1 to 310-8. When each bit of the bit signals b0 to b7 is H (high) level (bit 1), the selection circuits 310-1 to 310-8 are lines from the delay elements 308-1 to 308-8. Select. On the other hand, when the bit signals b0 to b7 are L (low) level (bit 0), the line bypassing the delay elements 308-1 to 308-8 is selected.

The relationship between the selection delay times for the bits b0 to b7 of the selection signal E17 from the drive processor 30 is as shown in the table of FIG. By the 8-bit selection signal E17, the drive processor 30 uses 256 types of delay times tau 0 to 255 of Table No. I = 0 to 255 in FIG. 39 designated by the table number 1 using 8-bit decimal representation. Can be set. Table number I = 0 is a delay time tau 0 = 0 nsec, and there is no delay amount. I = 255 delay time τ255 is 82nsec giving the maximum amount of delay. The delay times tau 0 to 255 are not arranged according to the magnitude relationship of the delay times. The selection of the optimum delay time is determined by repeating the setting of the delay time and the measurement of the duty ratio. Each delay time shown in FIG. 18 and FIG. 39 actually changes to some extent, and only the ideal design value is shown here to the last.

The delay operation of the variable delay circuit 114 in FIG. 34 will be described next. The variable delay circuit 114 delays the zero cross detection signal E16 obtained from the zero cross detection circuit 112. The zero cross detection signal E16 gives the reset pulse of the duty pulse in the duty pulse generator circuit 120 to delay the reset timing. That is, 37a shows the zero cross detection signal E16 input from the zero cross detection circuit 112. The arbitrary delay time tau d2 is set by the selection signal E17 from the drive processor 30. The delayed output signal E18 in FIG. 37B is obtained from the selection circuit 310-8 of the last stage.

The delay pulse adjusting operation of the duty pulses by the shifter 108 of FIG. 32 and the variable delay circuit 114 of FIG. 34 is performed in the following manner. 40A shows the rising timing of the PLL clock E10. The duty pulse before correction of FIG. 40B is 4? And the duty ratio is more than 50%. As shown in FIG. 40C, the duty ratio of this duty pulse is obtained as the integral voltage of the capacitor 126 by the integrating circuit 124 by inverting the second and third fields ODD1 and ODD2, and the drive delay amount is determined. For example, in the case of FIG. 40B, it is necessary to reduce the duty of Δτd over 4τ in order to achieve a 50% duty ratio. In this case, in order to realize the delay amount [Delta] τd requiring adjustment, the drive processor 30 determines the delay of the PLL clock E10 in units of 50 nsec with respect to the shifter 108 and the zero cross detection timing by the variable delay circuit 114. The delay amount tau d2 is determined.

That is, the values of the set delay amounts τd1 and τd2 are determined to satisfy the following equation.

τd-τd1 + τd2 = 100 nsec

40C shows the setting of tau d1-100 nsec for the shifter 108. 40E shows the delay setting of tau d2 of the zero cross detection timing for the variable delay circuit 114. FIG. Therefore, the duty pulse generating circuit 120 can obtain a corrected duty pulse corrected to a duty ratio of 50% in FIG. 40E.

The flowchart of FIG. 41 shows the duty adjustment process by the drive processor 30. As shown in FIG. First, in step S1, the duty ratio is measured by inverting the second and third fields ODD1 and ODD2 in the on-track state in which the servo head 18 is placed in a suitable target cylinder. If the measured duty ratio is 50% in step S2, the process is terminated without performing the adjustment process. If the duty ratio does not match 50%, the calculation of the delay time tau d1 for reducing the duty ratio and the delay time tau d2 for increasing the duty ratio are performed in step S3 based on the measured duty ratio. The calculated delay time is set in the shifter 108 and the variable delay circuit 114 in steps S4 and S5, respectively, and returns to step S1 to measure the duty ratio. The above processes of steps S1 to S5 are repeated until 50% duty ratio is obtained in step S2. This duty ratio adjustment process is executed in the initialization process after power-on start, as shown in step S4 of the flowchart of FIG.

The flowchart in FIG. 24 shows as a subroutine the setting process of the delay time tau d2 for the variable delay circuit 114 executed in step S4 in FIG. This subroutine uses the table information of FIG. First, in step S1, the table selection number I of the table of FIG. 39, the table number Ds of the finally determined delay time, and the delay time Dm obtained in the previous calculation are initialized to zero. The decision delay time tau d2 for the variable delay circuit 114 determined by the duty measurement in step S2 is read as Do. The delay time Di is calculated from the combination of delay elements designated by the table selection number I = 0 initialized in step S3. In this embodiment, since the delay time is previously contained as the table information of FIG. 39, only the table search is required. If the table is not used, the delay time D1 is calculated from the combination of the delay elements designated by the table selection number I. The delay time D1 calculated in step S4 is checked whether it is larger than the previous calculation delay time Dm or less than the determination delay time Do read in step S2. YES in step S4 means that the calculation delay time Dm determined by the currently selected table selection number 1 is valid, and the flow advances to step S5. The delay time D1 currently calculated is set to the calculation delay time Dm, and the table number I is set to the determination delay time table number Ds. If NO in step S4, the processing in step S5 is not performed and the delay time of the table selection number is ignored. In step S6, the table selection number I is increased by one. The processing of steps S3 to S7 is repeated until the final table number I = 255 is reached in step S7. By repeating the processing in this manner, it is possible to determine the table number I which becomes the delay time closest to the determination delay time Do =? D2 read in step S2. The selection signal E17 based on the table number I determined in the last step S8 is output to the variable delay circuit 114 to set the delay time closest to the delay time tau d2. The selection signal E17 at this time is data representing the decimal value of the table number I shown in FIG. 39 in 8 bits. Delay element selection is unconditionally determined by bit correspondence.

[Adjustment of Integrating Circuit]

In the integrating circuit 124 of FIG. 29, the amount of current supplied to the capacitor 126 is determined by the constant current sources 142 and 144. However, variations occur in the manufacturing process in the resistors used in the constant current circuit for realizing the constant current sources 142 and 144 and the capacity of the capacitor 126. Therefore, on the basis of the duty pulse of 50% duty ratio in the on-track state, current should be supplied to the capacitor 126 from both directions, and ideally, the terminal voltage should be 0V. However, in practice, either side of the capacitor, which is easy to generate, generates voltage. The error voltage at the time of on-track of the condenser 126 is supplied to the drive processor 30 as an amount of deviation from the center of the cylinder in the position detection signal, and the position detection accuracy is lowered. Therefore, in the disk apparatus of the present invention, the error voltage of the condenser 126 at the duty ratio of 50% is measured by the function of the integrating circuit adjusting processor 86 provided in the drive processor 30, and A is controlled at the head position. The correction is performed by subtracting the error from the position signal drawn from the / D converter 38 and using the correct position data.

The measurement of the error voltage of the condenser 126 during such on-track operation outputs the control signal E32 to the selection circuit 118 by the drive processor 30 shown in FIG. 10 and the drive processor (118) to the selection circuit 118. Duty in the integrating circuit 124 by supplying a read pulse corresponding to the simulated zero cross detection pulse from 30) to the duty pulse generator circuit 120 and controlling the duty ratio of duty pulse E19 to the drive processor 30. Measure the error voltage when the ratio is 50%. Also, through the selection circuit 118, a duty pulse equivalent to the state of the head searched for the target cylinder by ± 1 cylinder length is generated, and the position signal is measured by the integrating circuit 124, and the position detection per cylinder is detected. Measure the cylinder gain to display the data. Therefore, the cylinder gain as position detection data indicating the capacitor error voltage of the integrating circuit 124 and the amount of head movement of one cylinder can be measured only by creating a simulated duty pulse without actually moving the servo head 18. .

Three types of read pulses output to the duty pulse generator circuit 120 by the drive processor 30 through the selection circuit 118 for the measurement of the integral error voltage and the cylinder gain will be described next. Fig. 43A shows the phase servo pattern of the servo surface. The servo head 18 is located on the track of cylinder number two. In this on-track state, the master clock of FIG. 43B is supplied to the duty pulse generator circuit 120. The duty pulse is set corresponding to the rising section of the master clock. The duty pulse is set corresponding to the rising section of the master clock. The duty pulse is reset to an on track read pulse from the drive processor 30 via the selection circuit 118. As shown in FIG. 43C, the on track read pulse is generated with a phase difference of approximately 4? In the rising section of the master clock. Thus, the integrating circuit 124 can be operated by simulating a duty pulse having a duty ratio of 50% in FIG. 43D.

FIG. 43F shows +1 search read pulses output from the drive processor 30 corresponding to one cylinder search in the plus direction of the servo head 18 on track in the cylinder number in FIG. 43A. This +1 search read pulse corresponds to the read pulse when the servo head 18 moves to cylinder number 3 in FIG. 43A and occurs with a phase delay of 6? With respect to the rising section of the master clock. This +1 search read pulse can simulate a duty pulse of 70% duty ratio in the first and fourth fields EVEN1 and EVEN2 in FIG. 43g and 25% duty ratio in the second and third fields ODD1 and ODD2. .

In addition, in FIG. 43H, a pulse corresponding to a read pulse obtained when the servo head 18 is searched for one cylinder in the negative direction from the on-track state and moves to cylinder number 1 is generated as -1 search read pulse to the drive processor 30. . The -1 search read pulse is shifted by 2? Phase shift with respect to the rising edge of the master clock in the first and fourth fields EVEN1 and EVEN2, and shifted by 6? Phase shift with respect to the reference clock in the second and third fields ODD1 and ODD2. Pulse. Thus, a duty pulse of 25% duty ratio in the first and fourth fields EVEN1 and EVEN2 shown in FIG. 431 and -75% duty ratio in the second and third fields ODD1 and ODD2 shown in FIG. It can occur synchronously.

FIG. 44A shows the ideal potential difference when the on-track read pulse of FIG. 43C is generated by the drive processor 30 to operate the integrating circuit 124 with a duty pulse of simulated duty ratio of 50%. This change in low order 330 is finally zero. However, in practice, when the integrating circuit 124 is operated with a duty pulse of 50% duty ratio based on the on-track read pulse, as shown in FIG. 44B, compared to the ideal characteristic 330 shown by a broken line due to a change in resistance or capacity, as shown in FIG. 44B. As shown by the characteristic 332 shown by the solid line, the potential difference of the capacitor 126 changes. Finally, the offset voltage DELTA V remains as an error voltage. The drive processor 30 draws and maintains this offset voltage DELTA V by the A / D converter 38. In subsequent head position control, the offset voltage DELTA A is removed from one data drawn from the A / D converter 38 to generate accurate position data.

45 shows the change in the potential difference of the capacitor 126 due to the generation of the +1 cylinder read pulse and the -1 cylinder read pulse to obtain the cylinder gain. The actual characteristic 334 is a change when simulated +1 cylinder search of the head. In this case, a potential difference of + V1 is obtained. The characteristic 336 indicated by the dotted line is the change in potential difference when the head is searched for -1 cylinder. In this case, a potential difference of -V2 is obtained.

The drive processor 30 obtains the change power of the potential difference + V1 when the head is searched for +1 cylinder and the potential difference -V2 when the head is searched for -1 cylinder as (V1 + V2). By dividing this change power by two cylinders, the change in the potential difference per cylinder, that is, the position signal, is obtained as the cylinder gain.

The flowchart of FIG. 46 shows the integral circuit correction processing by the drive processor 30. As shown in FIG. First, in step S1, the selection circuit 118 is switched to remove the servo head 18 so that the simulated read pulse from the drive processor 30 can be supplied to the duty pulse generation circuit 120. In step S2, the master clock of phase number 0 is selected by the cylinder switching signal E30 to generate it from the master clock creation circuit 110 as the master clock E10. In step S3, an on track read pulse that generates a duty pulse of 50% in all fields is generated to generate a simulated on track control state. Integral voltage is drawn out by the generation of the track read signal on in step S4, and the offset voltage [Delta] V is detected. After detection, the integrated voltage correction data is created in step S5 to be used for subsequent correction processing. The cylinder gain is measured by the processing of steps S6 to S11. First, in step S6, a read pulse for generating a duty pulse for +1 cylinder search for the head whose duty ratio changes from 75%, 25%, 25%, and 75% is generated to generate a simulated +1 cylinder search state, and step S7 At that time, the integrated voltage V1 is taken out. In step S8, a read pulse for generating a duty pulse whose duty ratio changes from 25%, 75%, 75%, and 25% is generated, which simulates the search state of -1 cylinder, and the integrated voltage V2 at that time in step S9. To draw. In step S10, the voltage change when the head is searched for two cylinders, that is, (V1 + V2) is calculated as the change voltage V1 (V + V2) / 2 per cylinder. Then, the servo head is released and the servo head is detached, and the adjustment process of the integrating circuit is also executed in the initialization process accompanying the power-on start of the disk apparatus as shown in step S5 of FIG.

[Position prediction including acceleration component]

The search control in the disk device of the present invention using the phase servo information does not use a track crossing pulse like the disk device using a conventional two-phase phase servo pattern. Therefore, for the calculation of the remaining number of cylinders from the speed control to the target cylinder for obtaining the target speed, the next head movement position is predicted for each sampling cycle of position detection. The remaining number of cylinders from the predicted head movement position to the target cylinder is obtained, and the target speed is obtained from the target speed pattern corresponding to the remaining number of cylinders to perform speed control. In the conventional disk device, only the speed prediction is performed for the prediction of the head position in the speed control during the search operation.

Fig. 47 shows the prediction of the conventional head moving position only by the velocity component. If the head is at position 284 at the sampling timing tn now, and the head was at position 282 in the previous sampling cast tn-1, in this case, the current head position 284 and the previous head position 282 ), And the head position 286 of the next sampling time point tn + 1 is predicted. When the predicted position 286 is determined, the remaining number of cylinders up to the target cylinder is obtained. Therefore, the corresponding target speed is obtained by referring to the target speed pattern from the remaining number of cylinders, and is set in the speed controller to execute speed control. At the same time, since the phase servo information is repeated for every four cylinders of cylinder numbers 0 to 3, the cylinder number 2 corresponding to the predicted position 286 is obtained and used for position detection based on the phase servo pattern at the next sampling time point tn + 1. The cylinder switching to select the master clock is performed.

However, in the head speed control during the search operation, the target speed pattern is acceleration, constant speed, and deceleration, and the acceleration and deceleration have acceleration components in which the detection speed at each sampling point changes. For example, during acceleration, the actual head position is at position 288 relative to predicted position 286 at sampling time tn + 1. This actual movement position 288 becomes the position beyond four cylinders of the current position 284. Therefore, at the sampling point tn + 1, the head position can only be recognized within the range of ± 2 cylinders with respect to the predicted position 186 as the actual head position 288, so the actual position before one cylinder of the predicted position 286 It is determined that the head has moved to position 290 at cylinder number 3 equal to position 288. Therefore, the predicted position at the sampling cast tn + 2 after the sampling time point tn + 1 becomes the position 294, which is greatly shifted from the actual head movement position 292. At this point, the head position is unknown and a search error occurs. Therefore, the present invention is characterized in that an acceleration component is added to the prediction of the next head position at each sampling point in addition to the velocity component.

Fig. 48 shows the prediction of the head position in the disk apparatus of the present invention in which the acceleration component is added in addition to the velocity component. Sampling time points tn-1 and tn are at positions as shown in FIG. If the head is at the position 284 at the sampling point tn now, the number of cylinders representing the head speed in the sampling period is obtained by subtracting the previous head position 282 from the current head position 284. In other words, the head moving speed is defined as the number of moving cylinders for each sampling period in position detection. The predicted position by only the velocity component at the next sampling time point tn + 1 becomes the position 286 as in the case of FIG. In other words, the number of cylinders CLv indicating the amount of head movement at the next sampling time point tn + 1 is determined by the velocity component. In the present invention, the number of cylinders CLa indicating the amount of head movement due to the acceleration at the next sampling time tn + 1 is calculated from the acceleration component at the current sampling time tn. The cylinder number CLa indicating the amount of head movement by this acceleration component is calculated based on the drive current supplied to the VCM 16 which drives a head, for example. Specifically, the number of cylinders CLa indicating the amount of head movement by the acceleration component is

CLa = (VCM indicated current value) × (acceleration correction factor)

Obtained as

The acceleration correction factor can be determined experimentally by giving the number of moving cylinders in the sampling period per unit instruction current.

FIG. 49 shows the change in speed control of the position correction amount CLa by the acceleration component obtained by multiplying the VCM command current value by the acceleration correction coefficient. That is, time t1-t2 become acceleration period. As indicated by the characteristic 298-1, the position correction amount CLa due to acceleration becomes a positive change. The section indicated by the characteristic 298-2 at the times t2 to t3 is a constant speed section. The position correction amount CLa by the acceleration component is almost zero. In addition, the section shown by the characteristic (298-3) of t3-t4 is a deceleration section. The position correction amount CLa by the deceleration acceleration component has a negative value. Therefore, as shown in the sampling point tn + 1 of FIG. 48, the head position 296 can be predicted, and the cylinder range which can be detected with respect to the actual head position 288 can be predicted correctly. At the next sampling time point tn + 1, the position at the next sampling time point tn + 1 is predicted by changing to the actual position 288 with respect to the prediction position 296.

The flowchart of FIG. 50 shows search control in the seek apparatus of the present invention for performing position prediction including acceleration. First, a target cylinder address is set in step S1. In step S2, speed control (course control) based on the target speed pattern is started. The stem S3 monitors the presence or absence of position detection based on the phase servo pattern, and detects the position every sampling period. If the position is detected, the head movement speed is obtained by subtracting the previous position from the current position in step S4. In step S5, the detection position of the next head movement position is predicted. This prediction process is performed including the velocity component and the acceleration component. In step S6, the cylinder number of the target cylinder is recognized based on the predicted position and the switching condition of the master clock is set. In step S7, it is checked whether the remaining cylinder number is less than 0.5 cylinder. In steps S2 to S7, the process is repeated until the head reaches the position before the 0.5 cylinder of the target cylinder. If it is determined that the head has moved to the position before the 0.5 cylinder of the target cylinder, the flow advances to step S8 to switch from the speed control up to that time to fine control for drawing the head to the head position indicating the target cylinder. When the control mode is switched to fine control, it is checked in step S9 whether the target cylinder falls within the range of the on track slice value for the predetermined target cylinder. If YES, the target cylinder position is recognized by raising the on track signal to a high level, and the series of search processing is completed.

The flowchart of FIG. 51 shows the detail of the position prediction shown by step S5 of FIG. In the position prediction of FIG. 43, an example is included in the range of ± 2 cylinders for each sampling cycle of the highest speed of the head moving speed. First, in step S1, it is checked whether the present position Pn is within ± 2 cylinders from the previous position Pn-1. If it exceeds +2 cylinders, it means that the head is runaway. Therefore, the flow advances to step S5 to execute the error detection process. If it is within the range of +/- 2 cylinders, the flow advances to step S2 to calculate the number of cylinder variations CLv from the previously determined head moving speed V to the next detection position. In step S3, the cylinder change number CLa to the next detection position due to the acceleration is calculated. In the final step S4, the cylinder position change number CLv based on the speed and the cylinder change number CLa based on the acceleration are added to the current position Pn to obtain the next position Pn + 1.

[Cylinder Switch by Search Speed]

In the disk apparatus of the present invention which detects the head position using the phase servo pattern, the phase servo pattern is repeatedly recorded every four cylinders. Therefore, in the phase servo region consisting of the first to fourth fields (EVEN1, ODD1, ODD2, and EVEN2), position detection is possible only when the head moving speed does not exceed the range of ± 2 cylinders around the target cylinder used for phase detection. Lose. Therefore, the head cannot be moved at a speed exceeding four cylinders in the phase servo region, so that the search operation cannot be performed at high speed.

Fig. 52 shows the state of head movement when the passage speed of the phase servo area is limited to ± 4 cylinders. In this case, the head moving speed is a value obtained by dividing the number of cylinders passing through the head in the radial direction by the width of the passage time st of the servo region seen in the right circumferential direction, and can be expressed in units of +4 [CL / st], for example. . In the following description, the head passing speed is simply expressed by the number of cylinders. The cylinder position 215 through which the head passes the boundary points of the second and third fields ODD1 and ODD2 is detected from the phase servo pattern. Therefore, if the detection position 215 is in cylinder number 0, the head position can be detected correctly at the passage speed which does not exceed the oblique area 214 which becomes +/- 2 cylinder centering on the cylinder number 0 position. The cylinder in which the detection point 215 used for the head position detection is located is defined as a center cylinder hereinafter.

In the case of FIG. 52, in the forward seek for the inside in which the cylinder address increases in the positive direction, as shown in the head movement trajectory 218, the four-cylinder phase servo region 214 is lower right from the upper left corner. ± 4 cylinders of the maximum speed of head movement through the corners. On the other hand, for the reverse seek for the negative direction in which the cylinder address decreases, i.e., the outward direction, as shown in the velocity trajectory 220, the lower left corner of the upper-right corner of the four-cylinder phase servo region 214 is shown. Head movement through the corner results in -4 cylinders at full search speed. Therefore, if the search speed is within the range of +4 cylinder to -4 cylinder, the position detection of the position 215 can be performed during the search operation as in the on-track operation with respect to the center cylinder 216. The position detection of the center cylinder 216 during the search operation is executed as a result of the position prediction shown in FIG. The master clock phase number for the cylinder number indicating the target cylinder in this case is as shown in the table of FIG. In other words, even during the search operation, cylinder switching for selecting the master clock corresponding to the cylinder number is performed as in the on-track state.

FIG. 54 shows the master clock phase number in each field of the phase servo area when the head moving speed is in the ± 4 cylinder as shown in FIG. As in the case of the on-track state, the same master clock is naturally used in all fields. For a disk device in which the head moving speed is limited to a value within a range of ± 4 cylinders centered on the center cylinder used for the head position detection during such a search operation, the present invention also centers on a head moving speed exceeding ± 4 cylinders. The head passing position of the cylinder can be detected.

55 shows cylinder switching when the maximum speed of the head moving speed in the forward direction is +6 cylinder. That is, in the conventional disk device, the same master clock is used for all four fields constituting one phase servo region, but the search speed is limited to ± 4 cylinders by this method. Therefore, the present invention is characterized by switching the cylinder in the field of the phase servo region.

55 shows two stages of cylinder switching in which the master clock is switched in two stages in the phase servo area by dividing into two fields in the first half and two fields in the second half. That is, the 1st center cylinder 228 and the 2nd center cylinder 230 which shift +/- 1 cylinder with respect to the center cylinder 216 of the detection position 215 used for head position detection are set. The cylinder switching of the master clock corresponding to the first center cylinder is performed on the first field EVEN1 and the second field ODD1. In addition, cylinder switching of the master clock corresponding to the 2nd center cylinder 230 is performed with respect to the 3rd field ODD2 and the 4th field Even2 of the latter half. As a result, for the forward search in which the cylinder address increases, the head movement with the +6 cylinder as the maximum speed can be realized as shown in the speed trajectory 232. On the other hand, for the reverse direction search to reduce the cylinder address, the speed trajectory passing through the head detection position 215 is constrained to the range of ± 1 cylinder as shown in the speed trajectory 235 so that the -2 cylinder becomes the maximum speed.

56 shows the master clock phase number in the forward search for the center cylinder 216 having the head detection position 215 in the case of enabling the search speed in the range of +6 cylinder to -2 cylinder in FIG. Indicates the master clock phase number. The cylinder switching to obtain master clocks of different phase numbers is performed in two steps for the first and second fields EVEN1 and ODD1 in the first half and the third and fourth fields ODD2 and EVEN2 in the second half.

Fig. 57 shows cylinder switching when the maximum speed in the forward direction is +7 cylinder. In this case, cylinder switching is performed step by step for each field of the first to fourth fields. That is, the first center cylinder 246, the second center cylinder 248, the third center cylinder to shift one cylinder from the first field to the fourth field with respect to the center cylinder 216 having the detection position 215. 250 and the fourth center cylinder 252 is set. The third center cylinder 250 is equal to the center cylinder 216. This sets the areas 238, 240, 242, 244 of the ± cylinder for each of the center cylinders 246, 250, 252. In this example, the maximum search speed in the forward direction, in which the cylinder address increases, becomes +7 cylinder as shown in the velocity trajectory 254. On the other hand, for the negative direction search in which the cylinder address decreases, the maximum search speed is limited to -1 cylinder.

FIG. 58 shows the correspondence relationship between the master clock phase number in each field in the cylinder changeover of FIG. 57 and the cylinder number of the center cylinder having the head detection position 215. FIG. In either case, cylinder switching is performed in which phase numbers of different master clocks are selected in steps in the first to fourth fields. 59 shows cylinder switching when the maximum speed in the forward direction is set to +10 cylinders. Cylinder switching is performed for each field similarly to FIG. In the case of FIG. 57, the cylinder switching for each field is performed across one cylinder, while in FIG. 59, the cylinder switching is performed over two cylinders. That is, the first center cylinder 268, the second center cylinder 270, the third center cylinder 272, and the fourth center to be spaced two cylinders around the center cylinder 216 having the head detection position 215. The cylinder 274 is set. For each center cylinder 268, 270, 272, 274, areas 260, 262, 264, 266 which are in the range of ± 2 cylinders are set. Therefore, the maximum speed in the forward direction becomes ± 10 cylinders as shown in the speed trajectory 276. On the other hand, the lowest cylinder speed of the forward search is regulated with respect to the head maximum speed, resulting in a +4 cylinder as shown in the speed trajectory 278. Therefore, in the cylinder switching of Fig. 59, the head can move at a search speed in the range of +4 cylinders to 10 cylinders.

FIG. 60 shows the correspondence between the combination of phase numbers of the master clock used for cylinder switching in FIG. 59 and the center cylinder number of the center cylinder 216 to which the head detection position 215 belongs.

FIG. 61 shows the cylinder shift of FIG. 52 with respect to the head moving speed at the first speed (1ST), the cylinder shift of 55 degree with the second speed (2ND), and the cylinder shift of FIG. 57 with the third speed (3RD), of FIG. The shift pattern of a kind of search speed in the case where the cylinder switching is the fourth speed 4TH is shown. In this way, the shift pattern due to the cylinder changeover can be realized, so that the device can be matched to any search speed by detecting the head moving speed and performing the cylinder changeover in which the required speed range is selected. This operation can be referred to as a function similar to the automatic transmission employed in the car.

The flowchart of FIG. 62 shows the cylinder switching process using two stages of speed switching of the first speed 1ST and the second speed 2ND shown in FIG. First, the speed Vple is read out in step S1. This velocity V is obtained from the difference between the current head position and the previous head position. In step S2, it is checked whether the speed V falls within the range of ± 4 cylinders. If YES, the flow advances to step S3 to determine the phase shift pattern by selecting the master clock phase number from the so-called first speed table shown in FIG. 54 based on the cylinder number corresponding to the predicted position of the next detected head. On the other hand, if the speed V exceeds the range of ± 4 cylinders in step S2, the flow advances to step S4 to check whether the speed V is within the range of -2 to +6 cylinders. If YES, the flow advances to step S5 to select a phase shift pattern of a combination of corresponding master clock phase numbers from the so-called second speed table of FIG. 56 corresponding to the predicted cylinder number. In Fig. 59, the maximum speed is +10 cylinders, but the maximum speed can be increased by extending the cylinder interval of the center cylinder in each field to three cylinders or four cylinders.

[Phase Servo Pattern on Data Surface]

In the disk apparatus of the present invention, a phase servo pattern equivalent to the phase servo pattern of the servo surface is also recorded for a specific cylinder of the data surface so that the head position can be detected from the read head (MR head) provided in the data head.

63 shows the frame configuration of the phase servo pattern written in the specific cylinder of the data plane. For example, in the data plane, a specific cylinder in the outer guard band area OGB1 and a specific cylinder in the inner guard band area IBG1 are provided with a servo area 340 for one rotation of the disk shown in a straight line. The servo region 340 for one rotation is divided into 216 regions similar to the servo surface of FIG. 17 to form 216 data surface servo frames 350. The data plane servo frame 350 is composed of an unused region 360 and a servo pattern portion 370 as shown in an enlarged manner. The servo pattern portion 370 is the same size as the servo pattern portion 164 of the data plane of FIG. 17. If the count value of the reference clock is zero at the head of the servo frame, the servo pattern portion 370 is in the range of count value 1268 to 1512. In the servo pattern section 370, a phase servo pattern shown in FIG. 64 and FIG. 65 is recorded.

64 and 65, the phase servo pattern is divided into a first field 372, a second field 374, a third field 376, and a fourth field 378. For the first to fourth fields, the first field 372 is called (EVEN1), the second field is (ODD1), the third field is (ODD2), and the fourth field is called (ENVEN2). It has a length of approximately 4? × 10 of the first to fourth fields. The first and fourth fields have the same phase servo pattern. The second and third fields also have the same phase servo pattern. In addition, the phases of the servo patterns of the first and fourth fields are opposite to the phases of the servo patterns of the second and third fields. This viscosity is similar to the phase servo pattern of the servo surface.

The difference between the phase servo pattern of the first to fourth fields and the phase servo pattern of the servo plane is that the phase patterns of the first field 372 (EVEN1) and the fourth field 378 (EVEN2) are shown in FIG. It is a point which has the radial position shift of 0.25 cylinder for liver. This is also the same relationship between the second field 374 (ODD1) and the third field 376 (ODD2) in FIG. As shown in Figs. 66 and 67, the data surface servo pattern is recorded in the range of ± 2.5 cylinders around the zero cylinder serving as the target cylinder. In addition, a pattern without phase shift is recorded in the region beyond the range of ± 1.5 cylinders to prevent the head position from being detected. Therefore, the number of cylinders that become the head position detection range in the data plane is limited to three cylinders, compared to the four cylinders that become the head position detection range in the servo plane. The reason why the number of cylinders at which the head position can be detected is limited to three cylinders is that the servo information recorded on the data plane is, for example, aimed at measuring the offset in a state in which the cylinder of cylinder number 0 as the target cylinder is on-track. Because. Therefore, it is sufficient to have a head detection range of about 1.5 cylinders. The error of the head position exceeding this range can be covered by the detection of the head position based on the phase servo information of the servo surface.

The reason why the phase servo patterns of the first and fourth fields of FIG. 66 are 0.25 cylinder shifts in the radial direction, and the phase servo patterns of the second and third fields of FIG. In the case of using a phase servo pattern such as the servo head 18 because the core width of the read head using the MR head installed in the data head 20 is smaller than that of the To prevent it. This relationship is described next.

Fig. 68 shows the relationship of the amount of detection to the amount of head movement when the phase servo pattern of the servo surface is read by the servo head. The boundary between the second and third fields ODD1 and ODD2 in the servo frame of the servo surface 380 is taken out, and the core width W1 of the servo head 18 is about 1 cylinder. For example, if the track pitch is 7.5 m, the core width of the servo head 18 is 7 m. With respect to the core width W1 of the servo head 18 as described above, the servo pattern is recorded on the servo surface 380 at a 0.5 cylinder pitch in the radial direction. Since the servo head 18 is always present over two servo patterns to obtain a read signal, the detection amount for the head movement amount changes linearly as shown in the characteristic 382.

FIG. 69 shows a case where the same servo pattern as the servo plane 380 of FIG. 68 is recorded on the data plane 384. FIG. Since the readhead 410 used for reading the servo pattern of the data plane 384 uses an MR head, the core width W3 is smaller than the servohead 18 so that, for example, less than half the core width of the servohead 18 is used. W3 = 3 micrometers. Therefore, when the same readout servo pattern with the readhead 410 having the small core width W3 is read as in the case of the servohead, even if the readhead 410 is completely inserted into the servo pattern having the width of 0.5 cylinder, the head position is changed. There are dead zones 390, 392, 394 that do not change at all. Therefore, the relationship between detection or not relative to the amount of head movement becomes as shown in the characteristic 386, so that the head position in accordance with the original characteristic 382 shown by the broken line becomes impossible.

In order to solve this problem, in the present invention, as shown in FIG. 70, for example, the phase servo patterns of the second and third fields ODD1 and ODD2 are shifted by 0.25 cylinder in the radial direction. For this reason, even when using the read head 410 having a small core width W3, the head movement does not cause a dead band such that the head continuously enters the phase servo pattern. As in the case of the servo surface, the detection amount with respect to the head movement amount can be obtained as shown by the linear characteristic 388. The same applies to the relationship between the first and fourth fields EVEN1 and EVEN2.

In order to write the phase servo pattern shifted by 0.25 cylinders in the first and fourth fields EVEN1 and EVEN2 and the second and third fields ODD1 and ODD2 on the data plane, 16 kinds of write signals having different phases are used. It becomes necessary. That is, in the first field 372 (EVEN1) and the second field 374 (ODD1) in the first half of FIG. 67, since each servo pattern has a length of 0.5 cylinder in the radial direction, it is shifted by 1τ as in the case of the servo plane. Write signals of eight different phases are required. In addition, since only 0.25 cylinders shift in the radial direction with respect to the third field 376 (ODD2) of FIG. 64 and the fourth field 376 (EVEN2) of FIG. 65, eight types of writings having different phases at the same writing cylinder position are provided. More signals are needed. Specifically, 8 of the phase numbers 0, 2, 4, 6, 8, 10, 12, and 14 shown in FIGS. 22A to 22I for the first field EVEN1 and the second field ODD1 in the first half. A kind write signal is used. Eight kinds of write signals of phase numbers (1, 3, 5, 7, 9, 11, 13, and 15) shown in Figs. 23B to 23I for the third field ODD2 and the fourth field EVEN2 in the latter half. Use 16 types of write signals having these phase numbers (0 to 15) are supplied from the master clock creation circuit 110 having the circuit configuration shown in FIG. 24 in the servo mode write mode for the data plane.

FIG. 71 shows the phase number of the write signal when writing the phase servo pattern in the data plane shown in FIGS. 64 and 65 in 0.25 cylinder units over a range of ± 2.5 cylinders centering on cylinder number 0 serving as the target cylinder. Indicates. Among these, the same pattern is repeated for the area exceeding ± 1.5 cylinders for the cylinder position 0.00 serving as the target cylinder, and the effective phase servo information is written in the range of ± 1.5 cylinders. Specifically, in the on-track state of the target cylinder of the data plane based on the phase servo information on the servo plane, the head of the servo write signal shown in FIG. 71 is searched for, for example, by 0.25 cylinder units from the position of -2.5 cylinder offset. The servo pattern is written at the timing of each servo frame while selecting a phase number for each of the first to fourth fields.

Fig. 72 shows the phase selection pattern of the master clock based on the cylinder switching used for detecting the position by reading the phase servo pattern of the data plane shown in Figs.64 and 65 by the readhead provided in the datahead (for three cylinders). ). When the servo pattern on the data surface is read, the target cylinder becomes the cylinder relative number 0, so that the heads do not need to be placed in the on-track state for the two cylinders on both sides. Therefore, it is sufficient to use only the master clock selection phase number of the cylinder relative number 0 fixedly.

The flowchart of Fig. 73 relates to the writing process of the servo pattern on the data surface by the disk apparatus of the present invention. As shown in Fig. 8, this writing process is executed at the stage after the writing of the phase servo information on the servo surface is completed in the final stage of the production process before shipment of the product and the automatic adjustment of the servo system is completed.

In FIG. 73, first, in step S1, the search for the start surface of the data surface writing start cylinder, that is, the head for the target cylinder is performed based on the phase information of the servo surface. As a writing start cylinder of the data plane, a specific cylinder of the outer circumference guard band region OGB1 is used for writing phase servo information on the data plane for temperature offset measurement. Since the measurement of the yaw offset is also necessary for offset measurement from the inside, when the writing of the outer circumferential guard band region OGB1 is completed, a specific cylinder of the inner circumferential guard band region IGB1 is designated as the writing cylinder. When the search operation for the write start cylinder is completed in step S2, for example, the first write pattern is selected from FIG. 69 in the search state in which the +2.5 cylinder or the -2.5 cylinder head is offset.

In step S4, the master clock of the selected write pattern phase is selected in synchronization with the servo state of the servo plane, and the phase servo pattern is written for each phase servo region in the servo frame. In step S5, it is checked whether or not writing of all patterns has been completed. In step S6, the head is searched for 0.5 cylinder offset and the flow returns to step S2 again. The next writing pattern is selected in step S3, and the servo pattern is written in the same way in step S4. The above processing is repeated until all the patterns are written in step S5.

[Read / Write Phase Servo Pattern to / from Data Surface]

In a relatively large disk apparatus, as shown in FIG. 4, the apparatus is constituted by a disk enclosure 10 having a mechanism portion including a head and a motor, and a drive controller 12 made of a printed circuit board for controlling the disk enclosure. The disk enclosure and the drive controller are integrated to form a drive module. One disk system configures one device by combining a plurality of drive modules with an upper disk control unit. Such a magnetic disk storage device constitutes a printed circuit board of the disk enclosure 10 and the drive controller 12 as a minimum unit. However, even if a device of the same model is different in the disk enclosure 10 and the drive controller 12, it is necessary to use a combination of the appropriate disk enclosure 10 and the drive controller 12. For this purpose, in the conventional disk device, a combination operation is normally performed for a change of the disk enclosure 10 in which a dip switch or the like is installed and combined on a printed circuit board on which the drive controller 12 is mounted. . However, in such a configuration, since it is necessary to artificially determine the substrate of the enclosure 10 and operate the dip switch on the drive controller 12 side, there was a fear of setting it incorrectly.

Therefore, in the disk apparatus of the present invention, a combination of the appropriate drive controller 12 in the assembling completion stage of the disk enclosure 10 allows a specific cylinder of the data surface, for example, cylinder address 0 and the outer circumferential guard band region OGB1 to be separated. The data required for the combination of the disk enclosure substrate, etc. is written into the empty cylinder using the phase servo information, and when the drive controller 12 is combined, the information of the disk enclosure is read on the drive controller 12 side and accompanied by the combination. The data writing operation using the phase servo pattern for the specific cylinder of the data plane is performed using the function of the position signal generating circuit 36 shown in FIG. Will execute.

The phase servo pattern corresponding to data bit 0 written on the data plane and its readout plate are as follows.

FIG. 74A shows a phase servo pattern indicating data bit 0. FIG. In the normal servo plane, the servo pattern is written in the range of ± 1.5 cylinders to the servo pattern shifted by only +1 cylinders. Therefore, the read pulse of the 74th b is obtained for the first to fourth fields EVEN1, ODD1, ODD2, and EVEN2. On the other hand, the master clock of Fig. 74C is a reference clock corresponding to cylinder number zero. Therefore, when the duty pulse generation circuit 120 is set in the rising section of the master clock and reset in the rising section of the read pulse, the duty pulse of Fig. 74D is obtained. That is, in the case of data bit 0, the duty pulse has a duty ratio of 25% in the first and fourth fields EVEN1 and EVEN2 and a duty ratio of 75% in the second and third fields ODD1 and ODD2. This duty pulse is extracted as the data window signal of FIG. 74E. Integrating operation by the integrating circuit yields an integral voltage -V representing data bit 0 shown in FIG. 74f.

The phase servo pattern written on the data bit 1 written on the data plane and its read waveform are as follows. In contrast to the case of the data bit 0, the phase servo pattern corresponding to the data bit 1 of the 75th phase is phased by 1τ corresponding to the case of -1 cylinder search of the head from the position of the original servo pattern with respect to the target cylinder of cylinder number 0. The same phase servo pattern is recorded in this shifted position over the range of ± 0.5 cylinders. Therefore, the duty pulse of FIG. 75d is obtained by the set by the rising section of the master clock corresponding to the target cylinder of cylinder number 0 of 75c degree and the reset by the rising section of the read pulse of FIG. 75b. That is, the duty ratio of the duty pulse is 75% in the first and fourth fields EVEN1 and EVEN2 and 25% in the second and third fields ODD1 and ODD2, which is opposite to that of the data bit 0. Therefore, the integrated voltage resulting from the duty pulse extracted by the data window signal of FIG. 75e finally becomes + V as shown in FIG. 75f.

The flowchart of FIG. 76 relates to the writing process of the phase servo pattern for the data plane corresponding to the data bits 0 and 1 shown in FIGS. 74A and 75A. This write process corresponds to the write operation performed by the write head 400 of the data head 20 according to the pattern of the phase number from the master clock write circuit 110 in FIG. This writing process is performed in parallel with the on-track control based on the head position signal by the read signal of the servo head 18. Therefore, the phase servo pattern indicating data bits 0 or 1 can be written in all servo frames of a specific cylinder of the data plane while positioning the head by the phase servo information of the servo plane.

However, the read processing of the data plane phase servo pattern prevents the on-track control based on the read signal of the servo head 18 and the restoration of the data bits 0 and 1 by the read signal from the read head 410 of the data head 20. Time-division processing should be performed by the same position signal generating circuit 36. For example, when reading across 12 frames, the phase servo pattern is read as frames 0, 13, 26, --- the first time, and frames 1, 14, 27 --- the second time, and the frame is shifted by one frame. Finally, read frames 12, 25, 38, and so on. In this way, all of 216 frames can be read.

The flowchart of FIG. 77 shows the position signal generation circuit 36 for 216 servo frames per cylinder in read processing executed by switching between the servo head 18 and the read head 410 provided in the data head 20. Recovery of the data bits based on the integral voltage from the circuit, i.e., read processing. First, in step S1, an interrupt voltage based on a predetermined data surface servo frame is received to read an integrated voltage. In step S2, it is checked whether or not this integrated voltage is a negative voltage of a prescribed value or more. If the integral voltage is a negative voltage greater than or equal to the specified value, the flow proceeds to step S3 to restore bit 0. On the other hand, if NO, the flow advances to step S4 to check whether the integrated voltage is a positive voltage higher than the specified value. If YES in step S4, bit 1 is restored in step S5. The above processing is repeated until all the bits are read in step S6. The above embodiment exemplifies 16 servo frames, that is, 16 bits of data reading and writing processing, per cylinder of the data plane. However, if the user wants to increase the data amount, the number of cylinders to be written may be increased.

[Measurement and Correction of Pleated Offset]

In the magnetic disk apparatus using the small MR head as the read head of the data head, as shown in FIG. 78, the data head 20 is positioned at the position 20 'of the innermost circumferential side and the data head 20 is optimally positioned. In the case of positioning at the position 20 on the outer circumferential side, the position shift occurs with respect to the on-track state of the writing head 400. This position shift is called the yaw angle offset. That is, the data head 20 has an outer peripheral maximum yaw angle α1 with respect to the neutral position of the center of rotation 430 of the head arm 402 when the data head 20 is moved at the inner end thereof and the outer maximum yaw angle α2 in the opposite direction to the data head 20. Position shift occurs between the write head 400 and the read head 410 provided.

79 shows an enlarged view of the data head 20. The write head 400 using the magnetic head and the read head 40 using the MR head are integrally provided. The core width W2 of the write head 400 is, for example, about 6 μm when the track pitch is 7.5 μm. On the other hand, the core width W3 of the read head 410 using the MR head is 3 μm or less, which is less than half the core width W2. The design coincides the center of the write head 410 but actually has a mechanical offset [Delta] W due to the positional shift. Data writing in the user area of the data plane is performed by on-track control of the write head 400 based on phase servo information on the servo plane. Therefore, when the user wants to switch to the read operation by the read head 410, the phase servo information is read at a position shifted from the track center by the mechanical offset? W.

In addition to the mechanical offsets ΔW of the write head 400 and the read head 410 in the data head 20, as shown in FIG. 78, offsets different for each yaw angle by the VCM 16 may be used. Between 400 and readhead 410.

FIG. 80A shows the yaw offset of the readhead 410 with respect to the track center 460 at the maximum peripheral yaw α1 in FIG. 80B shows the yaw angle offset of the read head 410 with respect to the track center 480 at the outer circumferential yaw angle α2 in FIG. As evident in the contrast between them, in the innermost circumferential side and the outermost circumferential side with respect to the yaw angle offset 0 at the center position 402 of FIG.

In FIG. 81, offsets ΔWin and ΔWout at the center cylinder address where the yaw angle offset becomes 0 °, for example, the cylinder address 2000 at the innermost maximum yaw angle on the left side and the outermost yaw angle on the right side are plotted. . Once the innermost and outermost head positions 424 and 422 are determined, an offset between them can be estimated by a straight line 428 connecting these head positions. Here, the yaw angle at the center position is 0 °, the outside side is the positive side, and the inside side is the minus side, and the mechanical offset? W at the yaw angle 0 ° is used as the origin. Looking at the maximum of the inner and outer yaw angle offsets, the outer side has a positive offset and the inner side has a negative offset.

In the disk apparatus of the present invention, as shown in FIGS. 64 and 65, the phase servo pattern is recorded in advance in the special empty cylinder of the inner circumferential guard band region IGBI on the data plane and the characteristic empty cylinder of the outer circumferential guard band region OGBI. Doing. Thus, for example, as shown in FIG. 8, the yaw offset offset process is performed at the final stage of assembly before shipment of the product to prepare the yaw offset offset table.

The flowchart of FIG. 82 shows the measurement process of the yaw angle offset by the disk apparatus of this invention. First, in step S1, the data head 20 is searched for the specific region of the inner circumferential guard band region IBGI on the innermost circumferential side of the data surface based on the phase servo pattern of the data surface. In step S2, the yaw offset [Delta] Win on the inner circumference side is measured from the data plane phase servo pattern while switching from the servo head 18 to the read head 410 of the data head 20 at constant servo frame intervals. In the measurement process of the data plane phase servo pattern, for example, every 13 frames of the servo plane servo frame among the 216 servo frames per cylinder, the operation mode is switched to the read mode of the data plane servo frame, and 16 The yaw offset is measured and finally yaw offset DELTA Win is determined as an average value. The yaw offset processing on the inner circumferential side in step S2 is executed for all the heads while switching the data heads in step S4. When the measurement processing of the inner periphery yaw offset in step S1 to S4 is completed, it progresses to step S5. Based on the phase servo pattern of the data plane, the data head 20 is searched for a specific cylinder in which the phase servo pattern of the outer circumference guard area OGBI located at the outermost circumference of the data plane is written.

When the search operation is completed, the process proceeds to step S6. In the same manner as in the case of step S2, the Servo ED 18 is transferred to the readhead 410 at a constant servo frame interval, and the outer circumferential yaw offset is measured, for example, from a phase servo pattern of 16 data plane servo frames per cylinder. The outer peripheral yaw angle offset Wout is determined as their average value. The process of step S6 is repeated until all the heads are finished in step S7 while switching the heads in step S8. When the pre-measurement of the yaw offset of the inner and outer circumferential sides is finished, the yaw angle at each cylinder position as shown in FIG. 81 by linear interpolation of the inner and outer circumferential yaw offsets? Win and Wout obtained for each data head in step S9. The offset angle calculation table is used to calculate the offset.

FIG. 83 shows an example of a correction table of the yaw angle offset created by the yaw angle offset measurement process of FIG. In this correction table, for example, one table angle offset is calculated for every 50 cylinder addresses.

The flowchart of FIG. 84 relates to the yaw angle offset correction performed by the read processing in operation by introducing the disk apparatus of the present invention into the system. First, in step S1, the head is searched for the target cylinder, and in step S2, a read operation is performed. In this reading operation, if a reading error is determined in step S3, the flow advances to step S5. With reference to the yaw angle offset table shown in FIG. 75, the yaw offset corresponding to the address of the target cylinder is read out and the data head is positioned to correct this yaw offset. In other words, the read error in step S3 occurs when the read head is greatly shifted from the write pattern written by the write head due to the yaw, and the read waveform deteriorates. To compensate for the deterioration of the read waveform, a yaw offset is performed to position the read head to the cylinder center side and retry the read operation to make the read operation successful. If there is no reading error in step S3, the normal termination response is returned as a status response in step S4, and the process returns to the main processing. Thus, by measuring the yaw offset in advance and creating a correction table, it is possible to assure the recovery of the read error by correcting the yaw offset when a reading error occurs.

[Adjust center of transducer for VCM]

85 shows the drive circuit portion of the VCM 16 provided in the drive controller 12 of the disk apparatus of the present invention. The current instruction data for the VCM 16 from the drive processor 30 is converted into an analog signal by the D / A converter 40, and is converted into a driving current by the driver circuit 42 and supplied. In the case of outputting current instruction data by the drive processor 30 as digital data of several bits in the current control of the VCM 16, the driver circuit 42 is provided to give a positive sign and an operation amount to the instruction data. A reference voltage generator 414 is provided. As the reference voltage of this reference voltage generation circuit 414, the midpoint voltage of the conversion voltage of the D / A converter 40 is set. The driver circuit 40 creates a drive voltage having a polarity and an operation amount when viewed from the reference voltage as the center. The driving voltage is converted into the driving current of the government to drive the VCM 16. Ideally, the drive voltage of the driver circuit 42 becomes zero because the converted voltage when instructing the instruction current 0 to the D / A converter 40 matches the reference voltage generated from the reference voltage generation circuit 414. However, components of the D / A converter 40 and the reference voltage generation circuit 414 have variations in resistance values and constants. Therefore, an error occurs between the center instruction voltage converted by the D / A converter 40 and the reference voltage generated by the reference voltage creation circuit 414. Unnecessary current flows due to the error in the VCM 16, so-called center offset occurs, and adversely affects servo control.

In order to solve such a problem, in the disk apparatus of the present invention, as shown in step S2 of the flowchart of FIG. 9, the center instruction voltage and the reference voltage of the D / A converter 40 are generated during the initialization process at power-on start. The error between the reference voltages generated by the circuit 414 is measured, and servo control which corrects this error is executed in the read and write processing after the initialization is completed. In order to measure the error between the center indication voltage and the reference voltage, in the embodiment of FIG. 85, the comparison circuit 416 comparing the converted voltage of the D / A converter 40 and the reference voltage of the reference voltage creation circuit 414 is renewed. Install. The comparison circuit 416 measures the error by the DAC center value adjusting unit 80, which is realized as a function of the drive processor 30 by utilizing the comparison output, to correct the correction based on the measurement error in normal read and write operations. It is supposed to be.

FIG. 86 shows measurement processing by the DAC center value adjusting unit 80 for VCM in FIG. This measurement process is divided into Mode 1 of the first half and Mode 2 of the second half. In the measurement process of mode 1, the lower limit center indication value Vcl lower than the predetermined center indication data for the D / A converter 40 by a predetermined value is set. Increasing the indication step by step increases the output voltage of the D / A comparator 40 as shown. Initially, the lower limit center indicating voltage Vc ₁ of the D / A converter 40 is lower than the reference voltage, so that the output of the comparison circuit 416 is at the L level. Increasing the indication to the D / A converter 40 inverts the output of the comparison circuit 416 to the H level when the converted voltage exceeds the actual reference voltage. The voltage Vc ₁ when the output is inverted to the H level is stored as a measured value. In Mode 1, the process is repeated four times, for example, and the final first center voltage Vc ₁ of Mode ₁ is obtained as the average value. Next, the measurement of mode 2 is started. Set a higher center than the upper limit reading instruction data center, which will measure the second mode of the D / A converter 40, and reduces gradually from the center of the upper limit voltage conversion instruction voltage V _CH. Initially, the upper center indicating voltage V _CH is higher than the actual reference voltage, so that the output of the comparison circuit 416 is inverted to L level. Therefore, the voltage Vc ₂ at this time is stored as the second center upper limit voltage. As in the case of Mode 1, four measurement processes are performed in Mode 2, and the final measured voltage Vc ₂ is obtained as the average value.

After the measurement of the above modes 1 and 2 is completed, the center indication data for the D / A converter 40 is obtained from the voltage Vc obtained by adding the measured voltage Vc ₂ of the mode 2 to the measured voltage Vc ₁ of the mode ₁ and dividing the total voltage by 2. Obtained and stored in the drive processor 30 as the corrected DAC center indication data.

The converted voltage of the center indication data of the measured D / A converter 40 is almost completely coincident with the reference voltage of the reference voltage generation circuit 414, so that an accurate center voltage can be set. The current instruction data of the VCM 16 in the drive processor 30 sets the data corresponding to the measured center instruction voltage Vc as zero point, generates data according to the sign and the manipulation amount, and outputs the data to the D / A converter 40. .

The flowchart of FIG. 87 relates to the center value adjustment process of the D / A converter of FIG. Processing in steps S1 to S5 becomes measurement processing in mode 1 of FIG. The processing in steps S6 to S10 is the measurement processing in mode 2. FIG. In step S11, calculation using the average value of the final center value Vc is performed. In step 12, the center processor value of the D / A converter 40 corresponding to the reference voltage is set in the drive processor 30. High-accuracy servo control by measuring and correcting the error between the reference voltage from the reference voltage generation circuit 414 which sets the operating point which becomes the zero point in the driver circuit 42 and the center voltage of the D / A converter. Can be done.

[Rezero action]

In the disk apparatus of the present invention, as shown in step S3 of FIG. 9, in the initialization step at the power-on start, the head is positioned in the outer guard band area OGB1 to form a cylinder address, and the zero address as the initial value is set to zero. Perform the rezero operation to set to. However, since the absolute cylinder address is not known at the stage of the rezero operation, there is a problem of speed control for searching the head in the outer guard band region for the head in the innermost contact start / stop region (CSS region).

That is, in the search control of the present invention using the phase servo pattern, the speed is detected while detecting the speed at each sampling period of the head position detection and predicting the head position at the next sampling time point. However, in the stage where the absolute cylinder number is not determined, there is an error in the target cylinder for cylinder switching based on the predicted cylinder position, so that a normal search operation cannot be expected.

Therefore, in the rezero operation of the present invention, after the head is driven by pushing the head from the innermost contact start / stop region to the outer circumferential side by acceleration control, the rezero operation of relatively zero cylinder address is performed by the integral voltage 0 obtained first. Run Based on this cylinder address, the target speed is determined by determining the target speed while obtaining the remaining number of cylinders to the target cylinder by position prediction by speed detection. When the head arrives in the outer guard band area OGB1 and the guard band detection signal is obtained, an absolute rezero operation is performed in which the absolute value of the cylinder address is zero. The flowchart in FIG. 88 shows details of the rezero process in the disk apparatus of the present invention. First, in step S1, the head floating in the contact start / stop area is driven by being driven from the inner circumference side to the outer circumference side by supplying the acceleration current to the VCM 16. In this state, the phase number of the master clock due to cylinder switching in step S2 is fixed to zero. In step S3, the movement time T for four cylinders is measured from the integral voltage number. Specifically, since the integral voltage changes in four stages due to the movement of the four cylinders, the movement time T of the four cylinders can be measured by detecting the change of the integral voltage of the four stages. In step S4, the number of cylinders per unit time, that is, the speed V, is calculated by dividing the number of cylinders 4 by the measurement movement time T. When the speed V is calculated, it is checked in step S5 whether the integral voltage is 0 voltage, that is, whether the head has reached the cylinder corresponding to phase number 0 of the master clock. The timing advances to step S6 when the integrated voltage reaches zero. In step S6, a relative rezero operation is performed in which the value Lpos of the position indicating the movement amount with respect to the absolute position of the head is made relatively zero. Switch the control mode to speed control in stem S7. In this speed control step, since the head position is obtained relatively in step S6, the position rule at the next sampling time point becomes possible in step S8. In addition, the position prediction may include the acceleration component as shown in FIG.

If the position of the next sampling time point is predicted in step S8, the master clock of the phase number according to the cylinder of the predicted position is selected in step S9, and the target velocity of the target cylinder pattern of the speed control pattern is obtained from the remaining number of cylinders up to the target cylinder. . The speed control is repeated until the outer guard band OGB1 is detected in step S10. When the outer guard band OGB1 is detected in step S10, in step S11, the original rezero operation of setting Lpos indicating the value of the position to zero again is executed. As a result, the rezero operation is terminated, and the control mode is switched to fine control for on-track to the cylinder address where the outer guard band OBG1 is detected in step S12.

As described above, in the disk apparatus of the present invention, even in the zero operation state in which the absolute position of the head is not determined, the speed control based on the speed detection based on the speed detection can be reliably performed, and the head is placed in the outer guard band region. You can certainly search for it and perform zero operation correctly.

[Auto Adjustment of Servo Meter]

In order to optimize the search control in the magnetic disk device, it is desired to minimize the setting time when switching from the coarse control which performs the speed control to the fine control. As an adjustment method of the servo system which suppresses this setting time to a minimum time, there is a method of determining the gain of acceleration / deceleration in the target speed pattern as the adjustment value by measuring the absolute position error integral value of FIG.

As another method, as shown in FIG. 90, there is an adjustment method of adjusting the speed gain at the acceleration / deceleration of the target speed pattern as the adjustment value K so as to minimize the course time as the evaluation function. The position error integration value employed as the evaluation function in FIG. 89 is the course of the head after the head reaches the position in front of the 0.5 cylinder of the target cylinder, as shown in the target speed pattern in FIG. 92a, the search current in FIG. 92b, and the position signal in FIG. 92c. The absolute value is obtained by integrating the error of the position signal from control to fine control and entering the on-track state.

The course time Tc employed as the evaluation function in FIG. 90 is the time from the start of speed control to the position before the head reaches the 0.5 cylinder of the target cylinder, as shown in FIG. 92c. The position error absolute integral value Δ1 and the course time Tc used as these evaluation functions are K1, K2, which indicate the slope gain during acceleration and deceleration in the target speed pattern of FIG. 92a, for example, the acceleration. It changes by switching K3. In other words, for the absolute position error absolute value? I, as shown in FIG. 89, the characteristic value 418 is varied with respect to the change in the adjustment value K as the speed gain, and the optimum value of the evaluation function? I is obtained by two of the singular points 420 and 422. Lose. As for the course time Tc, as shown in FIG. 90, the characteristic 424 is obtained with respect to the adjustment value K. In this case, the evaluation function Tc is obtained by the singular point 426.

However, in the case where the absolute position error absolute value? I is used as the evaluation function of FIG. 89, even if the evaluation function? I is the minimum value, the course time is too long and the search performance is poor as a whole, so that the optimum servo system adjustment state is not necessarily obtained. In the case where the course time Tc of FIG. 90 is used as the evaluation function, the course time can be shortened as much as possible, but the stability time until the head enters the on-track state becomes long, and thus the overall search performance optimization cannot be expected.

Therefore, in the stable automatic adjustment of the servo system of the present invention, both the position error absolute integral? I of FIG. 89 and the course time Tc of FIG. 90 are taken into the evaluation function to optimize the adjustment value K as the speed gain. Specifically, the search operation is repeated while adding and subtracting the speed gain as the adjustment value K, and the position error absolute integral value? I and the course time Tc are measured for each search operation. The characteristic 428 with respect to the adjustment value K shown in FIG. 91 is measured as an evaluation function (ΔI + Tc) obtained by adding these two values. When this characteristic 428 is obtained, the singular point 430 is obtained as an optimal adjustment value with the evaluation function? I + Tc as the minimum value. It is sufficient to set the speed gain at the acceleration / deceleration of the target speed pattern shown in FIG. 92A to the adjustment value K of the singular point 430. As shown in Fig. 8, the stable automatic adjustment of the servo system is executed in the final process of the product release step.

Such a stable adjustment in the search control of the present invention makes it possible to align the optimum adjustment value for minimizing the course time and the absolute position error integral value, and can greatly improve the search performance. In addition, since the stable automatic adjustment is performed for each disk device, an optimum adjustment state can be obtained in which device variations are also absorbed.

[Expansion of On Track Slice Value at Clearing]

In the disk apparatus of the present invention, when a padding command is received by the disk controller unit, the section from arbitrary recording of the designated cylinder address to the index detection is erased by alternating current using the write head. Similarly to the read operation and the write operation, an error is determined when the position error at the time of on-track becomes larger than the preset on-track slice value during the erase operation in the padding process. The retry operation is executed in the read operation or the write operation for this error determination. However, in the padding process of erasing all of the specified recordings from the indexes, the padding process is forcibly terminated when an error occurs due to an error on the on-track state.

Therefore, the write data after forcibly ending the padding process is not erased. The higher disk controller unit cannot detect abnormal termination during the padding process, and thus separate processing is executed. Therefore, there is a difference between the recognition of the management state of data in the upper disk controller unit and the data state in the actual disk device. For example, there is a problem in that an abnormal state in which IDs having the same numbers exist in the same cylinder exists, and as a result, the processing is terminated due to an error as a device error. Therefore, the disk apparatus of the present invention is characterized in that, during the padding process, the on track slice value used during the read operation or the write operation is enlarged during the padding process in order to avoid abnormal termination due to the on track error.

FIG. 93 shows a state in which the write head 400 and the read head 410 provided in the data head at the center of the cylinder of cylinder number 1 are on track. If the track pitch TP with respect to the center of the adjacent cylinder center is now 7.5 m, for example, the core width W1 of the writing head 400 is 6 m, which is smaller than the TP value. The core width W3 of the readhead 410 using the MR head is about 3 mu m, which is half of W1. In the padding process, the write head 400 alternately erases the cylinder record data. The erasing range may be shifted from the track center unless the read head reading area provided in the adjacent cylinder is erased. That is, during the padding process, the write head 400 is accommodated in the range of ± W _S2 as shown. Here, ± W _S2 = ± 3 µm.

FIG. 94 shows the on-track slice value ± W _S1 during the read / write operation in the disk apparatus of the present invention and the on-track slice value ± W _S2 during padding determined by FIG. On-track slice value ± W _S1 at the time of reading or writing is about ± 1 micrometer normally. On the other hand, the on-track slice value +/- W _S2 at the time of padding by this invention can be expanded to 3 micrometers at the maximum. For example, it is good to set it as +/- 2micrometer.

The flowchart of FIG. 95 relates to the padding process in the disk apparatus of the present invention. This padding process first searches the head for the target cylinder designated by the upper disk controller unit in step S1. When the head reaches the position in front of the 0.5 cylinder of the target cylinder in step S2, the flow advances to step S3 to switch the control mode to fine control. In this fine control, the on-track state is monitored using the on-track slice value ± W _S1 used during normal reading or writing. If the head position is within the target cylinder ± W _S1 range, raise the on-track detection signal to a high level. This is discriminated in step S4 so that the control mode is switched from search control to on-track control. When the control mode is switched to the on track control, the normal on track slice value is switched to the on-track slice value ± W _S2 for enlarged padding in step S5. The erase operation from the decodin designated in step S6 to the detection of the index is performed. During the erasing operation, it is checked whether or not the on-track slice value ± W _S2 enlarged in step S7 exceeds the head position signal. If YES, abnormal termination ends in step S10. However, in the present invention, since the on-track slice value is enlarged to be sufficiently larger than the normal read / write value, the abnormally terminated abnormally occurs because of an on track abnormality, and the erase operation can be normally terminated in step S8.

When the erasing operation ends, the track slice value back on in step S9 is returned to the original ± W _S1 , and the processing returns to the main processing. In such a padding operation, by using an enlarged on track slice value larger than a normal on track slice value, the situation where the padding process ends abnormally in the middle can be minimized.

[Etc]

In the above embodiment, as shown in FIG. 10, the case where the zero cross detection circuit 112 is used for the read signal of the phase servo pattern and the peak detection circuit 100 is used for the other read signals has been described and explained. On the other hand, as a modification of the present invention, a peak pulse detection circuit may be used for all read signals of the servo frame. Specifically, the zero cross detection circuit 112 is omitted, and the servo head 18 and the read head 410 are connected to the peak detection circuit 100 through the selection circuit 116 to output the output of the peak detection circuit 100. It is input to the variable delay circuit 114.

In this case, a read pulse is generated by detecting the peak timing of all the read signals in the training area, the index guard band area, the marker area, and the servo area of the servo frame. In this case, the adjustment to the duty ratio 50% by the shifter 108 and the variable delay circuit 114 ensures a phase shift due to the circuit delay.

On the other hand, as another variation of the present invention, the peak detection circuit 100 may be substituted instead of the zero cross detection circuit. In this case, all the read signals of the training area, the index guard band area, the marker area, and the servo area of the servo frame may be replaced. The detection pulse is generated by the detection of the zero cross timing.

Specifically, the peak detection circuit 100 is omitted, and the servo head 18 and the read head 410 are connected to the zero cross detection circuit 112 through the selection circuit 116 and the output of the zero cross detection circuit 112 is performed. Is input to the PLL circuit 102, the marker detection circuit 104, the guard band index detection circuit 105, and the variable delay circuit 114. In this case, the adjustment to the duty ratio 50% by the shifter 108 and the variable delay circuit 114 ensures an abnormality due to the circuit delay.

The disk device of the present invention is not limited to the above embodiment, and various combinations and modifications can be made within the scope described in the embodiment. In addition, this invention is not limited to the numerical value shown in the Example.

Claims (52)

In each of the plurality of servo frames arranged in the circumferential direction of each cylinder with a plurality of cylinders as one unit, a servo area in which servo information having a phase change and servo information having a reverse phase change is recorded is provided. A disk medium having a training area in which timing information is recorded in a rotational direction forward position of the servo area, and a servo surface having a marker area in which marker information for determining the servo area is recorded; A servo head moving in the radial direction of the disk medium to read recording information of the servo surface; A read pulse detection circuit section for detecting a read signal of the servo frame by the servo head and outputting a read pulse; A clock generation circuit section for generating a reference clock phase locked to a read pulse of a timing signal obtained by the read pulse circuit section by reading the training region; A master clock generation circuit section for generating a plurality of master clocks having a phase different from a reference phase of a reference clock of the clock generation circuit section, selecting and outputting a master clock having a phase corresponding to a target cylinder on which the servo head is on-tracked; A duty pulse generation circuit section for generating a duty pulse having a duty ratio corresponding to a phase difference in a range from the reference phase of the master clock outputted by the master clock generation circuit section to the timing of detection of the servo information by the read pulse detection circuit section; An integrating circuit section for integrating the duty pulse from the duty pulse generating circuit section to generate a position signal indicative of the position of the servo head; A duty measurement circuit unit for measuring a duty ratio of the duty pulse in an on-track state of the servo head with respect to a specific target cylinder in an initialization process immediately after power-up; And a duty adjustment circuit portion for generating an adjustment state for maintaining the duty ratio of the duty pulse at 50% in an on-track state of a target cylinder based on a measurement result of the duty measurement circuit portion. The servo field of claim 1, wherein the servo area of the servo plane is divided into four fields to record servo information having one phase change in the first and fourth fields of the four fields, and at the same time inverse to the second and third fields. A disk apparatus for recording servo information having a phase change. 2. The apparatus of claim 1, wherein the read pulse detection circuit unit comprises: a peak detection circuit unit for detecting peak timings of the read signals of the training area and the marker area by the servo head and outputting peak detection pulses; And a zero cross detection circuit portion for detecting a zero cross timing of a read signal of the servo area by the servo head and outputting a zero cross detection pulse. The disk apparatus according to claim 1, wherein the read detection circuit unit detects zero cross timings of the read signal of the training area, the marker area, and the servo area by the servo head and outputs a read pulse. . 5. The disk apparatus according to claim 3 or 4, wherein a low pass filter means is provided in a step before said zero cross detection circuit portion. The disk apparatus according to claim 1, wherein the read pulse detection circuit unit detects peak timings of the training region, the marker region, and the read signal of the servo region by the servo head and outputs a read pulse. . 2. The system of claim 1, wherein the duty measurement circuitry integrates the portions of the duty pulses corresponding to the first and fourth fields of the servo information as they are by the integrating circuit portion, and to the second and third fields of servo information. And integrating the corresponding duty pulse and integrating by the integrating circuit section to obtain an integral signal indicating the duty ratio. The electronic device of claim 1, wherein the duty cycle controller comprises: a first delay circuit unit configured to delay a reference phase of the master clock to reduce a duty ratio; And a second delay circuit section for delaying the detection timing of the reading pulse of the servo information to increase the duty ratio. 10. The shift circuit of claim 8, wherein the first delay circuit unit includes a shift circuit for delaying stepwise at a predetermined time determined by the reference clock within one cycle of the master clock, and outputs any one shift step of the shift circuit. Selecting and giving a desired amount of delay to the master clock. 9. The disk apparatus according to claim 8, wherein said second delay circuit portion includes a plurality of delay elements having a predetermined delay amount, and selectively connects the plurality of delay elements in series to give a desired delay amount to the read pulse of the servo information. 2. The disk medium according to claim 1, wherein the disk medium also has a data area, and provides a plurality of servo frames arranged in the circumferential direction of a specific cylinder in the data plane, recording servo information having one phase change, and inverse phase. Providing a servo area in the servo frame for recording servo information having a change; And a switching circuit section for converting the read signal of the servo head and the read signal of the servo information of the data plane into a data head and inputting the converted read signal to the read detection circuit section; The duty measurement circuit section measures a duty ratio of a duty pulse obtained from the servo information of the data plane; And the duty adjustment circuit section generates an adjustment state for maintaining the duty ratio of the duty pulse obtained from the servo information on the data plane at 50% in the on-track state of the target cylinder. 12. The servo information according to claim 11, wherein the servo area of the data plane is divided into four fields, and the servo information having one phase change in the first and fourth fields of the four fields and the reverse phase change in the second and third fields. A disk device for recording the servo information. 2. The integral error according to claim 1, wherein integrating error of supplying a duty pulse corresponding to an on-track state for positioning the servo head at an arbitrary target cylinder position on the servo surface to the integrating circuit in the initialization step after power on is measured. A measuring circuit section; And an integral error correction circuit section for correcting a position signal obtained from said integrating circuit after said initialization processing by said integral error to obtain an accurate position signal. 15. The apparatus of claim 13, wherein the integral error measuring circuit unit generates a pseudo read pulse of the servo information to the duty pulse generation circuit so as to generate a duty pulse in which the first to fourth fields of the servo information all have a duty ratio of 50%. A disk device having a pseudo pulse generating circuit portion for supplying. 2. The opposite direction to the generation of a duty pulse equivalent to moving one head in one direction from the generation of a duty pulse corresponding to an on-track state for positioning the servo head in an arbitrary target cylinder of the servo plane. A measuring circuit unit for converting to a generation of a duty pulse equivalent to one cylinder shift by means of the integrating circuit unit to measure the change in each position; And a cylinder gain detecting circuit portion for detecting a position change amount per cylinder as a cylinder gain based on a measurement result of the measuring circuit portion. 16. The method of claim 15, wherein the measurement circuit is a duty pulse of the duty ratio of 50% in all the first to fourth fields of the servo information, the duty ratio is 25%, 75%, 75%, 25 in the first to fourth fields The pseudo-clock of the servo information is generated in the master clock preparation circuit to generate a duty pulse that changes by% or a duty pulse that varies by 75%, 25%, 25%, or 75% in the first to fourth fields. Disk device having a pseudo pulse generating circuit section for supplying a read pulse. The speed detecting circuit unit according to claim 1, further comprising: a speed detecting circuit unit for detecting a head moving speed at the time of searching based on a difference in head positions obtained for each sampling period; And a position prediction circuit portion for predicting a head position at a next sampling time point for each sampling period to cause the clock generation circuit portion to select a master clock of a phase corresponding to a target cylinder obtained by the position prediction. 18. The disk apparatus according to claim 17, wherein the position prediction circuit unit selects a master clock of a corresponding phase by switching target cylinders for each of the first to fourth fields of the servo region according to the head moving speed. 19. The disk apparatus according to claim 18, wherein the position prediction circuit unit increases the number of cylinder switching stages in the first to fourth fields and the number of changes of the target cylinder for each cylinder switching as the head moving speed is higher. 19. The position prediction circuit unit according to claim 18, wherein when the head moving speed defined by the number of moving cylinders for each sampling period is within the number of repeating cylinders of servo information, the position prediction circuit unit does not switch target cylinders in the first to fourth fields. A disk device that fixedly selects a master clock for a phase. 19. The method of claim 18, wherein in the case of four cylinders of the servo information, the position prediction circuit unit does not switch the target cylinders in the first to fourth fields when the head moving speed is within the range of -4 cylinders to +4 cylinders. And a master device for selecting a master clock of a phase corresponding to a target cylinder to be a center cylinder. The position prediction circuit unit according to claim 18, wherein the position prediction circuit unit is divided into first and second fields and third and fourth fields when the head moving speed defined by the number of moving cylinders of the sampling period exceeds the number of repetition cylinders of servo information. And a master clock of a phase corresponding to the switching by selecting a target cylinder in two stages. 23. The cylinder according to claim 22, wherein when the number of repeating cylinders of the servo information is four cylinders, the position prediction circuit unit has one cylinder than the center cylinder in the first and second fields when the head moving speed is within the range of -2 cylinders to +6 cylinders. A disk device for switching to fewer target cylinders and switching to one cylinder more target cylinders than the center cylinder in the third and fourth fields, respectively, to select a master clock of a corresponding phase. 19. The method according to claim 18, wherein when the head moving speed defined by the number of moving cylinders in the sampling period exceeds the number of repetition cylinders in the servo information, the position prediction circuit unit switches the target cylinders in four steps to the first to fourth fields. A disk device for separating and selecting a master clock of a corresponding phase with respect to. 25. The disk apparatus of claim 24, wherein the position prediction circuitry converts the target cylinder in four stages in units of one cylinder so that a master clock of a corresponding phase is selected for the first to fourth fields. 25. The method according to claim 24, wherein if the repetition cylinder of servo information is four cylinders, the position prediction circuit section has two cylinders less than a center cylinder in the first field when the head moving speed is within the range of -1 cylinder to +7 cylinders. Switch to the target cylinder, switch to the target cylinder one cylinder less than the center cylinder in the second field, switch to the target cylinder one cylinder more than the center cylinder in the third field, and also target two cylinder more than the center cylinder in the fourth field. A disk device that switches to a cylinder and selects a master clock of each corresponding phase. 25. The disk apparatus of claim 24, wherein the position prediction circuit unit selects a master clock of a corresponding phase for each of the first to fourth fields by switching the target cylinder in four stages in units of plural cylinders. 28. The method of claim 27, wherein the number of repetition cylinders of the servo information is four cylinders, and the position prediction circuit unit reduces the target cylinder to three cylinders less than the center cylinder in the first field when the head moving speed is within a range of +4 cylinders to +10 cylinders. Switch to target cylinder, switch to target cylinder 1 cylinder less than center cylinder in the second field, switch to target cylinder 1 cylinder more than center cylinder in the third field, and target cylinder 3 more than center cylinder in the fourth field To select the master clocks of the corresponding phases respectively. 29. The disk apparatus according to claim 17 or 28, wherein the position prediction circuit section detects the acceleration of the head movement to predict the head position at the next sampling point. 29. The disk apparatus according to claim 17 or 28, wherein the position prediction circuit unit obtains the number of moving cylinders depending on the head acceleration based on the head driving current, and adds the number of moving cylinders to the current position to calculate the predicted position. 2. The data medium of claim 1, further comprising: a data surface of the disk medium which is integrally rotated with the servo surface; A data head integrated with the servo head in the radial direction of a disk medium to read recording information of the data surface; Data plane servo write to form servo area by recording servo information with one phase change and recording servo information with reverse phase change to each of a plurality of servo frames arranged in the circumferential direction of a specific cylinder of the data plane. Disk unit with more circuitry. The data plane servo write circuit unit divides the servo area of the data plane into four fields, and writes servo information having one phase change in the first and fourth fields of the four fields, and at the same time, the second one. And a servo device for recording servo information having an inverse phase change in a third field. 33. The data write servo write circuit divides the reference clock at 1 / N, and with respect to the reference clock (1 / 4N) when the number of repeating cylinders of the servo information recorded on the servo plane is N. Generates (4N) types of write pulses having different phases by period, and selects write pulses of a predetermined phase specified by the write cylinder from the write pulses, and sends the selected write pulses to the servo area of the data plane. Disk device to write as. 33. The data clock servo write circuit unit of claim 32 generates a write pulse having an excellent phase number for phases (2N) synchronized with the rising clock section of the reference clock generation circuit section and at the same time a falling section of the reference clock. And a write pulse having a radix phase number of the remaining (2N) phase portions in synchronization with each other. 35. The data plane servo write circuit divides the reference clock into quarters and sets the eight phases in synchronization with the rising section of the reference clock when the number of repeating cylinders of the servo information recorded on the servo plane is four cylinders. A disk device that generates minute write pulses and generates the remaining eight phase write pulses in synchronization with the falling section of the reference clock. 33. The data plane servo write circuit of claim 32, wherein the data plane servo write circuit writes the servo information on the data plane at the same cylinder pitch as the servo information of the servo plane, and also the servo information of the first and fourth fields and the phase of the second and third fields. A disk device for writing information and shifting each by a predetermined cylinder pitch. The data plane servo writing circuit section writes the servo information to the data plane at the same 0.5 cylinder pitch as the servo plane and writes the servo information to the data plane. A disk device for shifting each of servo information of a field and phase information of a second field and a third field by 0.25 cylinder pitch. 33. The disk apparatus according to claim 32, wherein the data surface servo write circuit section writes servo information at a predetermined off track centered on a write target cylinder. 33. The disk apparatus according to claim 32, wherein the data surface servo write circuit section writes servo information used for off-track measurement of the data surface to an outer cylinder outside the user area of the data surface. 33. The disk apparatus according to claim 32, wherein the data surface servo write circuit unit writes servo information used for measuring yaw off-sensing of the head drive mechanism to each of the outer cylinder and the inner cylinder outside the user area of the data surface. 41. The data head according to claim 40, wherein the data head provided with the write head and the read head integrally at the initialization processing immediately after power-on is positioned in each of the outer cylinder and the inner cylinder of the data plane based on the servo information of the servo plane. A yaw offset measurement circuit section for measuring an yaw offset of the read head associated with the turning of the head arm; And a table creating circuit section for obtaining a yaw offset at each cylinder position by an interpolation calculation of the yaw offsets of the inner and outer peripheries measured by the yaw angle offset measuring circuit section and creating a correction table with the cylinder address as an index. 42. The disk apparatus according to claim 41, wherein the correction table creating circuit unit creates a correction table storing yaw offsets in units of predetermined cylinders. 42. The disk apparatus according to claim 41, further comprising a yaw offset offset circuit portion for correcting the head position by reading the yaw angle offset of the correction table when reading the data surface. 44. The disk apparatus according to claim 43, wherein the yaw offset correction circuit section corrects the yaw offset when a reading error of the data surface occurs. 2. The apparatus of claim 1, further comprising: a data writing circuit section for writing data using servo information to a specific cylinder outside the user area of the data plane; And a data reading circuit section for reading out the phase servo information written to said data writing circuit section and restoring data. 46. The phase write information of claim 45, wherein the data writing circuit unit writes the phase servo information using duty pulses having different duty ratios of the first and fourth fields and duty ratios of the second and third fields corresponding to write data bits 0 and 1. Disk device. The duty cycle of claim 46, wherein the duty cycle of the first to fourth fields is 25%, 75%, 75%, 25%, and the duty ratio of the first to fourth fields is 75%, 25%, A disk device for writing the phase servo information corresponding to write data bits 0 and 1 using two types of duty pulses of 25% and 75%. 46. The data bit according to claim 45, wherein the data reading circuit section supplies a read signal of the servo information on the data plane to the master clock generation circuit section to generate a duty pulse and to integrate the duty pulse by the integrating circuit section. Disk unit to restore 0 or 1. 2. The apparatus according to claim 1, further comprising: D / A conversion means for converting head drive data during servo control into an analog signal; A reference voltage generation circuit section for generating a reference voltage for setting a center value of the conversion output corresponding to the center value of the input data of said D / A conversion means; A driving circuit unit for supplying a driving current to the head driving unit according to the polarity and magnitude of the conversion signal of the D / A converting means with respect to the reference voltage; A center error measuring circuit unit for changing the head drive data for the A / D conversion means from the input center value in the initialization processing immediately after the power is turned on to measure an error until the converted signal matches the reference voltage; And a center error correction circuit section for correcting the head drive data for the D / A conversion means to remove the center error after the initialization process. The course time measurement according to claim 1, wherein the course time from the change of the control mode from the course control to the fine control in the search operation is measured while varying the gain for determining the acceleration / deceleration of the target speed pattern using the speed control as an adjustment value. A circuit section; An integral measurement circuit section for measuring while varying the absolute integral value of the position error from the control operation to fine control to the on-track operation in the search operation and adjusting the gain that determines the acceleration / deceleration of the target speed pattern used for the speed control as an adjustment value; ; And an adjustment circuit section for automatically adjusting the servo system by detecting an adjustment value which becomes the minimum value as an evaluation function by evaluating the sum of the course integral obtained by the measurement circuit section and the absolute integral value of the position error as an evaluation function. The disk according to claim 1, further comprising means for changing an on track slice value for determining the on track state of the head at the time of erasing the information recorded on the data surface to a value which is enlarged to a value larger than the on track slice value at the time of reading and writing. Device. The method according to claim 1, wherein an index guard band region is provided between the marker region and the servo region at the same time to record a plurality of sets of index information and guard band information, and each of the plurality of sets of index information and guard band information is read. A disk device further comprising a detection circuit portion for detecting information.