JPWO2011132418A1 - Deposition method - Google Patents
Deposition method Download PDFInfo
- Publication number
- JPWO2011132418A1 JPWO2011132418A1 JP2012511554A JP2012511554A JPWO2011132418A1 JP WO2011132418 A1 JPWO2011132418 A1 JP WO2011132418A1 JP 2012511554 A JP2012511554 A JP 2012511554A JP 2012511554 A JP2012511554 A JP 2012511554A JP WO2011132418 A1 JPWO2011132418 A1 JP WO2011132418A1
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- Prior art keywords
- target
- film
- thin film
- sputtering
- forming method
- Prior art date
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- 238000000151 deposition Methods 0.000 title description 3
- 239000010408 film Substances 0.000 claims abstract description 176
- 238000004544 sputter deposition Methods 0.000 claims abstract description 74
- 239000010409 thin film Substances 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 27
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 27
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910001868 water Inorganic materials 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims description 101
- 239000011701 zinc Substances 0.000 claims description 69
- 230000005669 field effect Effects 0.000 claims description 49
- 230000015572 biosynthetic process Effects 0.000 claims description 42
- 239000007789 gas Substances 0.000 claims description 38
- 229910052738 indium Inorganic materials 0.000 claims description 34
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 229910052760 oxygen Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 26
- 239000001301 oxygen Substances 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 25
- 229910052725 zinc Inorganic materials 0.000 claims description 24
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 23
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 14
- 229910052733 gallium Inorganic materials 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 12
- 239000012528 membrane Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 29
- 230000000052 comparative effect Effects 0.000 description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 9
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 9
- 239000011521 glass Substances 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 229910004205 SiNX Inorganic materials 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 230000005355 Hall effect Effects 0.000 description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 238000001552 radio frequency sputter deposition Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 230000001771 impaired effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 238000005477 sputtering target Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 241001175904 Labeo bata Species 0.000 description 1
- 229910018068 Li 2 O Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- -1 Ta 2 O 5 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/0021—Reactive sputtering or evaporation
- C23C14/0036—Reactive sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
- C23C14/086—Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
- C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
希ガス原子及び水分子を含み、前記水分子の含有量が前記希ガス原子に対して分圧比で0.1〜10%である気体の雰囲気下において、金属酸化物からなるターゲットをスパッタリングし、基板上に薄膜を成膜する成膜方法。Sputtering a target made of a metal oxide in a gas atmosphere containing a rare gas atom and a water molecule, wherein the content of the water molecule is 0.1 to 10% in a partial pressure ratio with respect to the rare gas atom, A film forming method for forming a thin film on a substrate.
Description
本発明は、成膜方法に関する。 The present invention relates to a film forming method.
電界効果型トランジスタは、半導体メモリ集積回路の単位電子素子、高周波信号増幅素子、液晶駆動用素子等として広く用いられており、現在、最も多く実用化されている電子デバイスである。そのなかでも、近年における表示装置の発展に伴い、液晶表示装置(LCD)のみならず、エレクトロルミネッセンス表示装置(EL)、フィールドエミッションディスプレイ(FED)等の各種表示装置において、表示素子に駆動電圧を印加して表示装置を駆動させるスイッチング素子として、薄膜トランジスタ(TFT)が多用されている。 Field effect transistors are widely used as unit electronic elements, high frequency signal amplifying elements, liquid crystal driving elements and the like of semiconductor memory integrated circuits, and are the most widely used electronic devices at present. Among them, with the development of display devices in recent years, not only liquid crystal display devices (LCD) but also various display devices such as electroluminescence display devices (EL) and field emission displays (FED), drive voltages are applied to display elements. Thin film transistors (TFTs) are frequently used as switching elements that are applied to drive display devices.
大型液晶表示装置の液晶駆動用トランジスタにおいては、従来アモルファスシリコン系半導体薄膜が使用されていた。ところが、近年のさらなる大型化、高精細化の要求に伴い、アモルファスシリコンでは移動度が不足するため、画像の書き込みが間に合わなくなってきつつある。また有機エレクトロルミネッセンス(有機EL)ディスプレイについても大型化技術が進展中で、バックプレーンに対しても、大面積で均一、かつ高移動度の材料がこれまで以上に求められている。
そこで、アモルファスシリコン系半導体薄膜のように大面積化が可能で、結晶シリコンに次いで移動度が高い材料として金属酸化物からなる透明半導体薄膜、特に、酸化インジウム、酸化亜鉛、酸化ガリウムからなる酸化物半導体薄膜が注目されている。Conventionally, an amorphous silicon-based semiconductor thin film has been used in a liquid crystal driving transistor of a large liquid crystal display device. However, with the recent demands for further enlargement and higher definition, amorphous silicon is lacking in mobility, so that image writing is not in time. Further, with respect to organic electroluminescence (organic EL) displays, a technology for increasing the size is in progress, and a material having a large area, a uniform area, and high mobility is required more than ever for the backplane.
Therefore, a transparent semiconductor thin film made of a metal oxide, particularly an oxide made of indium oxide, zinc oxide, or gallium oxide, which can be enlarged as an amorphous silicon-based semiconductor thin film and has the second highest mobility after crystalline silicon. Semiconductor thin films are attracting attention.
従来、TFT活性層に用いる酸化物半導体膜は、膜の電気特性を制御するため、酸素ガスを導入した雰囲気中で成膜されるのが一般的である。しかし、酸素分圧のわずかな振れにより、膜中のキャリア濃度が大きく変化し、半導体特性が変動するという問題があった。 Conventionally, an oxide semiconductor film used for a TFT active layer is generally formed in an atmosphere into which oxygen gas is introduced in order to control the electrical characteristics of the film. However, there is a problem that the carrier concentration in the film changes greatly due to a slight fluctuation of the oxygen partial pressure, and the semiconductor characteristics fluctuate.
この問題を解決する手段として、スパッタ成膜時のパワー密度を高くすることにより、膜中のキャリア濃度の酸素分圧依存性を緩やかにすることが知られている(特許文献1)。
しかし、パワー密度を高くした場合、成膜速度が速くなり、酸素供給速度が相対的に遅くなるため、膜中のキャリア濃度が概ね1018cm−3以上となってしまい、TFTとしたときに良好な特性が得られなくなる問題があった。As a means for solving this problem, it is known to increase the power density at the time of sputter film formation to moderate the oxygen partial pressure dependence of the carrier concentration in the film (Patent Document 1).
However, when the power density is increased, the film formation rate is increased and the oxygen supply rate is relatively decreased, so that the carrier concentration in the film is approximately 10 18 cm −3 or more. There was a problem that good characteristics could not be obtained.
上記問題を解決するためには、キャリア濃度を1018cm−3以下とする必要があるが、そのためには酸素分圧を高くしなければならない。酸素分圧を高くすると成膜速度が遅くなり、生産性が悪くなるという別の問題があった。従って、スパッタ成膜時のパワー密度を高くし、成膜速度を早くした状態で酸化物半導体を用いた良好な薄膜トランジスタを作製することは困難であった。In order to solve the above problem, the carrier concentration needs to be 10 18 cm −3 or less, and for this purpose, the oxygen partial pressure must be increased. When the oxygen partial pressure is increased, there is another problem that the film forming speed is lowered and the productivity is deteriorated. Therefore, it has been difficult to manufacture a favorable thin film transistor using an oxide semiconductor in a state where the power density at the time of sputtering film formation is increased and the film formation speed is increased.
特許文献2は、水蒸気分圧を導入して成膜した原子比In:Ga:Zn=0.98:1.02:4の半導体膜を用い、チャンネル層の厚さが45nmのトップゲート型の薄膜トランジスタを開示する。また、特許文献3ではIn、Znの少なくとも一方の元素、及び水素を含むアモルファス酸化物半導体が開示されている。
しかしながら、これらはいずれも4インチサイズ以下のターゲットで適用される技術であり、実生産を想定した高速成膜に関しては改良の余地があった。Patent Document 2 uses a top gate type semiconductor film having an atomic ratio of In: Ga: Zn = 0.98: 1.02: 4 formed by introducing a partial pressure of water vapor and a channel layer having a thickness of 45 nm. A thin film transistor is disclosed. Patent Document 3 discloses an amorphous oxide semiconductor containing at least one of In and Zn, and hydrogen.
However, these are all technologies applied to a target of 4 inches or less, and there is room for improvement in high-speed film formation assuming actual production.
非特許文献3は、10−2Pa以上の水蒸気分圧で原子比In:Ga:Zn=1.3:1.3:1.0の半導体膜を成膜し、チャンネル層の膜厚が30nmのボトムゲート構成且つボトムコンタクト構成を有する薄膜トランジスタを開示する。
しかし、水蒸気分圧を導入して成膜した薄膜トランジスタは、電界移動度が3cm2/Vs程度と酸素導入時よりも特性が低くなり、大面積且つ高精細な表示装置に用いるには特性が不十分である。Non-Patent Document 3 forms a semiconductor film with an atomic ratio of In: Ga: Zn = 1.3: 1.3: 1.0 at a water vapor partial pressure of 10 −2 Pa or more, and the channel layer has a thickness of 30 nm. A thin film transistor having a bottom gate configuration and a bottom contact configuration is disclosed.
However, a thin film transistor formed by introducing a partial pressure of water vapor has an electric field mobility of about 3 cm 2 / Vs, which is lower than that when oxygen is introduced, and is not suitable for use in a large-area and high-definition display device. It is enough.
上記問題に加えて、液晶ディスプレイ等の平面ディスプレイの製造時の基盤の大きさは、ディスプレイの大型化や激しいコストダウン競争により年々大きくなっており、最近では3m角以上のガラス基盤を用いた液晶パネルの製造が必要とされている。ところが、基盤サイズが大きくなるとチャンネル層(半導体層)の膜厚及び膜質を均一に成膜することが難しくなり、膜厚や膜質の不均一性からくる特性のばらつきが大きくなるというもう1つの問題があった。 In addition to the above-mentioned problems, the size of the base when manufacturing flat displays such as liquid crystal displays is increasing year by year due to the increase in display size and intense cost reduction competition. Recently, liquid crystals using a glass base of 3 m square or more are used. Panel manufacturing is needed. However, when the substrate size increases, it becomes difficult to uniformly form the film thickness and film quality of the channel layer (semiconductor layer), and another problem is that the variation in characteristics due to the nonuniformity of the film thickness and film quality increases. was there.
例えば、チャンネル層の膜厚を厚くすると、膜厚及び膜質の均一性は向上するが、IGZOを代表とする酸化物半導体では膜厚が厚くなるに従い、移動度が低下する、閾値電圧が負方向に大きくなる等の問題があった(非特許文献1)。特に、製造コストが低いチャンネルエッチ型のトランジスタを製造する際、チャンネル層(半導体層)がエッチィング液に晒されるため、基盤を大型化した際の不均一性の問題が顕著であった(非特許文献2)。
そのため、これまで酸化物半導体を用いた薄膜トランジスタは、通常、チャンネル層は50nm以下の薄い膜厚で作製されており(非特許文献3)、チャンネル層の厚膜が厚く(例えば50nm以上、さらには60nm以上、70nm以上)、移動度、閾値電圧等の特性の良好な薄膜トランジスタが求められていた。For example, when the channel layer thickness is increased, the uniformity of the film thickness and the film quality is improved. However, in the oxide semiconductor typified by IGZO, the mobility decreases, and the threshold voltage is negative. (Non-patent Document 1). In particular, when manufacturing a channel etch type transistor with a low manufacturing cost, the channel layer (semiconductor layer) is exposed to an etching solution, so that the problem of non-uniformity when the base is enlarged is significant (non- Patent Document 2).
Therefore, until now, in a thin film transistor using an oxide semiconductor, a channel layer is usually formed with a thin film thickness of 50 nm or less (Non-Patent Document 3), and a thick film of the channel layer is thick (for example, 50 nm or more, further Thin film transistors having good characteristics such as mobility and threshold voltage have been demanded.
特許文献4,5にはACスパッタリング装置を用いて大面積ITOの製造例が開示されている。しかしながら、酸化物半導体の場合は酸素欠損の制御がより重要であり、パワーや周波数に対して半導体のキャリア濃度がどのように影響するか不明であった。 Patent Documents 4 and 5 disclose production examples of large area ITO using an AC sputtering apparatus. However, in the case of an oxide semiconductor, control of oxygen vacancies is more important, and it has been unclear how the carrier concentration of the semiconductor affects the power and frequency.
本発明の目的は、スパッタ成膜時のパワー密度が高い状態でも成膜速度を落とすことなく、かつ膜中のキャリア濃度を1018cm−3以下に抑制する酸化物半導体膜の成膜方法を提供することである。
また、本発明の他の目的は、チャンネル層(半導体層)の膜厚が厚くても、移動度等のトランジスタ特性の良好な薄膜トランジスタを提供することである。An object of the present invention is to provide a method for forming an oxide semiconductor film that suppresses the carrier concentration in the film to 10 18 cm −3 or less without decreasing the film formation speed even in a state where the power density during sputtering film formation is high. Is to provide.
Another object of the present invention is to provide a thin film transistor having good transistor characteristics such as mobility even when the channel layer (semiconductor layer) is thick.
本発明者等は鋭意検討した結果、スパッタ成膜時に酸素を導入する代わりに水蒸気を適切に導入することで、スパッタ成膜時のパワー密度が高い状態においても成膜速度を落とすことなく、膜中のキャリア濃度を1018cm−3以下にできることを見出した。
また上記成膜方法を用いることにより、製造時間が延長されることなく安定した半導体膜の製造方法を見出した。As a result of intensive studies, the present inventors have successfully introduced water vapor instead of introducing oxygen at the time of sputtering film formation, so that the film formation rate does not decrease even when the power density at the time of sputtering film formation is high. It has been found that the carrier concentration inside can be 10 18 cm −3 or less.
Further, the present inventors have found a method for manufacturing a semiconductor film that is stable without extending the manufacturing time by using the film forming method.
本発明によれば、以下の成膜方法等が提供される。
1.希ガス原子及び水分子を含み、前記水分子の含有量が前記希ガス原子に対して分圧比で0.1〜10%である気体の雰囲気下において、金属酸化物からなるターゲットをスパッタリングし、基板上に薄膜を成膜する成膜方法。
2.前記気体の圧力が、0.1〜5.0Paである1に記載の成膜方法。
3.前記スパッタリングが、直流スパッタである1又は2に記載の成膜方法。
4.前記スパッタリングが、交流スパッタである1又は2に記載の成膜方法。
5.直流パワー密度が1〜5W/cm2である3に記載の成膜方法。
6.真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、
前記各ターゲットに交流電源から負電位及び正電位を交互に印加して前記ターゲット上にプラズマを発生させて前記基板表面上に薄膜を成膜する成膜方法であって、
前記成膜は、前記交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら行う、4に記載の成膜方法。
7.交流パワー密度が5〜20W/cm2である4又は6に記載の成膜方法。
8.前記交流電源の周波数が10kHz〜1MHzである4、6及び7のいずれかに記載の成膜方法。
9.基板の成膜面に対して垂直方向の成膜速度が1〜100nm/minである1〜8のいずれかに記載の成膜方法。
10.前記ターゲット及び基板間の距離が、基板の成膜面に対して垂直方向に1〜15cmである1〜9のいずれかに記載の成膜方法。
11.前記雰囲気の磁場強度が300〜1000ガウスである1〜10のいずれかに記載の成膜方法。
12.前記金属酸化物が、ガリウム元素(Ga)、亜鉛元素(Zn)及びスズ元素(Sn)からなら群から選択される1以上の元素、及びインジウム元素(In)を含有し、
ターゲット中のインジウム元素の含有量が、下記原子比を満たす1〜11のいずれかに記載の成膜方法。
0.2≦[In]/全金属原子≦0.8
(式中、[In]はターゲット中のインジウム元素の原子数である。
全金属原子とは、ターゲットに含まれる全ての金属原子の原子数である。)
13.前記金属酸化物が、インジウム元素(In)、ガリウム元素(Ga)及び亜鉛元素(Zn)を含有し、
ターゲット中のインジウム元素、ガリウム元素及び亜鉛元素の含有量が、下記原子比を満たす1〜11のいずれかに記載の成膜方法。
0<[In]/[Ga]<0.5
0.2<[In]/([In]+[Ga]+[Zn])<0.9
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Ga]はターゲット中のガリウム元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)
14.前記金属酸化物が、インジウム元素(In)、スズ元素(Sn)及び亜鉛元素(Zn)を含有し、
ターゲット中のインジウム元素、スズ元素及び亜鉛元素の含有量が、下記原子比を満たす1〜11のいずれかに記載の成膜方法。
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.5
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Sn]はターゲット中のスズ元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)
15.1〜14のいずれかに記載の成膜方法により得られる薄膜を150〜400℃で5〜120分間アニール処理する酸化物半導体薄膜の製造方法。
16.前記アニール処理を、少なくも酸素を含有する雰囲気下で行なう15に記載の酸化物半導体薄膜の製造方法。
17.15又は16に記載の薄膜の製造方法により得られる酸化物半導体薄膜を備えてなる電界効果型薄膜トランジスタ素子。
18.前記酸化物半導体薄膜がチャネル層である17に記載の電界効果型薄膜トランジスタ素子。
19.移動度10cm2/Vs以上であり、閾値電圧が−5〜5Vである17又は18に記載の電界効果型薄膜トランジスタ素子。According to the present invention, the following film forming method and the like are provided.
1. Sputtering a target made of a metal oxide in a gas atmosphere containing a rare gas atom and a water molecule, wherein the content of the water molecule is 0.1 to 10% in a partial pressure ratio with respect to the rare gas atom, A film forming method for forming a thin film on a substrate.
2. 2. The film forming method according to 1, wherein the gas pressure is 0.1 to 5.0 Pa.
3. 3. The film forming method according to 1 or 2, wherein the sputtering is direct current sputtering.
4). 3. The film forming method according to 1 or 2, wherein the sputtering is alternating current sputtering.
5. 4. The film forming method according to 3, wherein the direct current power density is 1 to 5 W / cm 2 .
6). The substrate is sequentially transferred to a position facing three or more targets arranged in parallel in the vacuum chamber at a predetermined interval,
A method of forming a thin film on the surface of the substrate by alternately applying a negative potential and a positive potential to each target from an AC power source to generate plasma on the target,
The film formation method according to 4, wherein the film formation is performed while switching a target to which a potential is applied between two or more targets branched and connected to at least one of the outputs from the AC power source. .
7). The film-forming method of 4 or 6 whose alternating current power density is 5-20 W / cm < 2 >.
8). The film-forming method in any one of 4, 6, and 7 whose frequency of the said AC power supply is 10 kHz-1 MHz.
9. The film-forming method in any one of 1-8 whose film-forming speed | rate of the orthogonal | vertical direction is 1-100 nm / min with respect to the film-forming surface of a board | substrate.
10. The film forming method according to any one of 1 to 9, wherein a distance between the target and the substrate is 1 to 15 cm in a direction perpendicular to a film forming surface of the substrate.
11. The film-forming method in any one of 1-10 whose magnetic field intensity of the said atmosphere is 300-1000 gauss.
12 The metal oxide contains at least one element selected from the group consisting of gallium element (Ga), zinc element (Zn) and tin element (Sn), and indium element (In),
The film-forming method in any one of 1-11 with which content of the indium element in a target satisfy | fills the following atomic ratio.
0.2 ≦ [In] / all metal atoms ≦ 0.8
(In the formula, [In] is the number of atoms of indium element in the target.
The total metal atom is the number of atoms of all metal atoms included in the target. )
13. The metal oxide contains indium element (In), gallium element (Ga) and zinc element (Zn);
The film forming method according to any one of 1 to 11, wherein the contents of indium element, gallium element and zinc element in the target satisfy the following atomic ratio.
0 <[In] / [Ga] <0.5
0.2 <[In] / ([In] + [Ga] + [Zn]) <0.9
(In the formula, [In] is the number of atoms of indium element in the target, [Ga] is the number of atoms of gallium element in the target, and [Zn] is the number of atoms of zinc element in the target.)
14 The metal oxide contains indium element (In), tin element (Sn), and zinc element (Zn),
The film-forming method in any one of 1-11 with which content of the indium element in a target, a tin element, and a zinc element satisfy | fills the following atomic ratio.
0.2 <[In] / ([In] + [Sn] + [Zn]) <0.9
0 <[Sn] / ([In] + [Sn] + [Zn]) <0.5
(In the formula, [In] is the number of atoms of indium element in the target, [Sn] is the number of atoms of tin element in the target, and [Zn] is the number of atoms of zinc element in the target.)
15. A method for producing an oxide semiconductor thin film, comprising annealing a thin film obtained by the film forming method according to any one of 15.1 to 14 at 150 to 400 ° C. for 5 to 120 minutes.
16. 16. The method for producing an oxide semiconductor thin film according to 15, wherein the annealing treatment is performed in an atmosphere containing at least oxygen.
A field effect thin film transistor element comprising an oxide semiconductor thin film obtained by the method for producing a thin film according to 17.15 or 16.
18. 18. The field effect thin film transistor element according to 17, wherein the oxide semiconductor thin film is a channel layer.
19. The field effect thin film transistor element according to 17 or 18, which has a mobility of 10 cm 2 / Vs or more and a threshold voltage of −5 to 5 V.
本発明によれば、スパッタ成膜時のパワー密度が高い状態でも成膜速度を落すことなく、かつ膜中のキャリア濃度を1018cm−3以下に抑制する酸化物半導体膜の成膜方法が提供できる。
また、本発明によれば、チャンネル層(半導体層)の膜厚が厚くても、移動度等のトランジスタ特性の良好な薄膜トランジスタを提供できる。According to the present invention, there is provided a method for forming an oxide semiconductor film, which does not decrease the film formation speed even when the power density at the time of sputtering film formation is high and suppresses the carrier concentration in the film to 10 18 cm −3 or less. Can be provided.
Further, according to the present invention, a thin film transistor having favorable transistor characteristics such as mobility can be provided even when the channel layer (semiconductor layer) is thick.
本発明の成膜方法は、希ガス原子及び水分子を含み、水分子の含有量が希ガス原子に対して分圧比で0.1〜10%である気体雰囲気下において、金属酸化物からなるターゲットをスパッタリングし、基板上に薄膜を成膜する。
尚、水分子の希ガス原子に対する分圧比とは、[H2O]/([H2O]+[希ガス原子])で表され、[H2O]は気体雰囲気中の水分子の分圧であり、[希ガス原子]は気体雰囲気中の希ガス原子の分圧である。The film forming method of the present invention comprises a metal oxide in a gas atmosphere containing a rare gas atom and a water molecule, and the content of the water molecule is 0.1 to 10% in a partial pressure ratio with respect to the rare gas atom. A target is sputtered to form a thin film on the substrate.
The partial pressure ratio of water molecules to rare gas atoms is represented by [H 2 O] / ([H 2 O] + [rare gas atoms]), where [H 2 O] is the water molecule in the gas atmosphere. It is a partial pressure, and [rare gas atom] is a partial pressure of a rare gas atom in a gas atmosphere.
本発明の成膜方法を用いると、少量の水分子を導入することにより、膜中にOH基が取り込まれ、酸素を導入して成膜した場合よりも効率的に酸素欠損の生成(キャリアの発生)を回避することができる。また導入する水分子の量が少量であるため、スパッタ速度を低下させることなく、例えば半導体膜を成膜することができる。 When the film forming method of the present invention is used, by introducing a small amount of water molecules, OH groups are taken into the film, and oxygen vacancies are generated more efficiently than when oxygen is introduced (film formation of carriers). Occurrence) can be avoided. Further, since the amount of water molecules introduced is small, for example, a semiconductor film can be formed without reducing the sputtering rate.
スパッタリング中の気体雰囲気は、希ガス原子及び水分子を含み、水分子の含有量が希ガス原子に対して分圧比で0.1〜10%であり、好ましくは0.5〜7%であり、さら
に好ましくは1.0〜5%であり、特に好ましくは、1.0〜3.0%である。
スパッタ時の水の分圧は5×10−3〜5×10−1Paが好ましい。5×10−3Pa未満の場合、膜中に取り込まれるOH基の量が少なくなるため、薄膜の酸化度が不足し、キャリア濃度が増加しやすくなる。5×10−1Paを超えると、膜中に多量のOH基が取り込まれるため、酸化が促進され、キャリア濃度と移動度が低くなる。そのためTFT素子としたときに電界効果移動度が所望の値よりも低くなってしまうおそれがある。
最適な水分圧は、放電のパワー密度やT−S距離等の種々のスパッタリングの条件により変化する。例えば放電のパワー密度が2.5W/cm2の場合は、水分圧は好ましくは3×10−3Pa〜1.5×10−2Paであり、放電のパワー密度が5.0W/cm2の場合は、水分圧は好ましくは1×10−2Pa〜1×10−1Paであり、放電のパワー密度が7.4W/cm2の場合は、水分圧は好ましくは2.0×10−2Pa〜3.5×10−2Paの範囲である。水分圧をこれら範囲にすることで、得られる薄膜のキャリア濃度を1017cm−3台後半とすることができ、TFT素子とした時に10cm2/Vs以上の高い電界効果移動度を得ることができる。The gas atmosphere during sputtering contains rare gas atoms and water molecules, and the content of water molecules is 0.1 to 10%, preferably 0.5 to 7%, in terms of partial pressure ratio with respect to the rare gas atoms. More preferably, it is 1.0 to 5%, and particularly preferably 1.0 to 3.0%.
The partial pressure of water during sputtering is preferably 5 × 10 −3 to 5 × 10 −1 Pa. When the pressure is less than 5 × 10 −3 Pa, the amount of OH groups taken into the film decreases, so that the degree of oxidation of the thin film becomes insufficient and the carrier concentration tends to increase. If it exceeds 5 × 10 −1 Pa, a large amount of OH groups are taken into the film, so that oxidation is promoted and the carrier concentration and mobility are lowered. Therefore, the field effect mobility may be lower than a desired value when the TFT element is used.
The optimum moisture pressure varies depending on various sputtering conditions such as the power density of discharge and the TS distance. For example, when the discharge power density is 2.5 W / cm 2 , the moisture pressure is preferably 3 × 10 −3 Pa to 1.5 × 10 −2 Pa, and the discharge power density is 5.0 W / cm 2. In this case, the moisture pressure is preferably 1 × 10 −2 Pa to 1 × 10 −1 Pa, and when the discharge power density is 7.4 W / cm 2 , the moisture pressure is preferably 2.0 × 10 8. −2 Pa to 3.5 × 10 −2 Pa. By setting the moisture pressure within these ranges, the carrier concentration of the obtained thin film can be in the latter half of the 10 17 cm −3 unit, and a high field effect mobility of 10 cm 2 / Vs or more can be obtained when a TFT element is obtained. it can.
水分子の含有量が希ガス原子に対して分圧比で0.1%未満の場合、膜中に十分にOH基が取り込まれないため酸素欠損の生成抑制効果が得られず、膜中のキャリア濃度を十分に低減することができないおそれがある。一方、水分子の含有量が希ガス原子に対して分圧比で10%超の場合、膜中に過剰にOH基が取り込まれ、酸化されすぎるためにキャリア濃度、移動度が低下してしまい、得られるTFT素子の移動度が低下するおそれがある。
尚、希ガス原子は、特に制限されないが、好ましくはアルゴン原子である。また、希ガス原子及び水以外に、TFT素子に影響を及ぼさない範囲で酸素及び窒素を含んでもよい。When the content of water molecules is less than 0.1% in terms of partial pressure ratio with respect to rare gas atoms, OH groups are not sufficiently taken into the film, so that the effect of suppressing the generation of oxygen vacancies cannot be obtained, and the carrier in the film There is a possibility that the concentration cannot be reduced sufficiently. On the other hand, when the content of water molecules is more than 10% in the partial pressure ratio with respect to the rare gas atoms, the OH groups are excessively taken into the film and are excessively oxidized, so that the carrier concentration and mobility are lowered. There is a possibility that the mobility of the obtained TFT element is lowered.
The rare gas atom is not particularly limited, but is preferably an argon atom. In addition to rare gas atoms and water, oxygen and nitrogen may be included within a range that does not affect the TFT element.
気体雰囲気の圧力(スパッタ圧力)は、プラズマが安定して放電できる範囲であれば特に限定されないが、好ましくは0.1〜5.0Paである。
尚、スパッタ圧力とは、アルゴン、水、酸素等を導入した後のスパッタ開始時の系内の全圧をいう。The pressure of the gas atmosphere (sputtering pressure) is not particularly limited as long as the plasma can be stably discharged, but is preferably 0.1 to 5.0 Pa.
The sputtering pressure refers to the total pressure in the system at the start of sputtering after introducing argon, water, oxygen or the like.
スパッタリングの成膜速度は、基板の成膜面に対して垂直方向に通常は1〜250nm、好ましくは1〜100nm/minであり、さらに好ましくは10〜80nm/minであり、特に好ましくは30〜60nm/minである。
成膜速度が1nm/min未満の場合、成膜速度が遅いため生産性が悪くなるおそれがある。一方、成膜速度が250nm/min超の場合、成膜速度が速くなりすぎて、膜厚の制御性が悪くなるとともに、OH基が膜中に均一に取り込まれず特性の面内均一性が損なわれるおそれがある。また、成膜速度が速すぎると膜中に十分にOH基が取り込まれないため、スパッタ成膜時に過剰な水分子の導入が必要となるおそれがある。The film formation rate of sputtering is usually 1 to 250 nm, preferably 1 to 100 nm / min, more preferably 10 to 80 nm / min, and particularly preferably 30 to 50 nm in the direction perpendicular to the film formation surface of the substrate. 60 nm / min.
When the film formation rate is less than 1 nm / min, the film formation rate is low, and thus productivity may be deteriorated. On the other hand, when the film formation rate exceeds 250 nm / min, the film formation rate becomes too high, resulting in poor controllability of the film thickness, and OH groups are not uniformly incorporated into the film, resulting in impaired in-plane uniformity of characteristics. There is a risk of being. Further, if the film formation rate is too high, OH groups are not sufficiently taken into the film, so that it is necessary to introduce an excessive amount of water molecules during sputtering film formation.
ターゲット及び基板間の距離は、基板の成膜面に対して垂直方向に好ましくは1〜15cmであり、より好ましくは5〜15cmであり、さらに好ましくは4〜8cmである。
この距離が1cm未満の場合、基板に到達するターゲット構成元素の粒子の運動エネルギーが大きくなり、良好な膜特性を得ることができないおそれがあるうえ、膜厚及び電気特性の面内分布が生じてしまうおそれがある。一方、ターゲットと基板との間隔が15cmを越える場合、基板に到達するターゲット構成元素の粒子の運動エネルギーが小さくなりすぎて、緻密な膜を得ることができず、良好な膜特性を得ることができないおそれがある。The distance between the target and the substrate is preferably 1 to 15 cm, more preferably 5 to 15 cm, and further preferably 4 to 8 cm in the direction perpendicular to the film formation surface of the substrate.
When this distance is less than 1 cm, the kinetic energy of the target constituent element particles reaching the substrate increases, and there is a possibility that good film characteristics cannot be obtained, and in-plane distribution of film thickness and electrical characteristics occurs. There is a risk that. On the other hand, if the distance between the target and the substrate exceeds 15 cm, the kinetic energy of the target constituent element particles reaching the substrate becomes too small to obtain a dense film, and good film characteristics can be obtained. It may not be possible.
磁場強度が300〜1000ガウスの雰囲気下でスパッタリングすることが望ましい。
磁場強度が300ガウス未満の場合、プラズマ密度が低くなるため高抵抗のスパッタリングターゲットの場合スパッタリングできなくなるおそれがある。一方、1000ガウス超の場合、膜厚及び膜中の電気特性の制御性が悪くなるおそれがある。It is desirable to perform sputtering in an atmosphere having a magnetic field strength of 300 to 1000 gauss.
When the magnetic field strength is less than 300 gauss, the plasma density becomes low, so there is a possibility that sputtering cannot be performed in the case of a high resistance sputtering target. On the other hand, if it exceeds 1000 gauss, the controllability of the film thickness and electrical characteristics in the film may be deteriorated.
スパッタリングの方法は特に限定されず、プラズマ活性の低いDCスパッタリング及び周波数10MHz以下の高周波スパッタリングのいずれでもよい。また、スパッタリングはパルススパッタリングでもよい。
ここでDCスパッタリングとは、直流電源を印加して行うスパッタ方法(直流スパッタ)をいい、高周波スパッタ(RFスパッタリング)とは、交流電源(交流スパッタ)を印加して行うスパッタリングをいう。また、パルススパッタリングとは、パルス電圧を印加して行うスパッタリングをいう。The method of sputtering is not particularly limited, and any of DC sputtering with low plasma activity and high-frequency sputtering with a frequency of 10 MHz or less may be used. The sputtering may be pulse sputtering.
Here, DC sputtering refers to a sputtering method (DC sputtering) performed by applying a DC power supply, and high-frequency sputtering (RF sputtering) refers to sputtering performed by applying an AC power supply (AC sputtering). Pulse sputtering refers to sputtering performed by applying a pulse voltage.
RFスパッタリングは、DCスパッタリングに比べてプラズマ密度が高く、放電電圧が下がるため、格子の乱れ等が減少し、キャリア移動度を高めることができる。また、一般的にRFスパッタリングの方が面内均一性が良好な膜が得られやすい。
そのため、RFスパッタリングより得られる膜は、TFT素子としたときの電界効果移動度も高くなることが期待される。しかし、一般的にRFスパッタリングは、DCスパッタリングよりも成膜が遅いため、工業的にはDCスパッタリングが採用されている。Since RF sputtering has a higher plasma density and lower discharge voltage than DC sputtering, lattice disturbance and the like can be reduced, and carrier mobility can be increased. In general, RF sputtering tends to provide a film with good in-plane uniformity.
Therefore, a film obtained by RF sputtering is expected to have high field effect mobility when used as a TFT element. However, since RF sputtering is generally slower than DC sputtering, DC sputtering is industrially adopted.
DCスパッタ成膜時のターゲットに印加するパワー密度は、好ましくは1〜10W/cm2であり、さらに好ましくは2〜5W/cm2である。特に好ましくは2.5〜5W/cm2である。
パワー密度が1W/cm2未満の場合、成膜速度が遅くなって生産性が悪くなるおそれがあるうえ、また放電も安定しないおそれがある。一方、スパッタパワー密度が10W/cm2超の場合、成膜速度が速くなりすぎて、膜厚の制御性及び特性の均一性が悪くなるおそれがある。The power density applied to the target at the time of DC sputtering film formation is preferably 1 to 10 W / cm 2 , and more preferably 2 to 5 W / cm 2 . Most preferably, it is 2.5-5 W / cm < 2 >.
If the power density is less than 1 W / cm 2 , the film formation rate may be slowed, resulting in poor productivity, and the discharge may not be stable. On the other hand, when the sputtering power density is more than 10 W / cm 2 , the film formation rate becomes too fast, and the film thickness controllability and the uniformity of characteristics may be deteriorated.
好適な交流スパッタリングとして以下の方法がある。
真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、上記各ターゲットに交流電源から負電位及び正電位を交互に印加して、ターゲット上にプラズマを発生させて基板表面上に成膜する。
このとき、交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら成膜を行う。即ち、上記交流電源からの出力の少なくとも1つを分岐して2枚以上のターゲットに接続し、隣り合うターゲットに異なる電位を印加しながら成膜を行う。Examples of suitable alternating current sputtering include the following methods.
The substrate is sequentially transported to a position facing three or more targets arranged in parallel at a predetermined interval in the vacuum chamber, and negative and positive potentials are alternately applied to each target from an AC power source, Plasma is generated on the target to form a film on the substrate surface.
At this time, film formation is performed while switching a target to which a potential is applied between two or more targets branched and connected to at least one of the outputs from the AC power supply. That is, at least one of the outputs from the AC power supply is branched and connected to two or more targets, and film formation is performed while applying different potentials to adjacent targets.
このスパッタリングに用いることができる装置としては、例えば特許文献3に記載の大面積生産用のAC(交流)スパッタ装置が挙げられる。この装置を用いることにより、さらなる高速成膜が可能となり、また膜キャリア濃度を再現性よく所定の値とすることができる。 As an apparatus that can be used for this sputtering, for example, an AC (alternating current) sputtering apparatus for large area production described in Patent Document 3 can be cited. By using this apparatus, it is possible to form a film at a higher speed, and to set the film carrier concentration to a predetermined value with good reproducibility.
上記のACスパッタ装置は、具体的には、真空槽と、真空槽内部に配置された基板ホルダと、この基板ホルダと対向する位置に配置されたスパッタ源とを有する。スパッタ源の要部を図1に示す。
スパッタ源は、複数のスパッタ部を有し、板状のターゲット100a〜100fをそれぞれ有し、各ターゲット100a〜100fのスパッタされる面をスパッタ面とすると、各ターゲットはスパッタ面が同じ平面上に位置するように配置される。
各ターゲット100a〜100fは長手方向を有する細長の直方体に形成され、各ターゲットは同一形状であり、スパッタ面の長手方向の縁部分(側面)が互いに所定間隔を空けて平行に配置される。従って、隣接するターゲット100a〜100fの側面は平行になる。Specifically, the AC sputtering apparatus includes a vacuum chamber, a substrate holder disposed inside the vacuum chamber, and a sputtering source disposed at a position facing the substrate holder. A main part of the sputtering source is shown in FIG.
The sputter source has a plurality of sputter units, each of which has plate-like targets 100a to 100f, and when the surface to be sputtered of each target 100a to 100f is a sputter surface, each target has a sputter surface on the same plane. It is arranged to be located.
Each of the targets 100a to 100f is formed in an elongated rectangular parallelepiped having a longitudinal direction, each target has the same shape, and the edge portions (side surfaces) in the longitudinal direction of the sputtering surface are arranged in parallel at a predetermined interval. Therefore, the side surfaces of the adjacent targets 100a to 100f are parallel.
真空槽の外部には、交流電源300a〜300cが配置されており、これら交流電源には、それぞれ対応する電極が2つずつ接続している。各交流電源300a〜300cのそれぞれの2つの端子のうち、一方の端子は隣接する2つの電極のうちの一方に接続され、他方の端子は他方の電極に接続されている。
各交流電源300a〜300cの2つの端子は正負の異なる極性の電圧を出力するようになっており、ターゲット100a〜100fは、電極に密着して取り付けられているので、隣接する2つのターゲット100a〜100fには互いに異なる極性の交流電圧が交流電源300a〜300cから印加される。従って、互いに隣接するターゲット100a〜100fのうち、一方が正電位に置かれる時には他方が負電位に置かれた状態になる。AC power supplies 300a to 300c are arranged outside the vacuum chamber, and two corresponding electrodes are connected to each of these AC power supplies. Of the two terminals of each of the AC power supplies 300a to 300c, one terminal is connected to one of the two adjacent electrodes, and the other terminal is connected to the other electrode.
Two terminals of each of the AC power supplies 300a to 300c output voltages of positive and negative different polarities, and the targets 100a to 100f are attached in close contact with the electrodes. AC voltages having different polarities are applied to 100f from the AC power supplies 300a to 300c. Therefore, when one of the targets 100a to 100f adjacent to each other is placed at a positive potential, the other is placed at a negative potential.
電極のターゲット100a〜100fとは反対側の面には磁界形成手段200a〜200fが配置されている。各磁界形成手段200a〜200fは、外周がターゲット100a〜100fの外周と略等しい大きさの細長のリング状磁石と、リング状磁石の長さよりも短い棒状磁石とをそれぞれ有している。 Magnetic field forming means 200a to 200f are arranged on the surface of the electrode opposite to the targets 100a to 100f. Each of the magnetic field forming means 200a to 200f has an elongated ring-shaped magnet whose outer periphery is substantially equal to the outer periphery of the targets 100a to 100f, and a rod-shaped magnet shorter than the length of the ring-shaped magnet.
各リング状磁石は、対応する1個のターゲット100a〜100fの真裏位置で、ターゲット100a〜100fの長手方向に対して平行に配置されている。上述したように、ターゲット100a〜100fは所定間隔を空けて平行配置されているので、リング状磁石もターゲット100a〜100fと同じ間隔を空けて配置されている。 Each ring-shaped magnet is arranged in parallel with the longitudinal direction of the targets 100a to 100f at a position directly behind the corresponding one of the targets 100a to 100f. As described above, since the targets 100a to 100f are arranged in parallel at a predetermined interval, the ring-shaped magnets are also arranged at the same interval as the targets 100a to 100f.
上記の装置を用いる場合、パワー密度は、3〜20W/cm2が好ましい。3W/cm2未満の場合、成膜速度が遅く、生産上経済的でない。20W/cm2を超えるとターゲットが破損する場合がある。パワー密度は、より好ましくは5〜20W/cm2、さらに好ましくは4〜10W/cm2である。When using said apparatus, 3-20 W / cm < 2 > is preferable for a power density. When it is less than 3 W / cm 2 , the film formation rate is slow, which is not economical for production. If it exceeds 20 W / cm 2 , the target may be damaged. Power density is more preferably 5~20W / cm 2, more preferably from 4~10W / cm 2.
ACスパッタの周波数は10kHz〜1MHzの範囲が好ましい。10kHz未満であると、騒音の問題が発生するおそれがある。1MHzを超えるとプラズマが広がりすぎるため、所望のターゲット位置以外でスパッタが行われ、均一性が損なわれることがある。より好ましいACスパッタの周波数は20kHz〜500kHzである。 The frequency of AC sputtering is preferably in the range of 10 kHz to 1 MHz. If it is less than 10 kHz, there is a risk of noise problems. If the frequency exceeds 1 MHz, plasma spreads too much, so that sputtering is performed at a position other than the desired target position, and uniformity may be impaired. A more preferable frequency of AC sputtering is 20 kHz to 500 kHz.
また、上記の装置を用いる場合、成膜速度は好ましくは70〜250nm/min、より好ましくは100〜200nm/minである。 Moreover, when using said apparatus, the film-forming speed | rate becomes like this. Preferably it is 70-250 nm / min, More preferably, it is 100-200 nm / min.
本発明の成膜方法に用いるターゲットは、金属酸化物からなるターゲットであれば特に限定されず、好ましくは以下の第1〜第3のターゲットである。 The target used for the film-forming method of this invention will not be specifically limited if it is a target which consists of metal oxides, Preferably they are the following 1st-3rd targets.
本発明の成膜方法に好適に用いることができる第1のターゲットは、金属酸化物からなるターゲットであって、当該金属酸化物が、ガリウム元素(Ga)、亜鉛元素(Zn)及びスズ元素(Sn)からなら群から選択される1以上の元素、及びインジウム元素(In)を含有し、ターゲット中のインジウム元素の含有量が、下記原子比を満たす。
0.2≦[In]/全金属原子≦0.8
(式中、[In]はターゲット中のインジウム元素の原子数である。
全金属原子とは、ターゲットに含まれる全ての金属原子の原子数である。)A first target that can be suitably used in the film formation method of the present invention is a target made of a metal oxide, and the metal oxide includes a gallium element (Ga), a zinc element (Zn), and a tin element ( Sn) contains at least one element selected from the group and indium element (In), and the content of indium element in the target satisfies the following atomic ratio.
0.2 ≦ [In] / all metal atoms ≦ 0.8
(In the formula, [In] is the number of atoms of indium element in the target.
The total metal atom is the number of atoms of all metal atoms included in the target. )
上記原子比は、好ましくは0.25≦[In]/全金属原子≦0.75であり、さらに好ましくは0.3≦[In]/全金属原子≦0.7である。
[In]/全金属原子(原子比)が0.2未満の場合、キャリア濃度が半導体領域よりも低くなってしまうおそれがある。一方、[In]/全金属原子(原子比)が0.8超の場合、スパッタリングした薄膜が結晶化しやすくなり、大面積に成膜した場合に、面内の電気特性が不均一になるおそれがある。The atomic ratio is preferably 0.25 ≦ [In] / all metal atoms ≦ 0.75, and more preferably 0.3 ≦ [In] / all metal atoms ≦ 0.7.
When [In] / total metal atoms (atomic ratio) is less than 0.2, the carrier concentration may be lower than that of the semiconductor region. On the other hand, when [In] / total metal atoms (atomic ratio) is more than 0.8, the sputtered thin film is likely to be crystallized, and in-plane electrical characteristics may be non-uniform when formed in a large area. There is.
本発明の成膜方法に好適に用いることができる第2のターゲットは、金属酸化物からなるターゲットであって、当該金属酸化物が、インジウム元素(In)、ガリウム元素(Ga)及び亜鉛元素(Zn)を含有し、ターゲット中のインジウム元素、ガリウム元素及び亜鉛元素の含有量が、下記原子比を満たす。
0<[In]/[Ga]<0.5
0.2<[In]/([In]+[Ga]+[Zn])<0.9
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Ga]はターゲット中のガリウム元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)The second target that can be suitably used in the film forming method of the present invention is a target made of a metal oxide, and the metal oxide contains indium element (In), gallium element (Ga), and zinc element ( Zn) and the contents of indium element, gallium element and zinc element in the target satisfy the following atomic ratio.
0 <[In] / [Ga] <0.5
0.2 <[In] / ([In] + [Ga] + [Zn]) <0.9
(In the formula, [In] is the number of atoms of indium element in the target, [Ga] is the number of atoms of gallium element in the target, and [Zn] is the number of atoms of zinc element in the target.)
第2のターゲットの金属酸化物は、好ましくは下記原子比を満たす。
0<[In]/[Ga]<0.45
0.3<[In]/([In]+[Ga]+[Zn])<0.9
第2のターゲットの金属酸化物は、より好ましくは下記原子比を満たす。
0<[In]/[Ga]<0.35
0.4<[In]/([In]+[Ga]+[Zn])<0.9The metal oxide of the second target preferably satisfies the following atomic ratio.
0 <[In] / [Ga] <0.45
0.3 <[In] / ([In] + [Ga] + [Zn]) <0.9
More preferably, the metal oxide of the second target satisfies the following atomic ratio.
0 <[In] / [Ga] <0.35
0.4 <[In] / ([In] + [Ga] + [Zn]) <0.9
第2のターゲットの金属酸化物についてどのような組成領域においても水分子を導入してスパッタリングをした効果を得ることができるが、[In]/[Ga]が0.5以上の場合は酸素分子を導入して成膜した場合でも酸化効果が大きいため、キャリア濃度が下がりすぎてしまい、得られる薄膜をTFT素子に用いた場合に、電界効果移動度が2cm2/Vs程度しか得ることができない。[In]/([In]+[Ga]+[Zn])が0.2以下の場合はターゲットの抵抗が高抵抗となってしまうため、DCスパッタリングやACスパッタリングができなくなるおそれがある。また[In]/([In]+[Ga]+[Zn])が0.9以上の場合は得られる薄膜が結晶化しやすくなり、大面積に成膜した場合に、面内の電気特性が不均一になるおそれがある。The effect of sputtering by introducing water molecules in any composition region of the metal oxide of the second target can be obtained, but when [In] / [Ga] is 0.5 or more, oxygen molecules Even when a film is formed by introducing a film, the oxidation effect is large, so that the carrier concentration is too low, and when the obtained thin film is used for a TFT element, a field effect mobility of only about 2 cm 2 / Vs can be obtained. . When [In] / ([In] + [Ga] + [Zn]) is 0.2 or less, the resistance of the target becomes high, and there is a possibility that DC sputtering or AC sputtering cannot be performed. In addition, when [In] / ([In] + [Ga] + [Zn]) is 0.9 or more, the obtained thin film is easily crystallized. May be non-uniform.
第2のターゲットでは、ガリウム元素の割合を減らし、インジウム元素の割合を増加させることにより、キャリア濃度やキャリア移動度を高くし、高電界効果移動度を得ることができる。
第2のターゲットの組成比が、例えば0<[In]/[Ga]<0.45且つ0.3<[In]/([In]+[Ga]+[Zn])<0.9では電界効果移動度を5〜10cm2/Vsとすることができ、0<[In]/[Ga]<0.35且つ0.4<[In]/([In]+[Ga]+[Zn])<0.9では電界効果移動度を10cm2/Vs以上とすることができるため望ましい。In the second target, by reducing the proportion of gallium element and increasing the proportion of indium element, carrier concentration and carrier mobility can be increased, and high field effect mobility can be obtained.
When the composition ratio of the second target is, for example, 0 <[In] / [Ga] <0.45 and 0.3 <[In] / ([In] + [Ga] + [Zn]) <0.9 The field effect mobility can be 5-10 cm 2 / Vs, and 0 <[In] / [Ga] <0.35 and 0.4 <[In] / ([In] + [Ga] + [Zn ]) <0.9 is desirable because the field effect mobility can be 10 cm 2 / Vs or more.
本発明の成膜方法に好適に用いることができる第3のターゲットは、金属酸化物からなるターゲットであって、当該金属酸化物が、インジウム元素(In)、スズ元素(Sn)及び亜鉛元素(Zn)を含有し、ターゲット中のインジウム元素、スズ元素及び亜鉛元素の含有量が、下記原子比を満たす。
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.5
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Sn]はターゲット中のスズ元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)A third target that can be suitably used in the film formation method of the present invention is a target made of a metal oxide, and the metal oxide contains indium element (In), tin element (Sn), and zinc element ( Zn) and the contents of indium element, tin element and zinc element in the target satisfy the following atomic ratio.
0.2 <[In] / ([In] + [Sn] + [Zn]) <0.9
0 <[Sn] / ([In] + [Sn] + [Zn]) <0.5
(In the formula, [In] is the number of atoms of indium element in the target, [Sn] is the number of atoms of tin element in the target, and [Zn] is the number of atoms of zinc element in the target.)
第3のターゲットの金属酸化物は、好ましくは下記原子比を満たす。
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.35
第3のターゲットの金属酸化物は、より好ましくは下記原子比を満たす。
0.3<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.2The metal oxide of the third target preferably satisfies the following atomic ratio.
0.2 <[In] / ([In] + [Sn] + [Zn]) <0.9
0 <[Sn] / ([In] + [Sn] + [Zn]) <0.35
More preferably, the metal oxide of the third target satisfies the following atomic ratio.
0.3 <[In] / ([In] + [Sn] + [Zn]) <0.9
0 <[Sn] / ([In] + [Sn] + [Zn]) <0.2
第3のターゲットの金属酸化物において、[In]/([In]+[Ga]+[Zn])が0.2以下の場合はターゲットの抵抗が高抵抗となってしまうため、DCスパッタリングやACスパッタリングができなくなるおそれがある。また[In]/([In]+[Ga]+[Zn])が0.9以上の場合は得られる薄膜が結晶化しやすくなり、大面積に成膜した場合に、面内の電気特性が不均一になるおそれがある。さらにスズ元素はキャリア散乱源となってしまうため、[Sn]/([In]+[Sn]+[Zn])が0.5以上の場合はキャリア移動度が低くなってしまい、得られる薄膜をTFT素子に用いた場合の電界効果移動度が5cm2/Vs以下となってしまうおそれがある。In the third target metal oxide, when [In] / ([In] + [Ga] + [Zn]) is 0.2 or less, the resistance of the target becomes high resistance. There is a possibility that AC sputtering cannot be performed. In addition, when [In] / ([In] + [Ga] + [Zn]) is 0.9 or more, the obtained thin film is easily crystallized. May be non-uniform. Furthermore, since tin element becomes a carrier scattering source, when [Sn] / ([In] + [Sn] + [Zn]) is 0.5 or more, the carrier mobility becomes low, and the resulting thin film May be 5 cm 2 / Vs or less.
第3のターゲットでは、スズ元素の割合を減らし、インジウム元素の割合を増加させることにより、キャリア濃度やキャリア移動度を制御し、高電界効果移動度を得ることができる。
第3のターゲットの組成比が、例えば0.2<[In]/([In]+[Sn]+[Zn])<0.9且つ0<[Sn]/([In]+[Sn]+[Zn])<0.35では、電界効果移動度を5〜10cm2/Vsとすることができ、0.3<[In]/([In]+[Sn]+[Zn])<0.9且つ0<[Sn]/([In]+[Sn]+[Zn])<0.2では、電界効果移動度を10cm2/Vs以上とすることができる。In the third target, by reducing the ratio of tin element and increasing the ratio of indium element, the carrier concentration and carrier mobility can be controlled, and high field effect mobility can be obtained.
The composition ratio of the third target is, for example, 0.2 <[In] / ([In] + [Sn] + [Zn]) <0.9 and 0 <[Sn] / ([In] + [Sn] + [Zn]) <0.35, the field effect mobility can be 5-10 cm 2 / Vs, and 0.3 <[In] / ([In] + [Sn] + [Zn]) < When 0.9 and 0 <[Sn] / ([In] + [Sn] + [Zn]) <0.2, the field-effect mobility can be 10 cm 2 / Vs or more.
非特許文献3では、キャリア濃度を制御するため、ターゲットはGa元素を含み、Ga元素のターゲットの全金属元素に対する原子数比が0.33である。
しかし、Ga元素の含有量が、ターゲットの全金属元素に対する原子数比で0.33を超える場合、Gaが散乱源となり、得られる薄膜が半導体層であるTFT素子は、その移動度が低下してしまうおそれがあった。一方で、Ga元素の含有量をターゲットの全金属元素に対する原子数比で0.33未満にすると、散乱源となるGaが少量となり、高い移動度が期待できるという利点を有する一方で、キャリア濃度を1018cm−3以下に制御することが困難となる問題があった。In Non-Patent Document 3, in order to control the carrier concentration, the target contains a Ga element, and the atomic number ratio of the Ga element target to all metal elements is 0.33.
However, when the Ga element content exceeds 0.33 in terms of the atomic ratio with respect to the total metal elements of the target, Ga serves as a scattering source, and the mobility of the TFT element in which the thin film obtained is a semiconductor layer decreases. There was a risk of it. On the other hand, when the content of Ga element is less than 0.33 in terms of the atomic ratio with respect to the total metal elements of the target, the amount of Ga serving as a scattering source becomes small, and there is an advantage that high mobility can be expected. There is a problem that it becomes difficult to control the thickness to 10 18 cm −3 or less.
本発明の成膜方法では、Ga元素の含有量がインジウム元素に対する原子数比で0.5未満である第2のターゲット、又はGa元素を含有しない第3のターゲットを用いて成膜した場合においても好適なTFT素子を得ることができる。特に、第3のターゲットを用いた場合、耐薬品性を向上させることができるため、エッチングストッパー層を形成せずともソース/ドレイン電極をウェットエッチングにて形成することが可能であり、さらに好適に動作するTFT素子を作製することができ、製造コストを低減することができる。 In the film forming method of the present invention, when the film is formed using the second target having a Ga element content of less than 0.5 in terms of the number ratio of atoms relative to the indium element, or the third target not containing the Ga element. Also, a suitable TFT element can be obtained. In particular, when the third target is used, chemical resistance can be improved, so that the source / drain electrodes can be formed by wet etching without forming an etching stopper layer, and more preferably. An operating TFT element can be manufactured, and the manufacturing cost can be reduced.
第1のターゲットの金属酸化物は、好ましくはインジウム元素、亜鉛元素から実質的になる又はのみからなる酸化物であり、同様に第2のターゲットの金属酸化物は、好ましくはインジウム元素、ガリウム元素及び亜鉛元素から実質的になる又はのみからなる酸化物であり、第3のターゲットの金属酸化物は、好ましくはインジウム元素、スズ元素及び亜鉛元素から実質的なる又はのみからなる酸化物である。
第1〜第3のターゲットは、本発明の効果を損なわないない範囲で例えばMg、Ca、Sr、Ba、Ti、Zr、Hf、Al、Ge、Cu、Co、Fe、Ni、Mo及び希土類元素、ランタノイド元素から選ばれる1種類以上の元素を含むことができる。The metal oxide of the first target is preferably an oxide consisting essentially of or only of indium element and zinc element. Similarly, the metal oxide of the second target is preferably indium element and gallium element. In addition, the third target metal oxide is preferably an oxide that is substantially or only composed of an indium element, a tin element, and a zinc element.
The first to third targets are, for example, Mg, Ca, Sr, Ba, Ti, Zr, Hf, Al, Ge, Cu, Co, Fe, Ni, Mo, and rare earth elements as long as the effects of the present invention are not impaired. One or more elements selected from lanthanoid elements can be included.
本発明の成膜方法により得られる薄膜をアニール処理することで、薄膜中に取り込まれたOH基がOとして酸素欠陥に入ることによりキャリア濃度を低下させることができる。アニール処理条件は好ましくは150〜400℃で5〜120分間アニール処理である。
アニール温度が150℃未満の場合、膜中に取り込まれたOH基が十分に酸素結合を作らないため、キャリア濃度を低下させる効果を得ることが難しく、400℃超の場合、結晶化が進行してしまうおそれがある。処理時間についても同様である。By annealing the thin film obtained by the film formation method of the present invention, the OH group taken into the thin film enters oxygen defects as O, so that the carrier concentration can be lowered. The annealing treatment condition is preferably an annealing treatment at 150 to 400 ° C. for 5 to 120 minutes.
When the annealing temperature is less than 150 ° C., the OH groups incorporated in the film do not sufficiently form oxygen bonds, so it is difficult to obtain the effect of reducing the carrier concentration. When the annealing temperature exceeds 400 ° C., crystallization proceeds. There is a risk that. The same applies to the processing time.
上記アニール処理は、150℃〜400℃の温度範囲であれば特に雰囲気に制限を受けるないが、少なくも酸素を含有する雰囲気下で行なうことが好ましい。酸素を含有する雰囲気下で行なうことにより、アニール処理した薄膜をTFTとしたときの特性のばらつきを抑制することができる。 The annealing treatment is not particularly limited as long as it is in the temperature range of 150 ° C. to 400 ° C., but is preferably performed in an atmosphere containing at least oxygen. By performing in an atmosphere containing oxygen, it is possible to suppress variation in characteristics when the annealed thin film is used as a TFT.
本発明の成膜方法により得られる薄膜をアニール処理して得られる酸化物半導体(以下、単に本発明の酸化物半導体という場合がある)は、薄膜トランジスタの半導体薄膜として好適に用いることができる。
本発明の酸化物半導体を含む電界効果型トランジスタは、電界効果移動度及びon−off比が高く、ノーマリーオフを示すとともに、ピンチオフが明瞭なトランジスタである。また、本発明の酸化物半導体を含む電界効果型トランジスタは、酸化物半導体を低温で成膜できるので、無アルカリガラス等の耐熱温度に限界のある基板上に構成することが可能である。An oxide semiconductor obtained by annealing a thin film obtained by the film formation method of the present invention (hereinafter sometimes simply referred to as the oxide semiconductor of the present invention) can be suitably used as a semiconductor thin film of a thin film transistor.
The field-effect transistor including an oxide semiconductor of the present invention is a transistor with high field-effect mobility and on-off ratio, normally-off, and clear pinch-off. In addition, since the field-effect transistor including an oxide semiconductor of the present invention can form an oxide semiconductor at a low temperature, the field-effect transistor can be formed over a substrate having a limit of heat resistance such as alkali-free glass.
本発明の酸化物半導体は、通常、n型領域で用いられるが、P型Si系半導体、P型酸化物半導体、P型有機半導体等の種々のP型半導体と組合せてPN接合型トランジスタ等の各種の半導体デバイスに利用することができる。また、TFTを論理回路、メモリ回路、差動増幅回路等各種の集積回路にも適用できる。さらに、電界効果型トランジスタ以外にも静電誘起型トランジスタ、ショットキー障壁型トランジスタ、ショットキーダイオード、抵抗素子に適応できる。 The oxide semiconductor of the present invention is usually used in an n-type region, but it can be used in combination with various P-type semiconductors such as P-type Si-based semiconductors, P-type oxide semiconductors, P-type organic semiconductors, and the like. It can be used for various semiconductor devices. The TFT can also be applied to various integrated circuits such as logic circuits, memory circuits, and differential amplifier circuits. In addition to field effect transistors, it can be applied to electrostatic induction transistors, Schottky barrier transistors, Schottky diodes, and resistance elements.
トランジスタの構成は、ボトムゲート、トップゲート、ボトムコンタクト、トップコンタクト等、公知の構成を制限なく利用することができる。特にボトムゲート構成が、アモルファスシリコンやZnOのTFTに比べ高い性能が得られるので有利である。ボトムゲート構成は、製造時のマスク枚数を削減しやすく、大型ディスプレイ等の用途の製造コストを低減しやすいため好ましい。 As the structure of the transistor, known structures such as a bottom gate, a top gate, a bottom contact, and a top contact can be used without limitation. In particular, the bottom gate configuration is advantageous because high performance can be obtained as compared with amorphous silicon or ZnO TFTs. The bottom gate configuration is preferable because it is easy to reduce the number of masks at the time of manufacturing, and it is easy to reduce the manufacturing cost for uses such as a large display.
大面積のディスプレイ用としては、チャンネルエッチ型のボトムゲート構成の薄膜トランジスタが特に好ましい。チャンネルエッチ型のボトムゲート構成の薄膜トランジスタは、フォトリソ工程時のフォトマスクの数が少なく低コストでディスプレイ用パネルを製造できる。中でも、チャンネルエッチ型のボトムゲート構成トップコンタクト構成の薄膜トランジスタが移動度等の特性が良好で工業化しやすいため特に好ましい。 For large-area displays, a channel-etched bottom gate thin film transistor is particularly preferable. A channel-etched bottom gate thin film transistor has a small number of photomasks at the time of a photolithography process, and can produce a display panel at a low cost. Among these, a thin film transistor having a channel etch type bottom gate structure and a top contact structure is particularly preferable because it has excellent characteristics such as mobility and is easily industrialized.
本発明の酸化物半導体を含む電界効果型トランジスタは、従来良好な特性を得ることが困難であった半導体膜の膜厚が50nm以上、さらには60nm以上、70nm以上であっても好適に作動できる。また、本発明の酸化物半導体を含む電界効果型トランジスタは、好適な移動度、オンオフ比及びS値を有する。
尚、半導体膜の膜厚の上限は例えば100nmである。The field effect transistor including an oxide semiconductor of the present invention can be suitably operated even when the film thickness of a semiconductor film, which has conventionally been difficult to obtain good characteristics, is 50 nm or more, further 60 nm or more, 70 nm or more. . In addition, the field-effect transistor including the oxide semiconductor of the present invention has preferable mobility, on / off ratio, and S value.
Note that the upper limit of the thickness of the semiconductor film is, for example, 100 nm.
本発明の酸化物半導体を含む電界効果型トランジスタのS値は、好ましくは1V/decade以下、さらに好ましくは0.7V/decade以下、特に好ましくは0.5V/decade以下である。S値の値が1V/decadeを超えると、駆動電圧が高くなる等トランジスタが良好なスイッチング特性を示さなくなるおそれがある。 The S value of the field effect transistor including an oxide semiconductor of the present invention is preferably 1 V / decade or less, more preferably 0.7 V / decade or less, and particularly preferably 0.5 V / decade or less. If the S value exceeds 1 V / decade, the transistor may not exhibit good switching characteristics such as an increase in driving voltage.
本発明の酸化物半導体を含む電界効果型トランジスタの閾値電圧は、通常は−5.0〜5.0V、好ましくは−1.0〜2.0V、より好ましくは−1.0〜1.0V、さらに好ましくは0〜1.0Vである。5Vより大きいと駆動電圧が大きくなる、消費電力が大きくなる等のおそれがあり、−5Vより小さいと消費電力が大きくなるおそれがある。 The threshold voltage of the field effect transistor containing the oxide semiconductor of the present invention is usually −5.0 to 5.0 V, preferably −1.0 to 2.0 V, more preferably −1.0 to 1.0 V. More preferably, it is 0-1.0V. If it is greater than 5 V, the drive voltage may increase and the power consumption may increase, and if it is less than −5 V, the power consumption may increase.
本発明の酸化物半導体を含む電界効果型トランジスタのチャネル長は、通常用いられる範囲であれば特に制限されるものではないが、通常10〜70μm、好ましくは20〜50μmである。
本発明の酸化物半導体を含む電界効果型トランジスタのチャネル幅は、通常10〜100μmであり、好ましくは20〜70μmである。The channel length of the field effect transistor including the oxide semiconductor of the present invention is not particularly limited as long as it is in a range usually used, but is usually 10 to 70 μm, preferably 20 to 50 μm.
The channel width of the field effect transistor including the oxide semiconductor of the present invention is usually 10 to 100 μm, preferably 20 to 70 μm.
ディスプレイの高精細化のために、TFTは微小にする必要がある。その場合、所望のオン電流を得るためには、TFTチャネル層に用いられる半導体膜には高い移動度が必要となる。
本発明の酸化物半導体を含む電界効果型トランジスタは高い移動度を有するので、1〜10μm領域、さらには2〜8μmの領域においても好適に使用することが期待できる。またチャネル幅について、本発明の酸化物半導体を含む電界効果型トランジスタは、1〜10μmの領域、さらには2〜8μmの領域においても好適に使用することが期待できる。In order to increase the definition of the display, it is necessary to make the TFT minute. In that case, in order to obtain a desired on-current, the semiconductor film used for the TFT channel layer needs high mobility.
Since the field effect transistor including the oxide semiconductor of the present invention has high mobility, it can be expected to be suitably used in a 1 to 10 μm region, and further in a 2 to 8 μm region. In addition, regarding the channel width, the field effect transistor including the oxide semiconductor of the present invention can be expected to be suitably used in a region of 1 to 10 μm, and further in a region of 2 to 8 μm.
図2は、本発明の酸化物半導体を備えてなる薄膜トランジスタの一実施形態を示す概略断面図である。
電界効果型トランジスタである薄膜トランジスタ1はボトムゲート型であり、ガラス基板60上に、ゲート電極30が形成され、その上にゲート絶縁膜50が形成されている。ゲート絶縁膜50上には、酸化物半導体膜40が形成され、さらにその上にドレイン電極10とソース電極20とが離間して形成されている。FIG. 2 is a schematic cross-sectional view showing an embodiment of a thin film transistor including the oxide semiconductor of the present invention.
The thin film transistor 1 which is a field effect transistor is a bottom gate type, and a gate electrode 30 is formed on a glass substrate 60 and a gate insulating film 50 is formed thereon. An oxide semiconductor film 40 is formed on the gate insulating film 50, and the drain electrode 10 and the source electrode 20 are further formed on the oxide semiconductor film 40.
ドレイン電極10、ソ−ス電極20及びゲート電極30の各電極を形成する材料に特に制限はなく、一般に用いられている材料を任意に選択することができる。
例えば、ITO,IZO,ZnO,SnO2等の透明電極や、Al,Ag,Cu,Cr,Ni,Mo,Au,Ti,Ta等の金属電極、又はこれらを含む合金の金属電極を用いることができる。There are no particular limitations on the material for forming the drain electrode 10, the source electrode 20, and the gate electrode 30, and any commonly used material can be selected.
For example, a transparent electrode such as ITO, IZO, ZnO, or SnO 2 , a metal electrode such as Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, or Ta, or a metal electrode made of an alloy containing these may be used. it can.
ドレイン電極10、ソ−ス電極20及びゲート電極30の各電極は、異なる2層以上の導電層を積層した多層構造とすることもでき、例えば図3では、各電極10,20及び30は、それぞれ第1導電層31,21,11及び第2導電層32,22,12から構成されている。特にソース・ドレイン電極は低抵抗配線への要求が強いため、AlやCu等の良導体をTiやMo等の密着性に優れた金属でサンドイッチして使う場合がある。 Each of the drain electrode 10, the source electrode 20, and the gate electrode 30 may have a multilayer structure in which two or more different conductive layers are stacked. For example, in FIG. The first conductive layer 31, 21, 11 and the second conductive layer 32, 22, 12 are respectively configured. In particular, since the source / drain electrode has a strong demand for low-resistance wiring, a good conductor such as Al or Cu may be sandwiched with a metal having excellent adhesion such as Ti or Mo.
ゲート絶縁膜50を形成する材料は特に制限はなく、一般に用いられている材料を任意に選択できる。
ゲート絶縁膜50の材料としては、例えばSiO2,SiNx,Al2O3,Ta2O5,TiO2,MgO,ZrO2,CeO2,K2O,Li2O,Na2O,Rb2O,Sc2O3,Y2O3,HfO3,CaHfO3,PbTi3,BaTa2O6,SrTiO3,AlN等の化合物を用いることができる。これらのなかでも、好ましくはSiO2,SiNx,Al2O3,Y2O3,HfO3,CaHfO3であり、より好ましくはSiO2,SiNx,Y2O3,HfO3,CaHfO3である。
尚、上記の酸化物の酸素数は、必ずしも化学量論比と一致していなくともよい(例えば、SiO2でもSiOxでもよい)。The material for forming the gate insulating film 50 is not particularly limited, and a commonly used material can be arbitrarily selected.
Examples of the material of the gate insulating film 50 include SiO 2 , SiNx, Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, and Rb 2. Compounds such as O, Sc 2 O 3 , Y 2 O 3 , HfO 3 , CaHfO 3 , PbTi 3 , BaTa 2 O 6 , SrTiO 3 , and AlN can be used. Among these, it is preferably SiO 2, SiNx, Al 2 O 3, Y 2 O 3, HfO 3, CaHfO 3, more preferably SiO 2, SiNx, Y 2 O 3, HfO 3, CaHfO 3 .
Note that the number of oxygen in the oxide does not necessarily match the stoichiometric ratio (for example, it may be SiO 2 or SiO x).
ゲート絶縁膜50は、異なる2層以上の絶縁膜を積層した構造でもよい。また、ゲート絶縁膜50は、結晶質、多結晶質、非晶質のいずれであってもよいが、工業的に製造しやすい多結晶質か、非晶質であるのが好ましい。 The gate insulating film 50 may have a structure in which two or more different insulating films are stacked. The gate insulating film 50 may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that is easy to manufacture industrially.
酸化物半導体膜40は、本発明の成膜方法により得られる酸化物半導体である。
酸化物半導体膜40は、通常はホール測定で求めたキャリア密度が1018cm−3未満であり、好ましくは5×1017cm−3未満であり、より好ましくは1×1017cm−3未満である。キャリア密度が1018cm−3以上の場合、漏れ電流が大きくなるおそれがある。
尚、キャリア密度の下限としては、酸化物半導体膜40を備える素子の用途にもよるが、例えば1015cm−3以上とするのが好ましい。The oxide semiconductor film 40 is an oxide semiconductor obtained by the film formation method of the present invention.
In the oxide semiconductor film 40, the carrier density obtained by hole measurement is usually less than 10 18 cm −3 , preferably less than 5 × 10 17 cm −3 , more preferably less than 1 × 10 17 cm −3. It is. When the carrier density is 10 18 cm −3 or more, the leakage current may increase.
Note that the lower limit of the carrier density is preferably, for example, 10 15 cm −3 or more, although it depends on the use of the element including the oxide semiconductor film 40.
酸化物半導体膜40の比抵抗は、四端子法で求めた値が、通常10−1〜108Ωcmであり、好ましくは101〜107Ωcmであり、より好ましくは102〜106Ωcmである。
比抵抗が10−1Ωcm未満の場合、電気が容易に流れ半導体薄膜として機能しないおそれがある。一方、比抵抗が108Ωcm超の場合、強い電界をかけないと半導体として機能しないおそれがある。As for the specific resistance of the oxide semiconductor film 40, the value obtained by the four-terminal method is usually 10 −1 to 10 8 Ωcm, preferably 10 1 to 10 7 Ωcm, and more preferably 10 2 to 10 6 Ωcm. It is.
When the specific resistance is less than 10 −1 Ωcm, electricity may flow easily and may not function as a semiconductor thin film. On the other hand, when the specific resistance exceeds 10 8 Ωcm, there is a possibility that the semiconductor does not function unless a strong electric field is applied.
酸化物半導体膜40の膜厚は、酸化物半導体40自身の比抵抗に応じて適宜最適な値が選定され、均一性の観点からは膜厚が厚い方が好ましく、成膜時間(工程のタクトタイム)の観点からは膜厚が薄い方が好ましい。
酸化物半導体膜40の膜厚は、通常は、20〜500nm、好ましくは50〜150nm、より好ましくは60〜140nm、特に好ましくは70〜130nm、特に好ましくは70〜110nmである。
酸化物半導体の膜厚が20nm未満の場合、大面積に成膜した際の膜厚の不均一性により、作製したTFTの特性が不均一になるおそれがある。一方、膜厚が500nm超の場合、成膜時間が長くなり工業的に採用できないおそれがある。The thickness of the oxide semiconductor film 40 is appropriately selected in accordance with the specific resistance of the oxide semiconductor 40 itself, and is preferably thick from the viewpoint of uniformity. From the viewpoint of (time), a thinner film thickness is preferable.
The thickness of the oxide semiconductor film 40 is usually 20 to 500 nm, preferably 50 to 150 nm, more preferably 60 to 140 nm, particularly preferably 70 to 130 nm, and particularly preferably 70 to 110 nm.
When the thickness of the oxide semiconductor is less than 20 nm, the characteristics of the manufactured TFT may be non-uniform due to non-uniformity of the thickness when the oxide semiconductor is formed over a large area. On the other hand, when the film thickness exceeds 500 nm, the film formation time becomes long and there is a possibility that it cannot be adopted industrially.
薄膜トランジスタ1の電界効果移動度は、通常1cm2/Vs以上であり、好ましくは5cm2/Vs以上、より好ましく10cm2/Vs以上、さらに好ましくは18cm2/Vs以上、特に好ましくは30cm2/Vs以上、最も好ましくは50cm2/Vs以上である。
電界効果移動度が1cm2/Vs未満の場合、スイッチング速度が遅くなるおそれがある。また、電界効果移動度の上限は例えば500cm2/Vsである。The field effect mobility of the thin film transistor 1 is usually 1 cm 2 / Vs or more, preferably 5 cm 2 / Vs or more, more preferably 10 cm 2 / Vs or more, further preferably 18 cm 2 / Vs or more, particularly preferably 30 cm 2 / Vs. Above, most preferably 50 cm 2 / Vs or more.
When the field effect mobility is less than 1 cm 2 / Vs, the switching speed may be slow. The upper limit of the field effect mobility is, for example, 500 cm 2 / Vs.
薄膜トランジスタ1のon−off比は、通常103以上であり、好ましくは104以上、よりより好ましく105以上、さらに好ましくは106以上であり、特に好ましくは107以上である。
また、薄膜トランジスタ1は、低消費電力の観点からは閾値電圧(Vth)がプラスでノーマリーオフとなることが好ましい。閾値電圧(Vth)がマイナスでノーマリーオンとなると、消費電力が大きくなるおそれがある。The on-off ratio of the thin film transistor 1 is usually 10 3 or more, preferably 10 4 or more, more preferably 10 5 or more, still more preferably 10 6 or more, and particularly preferably 10 7 or more.
The thin film transistor 1 is preferably normally off with a positive threshold voltage (Vth) from the viewpoint of low power consumption. If the threshold voltage (Vth) is negative and normally on, power consumption may increase.
本発明の酸化物半導体を含む電界効果型トランジスタの製造方法は、例えば以下の方法により製造することができる。
まず絶縁性基板上に金属膜を成膜し、ゲート電極を形成する。金属膜としてはMo,Al、Cr及びこれらを主成分とする合金が好適に用いられる。これらの金属膜の積層膜を用いてもよい。
ゲート電極及び絶縁性基板上に、プラズマCVD法により、ゲート絶縁膜を成膜する。次にスパッタリング法によりチャネルとなる半導体層を成膜する。次に、フォトリソグラフィー工程及びエッチング工程を経て、TFTとなる領域の半導体層を島状に形成する。続いて、ソース電極、ドレイン電極を形成するための第2金属膜を成膜する。この第2金属膜には、ゲート電極と同様に、Al、CrやMo、これらを含む合金等の材料を用いることができる。積層膜により構成することも可能である。
成膜した第2金属膜を、フォトリソグラフィー工程、エッチング工程により所望の形状のソース電極、ドレイン電極のパターンを得ることでトランジスタが得られる。The manufacturing method of the field effect transistor containing the oxide semiconductor of this invention can be manufactured, for example with the following method.
First, a metal film is formed on an insulating substrate to form a gate electrode. As the metal film, Mo, Al, Cr and alloys containing these as main components are preferably used. A laminated film of these metal films may be used.
A gate insulating film is formed on the gate electrode and the insulating substrate by plasma CVD. Next, a semiconductor layer to be a channel is formed by a sputtering method. Next, a semiconductor layer in a region to be a TFT is formed in an island shape through a photolithography process and an etching process. Subsequently, a second metal film for forming a source electrode and a drain electrode is formed. For the second metal film, a material such as Al, Cr, Mo, or an alloy containing these can be used in the same manner as the gate electrode. It is also possible to configure with a laminated film.
A transistor is obtained by obtaining a pattern of a source electrode and a drain electrode having desired shapes from the formed second metal film by a photolithography process and an etching process.
実施例1〜30
マグネトロンスパッタリング装置に、表1〜3に示すターゲット組成を有する2インチのターゲットを装着し、基板A1として厚み100nmの熱酸化膜付シリコンウェハーを、及び基板B1としてスライドガラス(コーニング社製♯1737)をそれぞれ装着した。
基板をチャンバー内へ搬送後、所定の到達圧力とした後、表1〜3に示す分圧比であるArガス及びH2Oガスを導入し、表1〜3に示すスパッタ条件にて膜厚50nmの非晶質膜を基板A1及び基板B1上にそれぞれ成膜した。
得られた薄膜を表1〜3に示すアニール条件でオーブン中でアニール処理を行い、基板A1及び基板B1上に積層してなる酸化物半導体を得た。Examples 1-30
A 2-inch target having the target composition shown in Tables 1 to 3 is mounted on a magnetron sputtering apparatus, a silicon wafer with a thermal oxide film having a thickness of 100 nm is used as the substrate A1, and a slide glass (# 1737 manufactured by Corning) as the substrate B1. Each was fitted.
After conveying the substrate into the chamber and setting it to a predetermined ultimate pressure, Ar gas and H 2 O gas having a partial pressure ratio shown in Tables 1 to 3 were introduced, and the film thickness was 50 nm under the sputtering conditions shown in Tables 1 to 3. Were formed on the substrate A1 and the substrate B1, respectively.
The obtained thin film was annealed in an oven under the annealing conditions shown in Tables 1 to 3 to obtain an oxide semiconductor laminated on the substrate A1 and the substrate B1.
加熱処理後の酸化物半導体を備えてなる基板B1を1cm2にカットし、4隅にAu電極をつけた。Au電極と銅線を銀ペーストにより接着してホール効果測定用素子B1とし、キャリア濃度を評価した。結果を表1〜3に示す。
尚、キャリア濃度の測定は、室温にてResiTest8300型(東陽テクニカ社製)を用いてホール効果測定を行うことにより求めた。The substrate B1 including the oxide semiconductor after the heat treatment was cut into 1 cm 2 and Au electrodes were attached to the four corners. An Au electrode and a copper wire were bonded with a silver paste to form a Hall effect measuring element B1, and the carrier concentration was evaluated. The results are shown in Tables 1-3.
The carrier concentration was measured by performing Hall effect measurement using a ReiTest 8300 type (manufactured by Toyo Technica Co., Ltd.) at room temperature.
加熱処理後の酸化物半導体を備えてなる基板A1を2インチカソードのマグネトロンスパッタリング装置に再度装着し、カソードにAuターゲットを装着して、専用のメタルマスクを用いて、W/L=1000/200μmとなるようにAu電極を成膜し、TFT素子A1を製造した。
得られたTFT素子A1をケースレー4200SCSにセットし、ドレイン電圧Vds=10V及びゲート電圧Vgs=−20〜20Vの条件で伝達特性を評価した。結果を表1〜3に示す。The substrate A1 including the oxide semiconductor after the heat treatment is mounted again on the 2-inch cathode magnetron sputtering apparatus, an Au target is mounted on the cathode, and a dedicated metal mask is used, and W / L = 1000/200 μm. An Au electrode was formed so that the TFT element A1 was manufactured.
The obtained TFT element A1 was set to Keithley 4200SCS, and the transfer characteristics were evaluated under the conditions of drain voltage Vds = 10V and gate voltage Vgs = -20 to 20V. The results are shown in Tables 1-3.
比較例1〜12及び参考例1〜2
表4及び5に示すターゲット組成を有するターゲットを用い、表4及び5に示す分圧比であるArガス及びH2Oガス(比較例5〜6及び参考例1〜2)又はArガス及びO2ガス(比較例1〜4、7〜12)を導入し、表4及び5に示す条件で非晶質膜の成膜及びアニール処理を行なった他は実施例1〜30と同様にして酸化物半導体を製造し、実施例1〜30と同様にしてホール効果測定用素子B1を製造してキャリア濃度を評価し、及びTFT素子A1を製造して伝達特性を評価した。結果を表4及び5に示す。Comparative Examples 1-12 and Reference Examples 1-2
Using a target having the target composition shown in Tables 4 and 5, Ar gas and H 2 O gas (Comparative Examples 5 to 6 and Reference Examples 1 and 2) or Ar gas and O 2 having a partial pressure ratio shown in Tables 4 and 5 A gas (Comparative Examples 1-4, 7-12) was introduced, and an oxide film was formed in the same manner as in Examples 1-30 except that an amorphous film was formed and annealed under the conditions shown in Tables 4 and 5. A semiconductor was manufactured, and a Hall effect measurement element B1 was manufactured and the carrier concentration was evaluated in the same manner as in Examples 1 to 30, and a TFT element A1 was manufactured and the transfer characteristics were evaluated. The results are shown in Tables 4 and 5.
実施例及び比較例の結果に基づき、酸素濃度又は水素濃度と得られる薄膜のキャリア濃度の関係を図4に示す。 Based on the results of Examples and Comparative Examples, FIG. 4 shows the relationship between the oxygen concentration or the hydrogen concentration and the carrier concentration of the obtained thin film.
実施例31
ボトムゲート構造トップコンタクト構成の電界効果トランジスタを作製した。
原子比In:Sn:Zn=36:15:49であるITZOスパッタリングターゲットを、DCマグネトロンスパッタリング成膜装置に装着してスパッタリングを行い、熱酸化膜(100nm)付シリコン基板上に半導体層(膜厚80nm)を成膜した。
スパッタ条件は、到達圧力2×10−4Pa、スパッタ圧力0.65Pa、分圧比[H2O]/([H2O]+[Ar])=3%、分圧比[O2]/([O2]+[Ar])=0%、パワー密度5.0W/cm2、T−S距離5cm、成膜速度95nm/min.とした。Example 31
A field effect transistor having a bottom gate structure and a top contact structure was fabricated.
An ITZO sputtering target having an atomic ratio of In: Sn: Zn = 36: 15: 49 is mounted on a DC magnetron sputtering film forming apparatus to perform sputtering, and a semiconductor layer (film thickness) is formed on a silicon substrate with a thermal oxide film (100 nm). 80 nm) was formed.
Sputtering conditions were ultimate pressure 2 × 10 −4 Pa, sputtering pressure 0.65 Pa, partial pressure ratio [H 2 O] / ([H 2 O] + [Ar]) = 3%, partial pressure ratio [O 2 ] / ( [O 2 ] + [Ar]) = 0%, power density 5.0 W / cm 2 , T-S distance 5 cm, deposition rate 95 nm / min. It was.
得られた半導体層をフォトリソグラフィして、半導体領域(いわゆる島)を構成し、大気下300℃で1時間熱処理した。フォトレジスト膜を形成後、DCスパッタリングでTi/Au/Tiの積層金属膜を成膜し、リフトオフでパターニングしてソース電極及びドレイン電極をそれぞれ形成した。その後、大気下300℃で1時間熱処理した。
次に、プラズマCVDにてSiOx及びSiNxの順に成膜し、第1の保護層、第2の保護層をそれぞれ形成した。コンタクトホールを形成し、外部配線と接続した。その後、大気下、300℃で1時間熱処理して、W=20μm及びL=20μmであり、Si基板をゲート電極としたボトムゲート構成かつトップコンタクト構成の電界効果型トランジスタを製造した。The obtained semiconductor layer was subjected to photolithography to form a semiconductor region (so-called island), and heat-treated at 300 ° C. for 1 hour in the atmosphere. After forming the photoresist film, a laminated metal film of Ti / Au / Ti was formed by DC sputtering, and patterning was performed by lift-off to form a source electrode and a drain electrode, respectively. Thereafter, heat treatment was performed at 300 ° C. for 1 hour in the atmosphere.
Next, SiOx and SiNx were formed in this order by plasma CVD to form a first protective layer and a second protective layer, respectively. Contact holes were formed and connected to external wiring. Thereafter, heat treatment was performed in the atmosphere at 300 ° C. for 1 hour to produce a field effect transistor having W = 20 μm and L = 20 μm and having a bottom gate configuration and a top contact configuration using a Si substrate as a gate electrode.
得られた電界効果型トランジスタについて、その特性評価を行なった。
その結果、電界効果移動度が21cm2/Vs、オンオフ比が108以上、閾値電圧が0.3V、S値が0.2V/decadeであった。
上記評価は、半導体パラメーターアナライザー(ケースレー4200)を用い、大気圧の乾燥窒素雰囲気下、室温、遮光環境下で評価した。The obtained field effect transistor was evaluated for its characteristics.
As a result, the field effect mobility was 21 cm 2 / Vs, the on / off ratio was 10 8 or more, the threshold voltage was 0.3 V, and the S value was 0.2 V / decade.
The evaluation was performed using a semiconductor parameter analyzer (Keutley 4200) in an atmosphere of dry nitrogen at atmospheric pressure, room temperature, and in a light-shielded environment.
比較例13
半導体層成膜時の水蒸気分圧及び酸素分圧をそれぞれ分圧比[H2O]/([H2O]+[Ar])=0%、分圧比[O2]/([O2]+[Ar])=10%とした他は実施例31と同様にして電界効果型トランジスタを製造し、評価した。
その結果、得られた電界効果型トランジスタは、閾値電圧−20V以下のノーマリーオン状態であった。酸素分圧制御では、チャンネル層が80nmの薄膜トランジスタの作製が困難であることが確認された。Comparative Example 13
The partial pressure ratio [H 2 O] / ([H 2 O] + [Ar]) = 0% and the partial pressure ratio [O 2 ] / ([O 2 ]) for the water vapor partial pressure and the oxygen partial pressure at the time of forming the semiconductor layer, respectively. A field effect transistor was manufactured and evaluated in the same manner as in Example 31 except that + [Ar]) = 10%.
As a result, the obtained field effect transistor was normally on with a threshold voltage of −20 V or less. In the oxygen partial pressure control, it was confirmed that it was difficult to produce a thin film transistor having a channel layer of 80 nm.
実施例32
ソース電極及びドレイン電極にMoを用い、リン酸系ウェットエッチング液を用い、チャンネル層上のMo電極をウェトエッチィングすることによって、チャンネルエッチ型のボトムゲート構成かつトップコンタクト構成の電界効果型トランジスタを製造した以外は、実施例31と同様にして電界効果型トランジスタを作製し評価した。
その結果、得られた電界効果型トランジスタは、電界効果移動度が19cm2/Vsであり、オンオフ比が108以上であり、閾値電圧が0.3Vであり、S値が0.2V/decadeであった。Example 32
By using Mo for the source electrode and the drain electrode, and wet etching the Mo electrode on the channel layer using a phosphoric acid-based wet etching solution, a field-effect transistor having a channel-etched bottom gate configuration and a top-contact configuration is obtained. A field effect transistor was prepared and evaluated in the same manner as in Example 31 except that it was manufactured.
As a result, the obtained field effect transistor has a field effect mobility of 19 cm 2 / Vs, an on / off ratio of 10 8 or more, a threshold voltage of 0.3 V, and an S value of 0.2 V / decade. Met.
実施例33
ガラス基板上に、室温でRFスパッタリングして、モリブデン金属を200nm積層した後、ドライエッチングでパターニングして、ゲート電極を作製した。ゲート電極は、エッチング後に順テーパとなっていた。ゲート電極を積層した基板に、プラズマ化学気相成長装置(PECVD)にて、SiNx、SiO2の順に成膜し、積層膜をゲート絶縁膜とした。
実施例31と同じスパッタリングターゲットを、DCマグネトロンスパッタリング成膜装置に装着し、実施例31と同一の条件でスパッタリングして、ゲート絶縁膜上に半導体層(膜厚80nm)を成膜した。その後、300℃で1時間熱処理した。Example 33
RF sputtering was performed on a glass substrate at room temperature to deposit 200 nm of molybdenum metal, followed by patterning by dry etching to produce a gate electrode. The gate electrode was forward tapered after etching. On the substrate on which the gate electrode was laminated, SiNx and SiO 2 were formed in this order by a plasma enhanced chemical vapor deposition apparatus (PECVD), and the laminated film was used as a gate insulating film.
The same sputtering target as in Example 31 was mounted on a DC magnetron sputtering film forming apparatus and sputtered under the same conditions as in Example 31 to form a semiconductor layer (film thickness of 80 nm) on the gate insulating film. Then, it heat-processed at 300 degreeC for 1 hour.
PECVDにてSiOxを成膜し、SiOx薄膜を形成した。続けて、レジスト膜を成膜し、パターニングした。ドライエッチ(RIE)で薄膜をパターニングして第1の保護層(エッチストッパー)を形成した。リフトオフ用のフォトレジストレジスト膜を塗布し形成後、DCスパッタリングでTi/Au/Tiの金属積層膜を成膜し、リフトオフ及びパターニングしてソース電極及びドレイン電極をそれぞれ形成した。さらに、PECVD(PECVD SiNx:H)にてSiNxを成膜し第2保護層とした。コンタクトホールを形成し、外部配線と接続した。その後、大気下、300℃で1時間熱処理して、W=20μm、L=20μmのボトムゲート構造であるエッチストッパー型電界効果型トランジスタを製造した。 A SiOx film was formed by PECVD to form a SiOx thin film. Subsequently, a resist film was formed and patterned. The thin film was patterned by dry etching (RIE) to form a first protective layer (etch stopper). After applying and forming a lift-off photoresist resist film, a Ti / Au / Ti metal laminate film was formed by DC sputtering, and lift-off and patterning were performed to form a source electrode and a drain electrode, respectively. Furthermore, SiNx was formed by PECVD (PECVD SiNx: H) to form a second protective layer. Contact holes were formed and connected to external wiring. Thereafter, heat treatment was performed in the atmosphere at 300 ° C. for 1 hour to manufacture an etch stopper type field effect transistor having a bottom gate structure of W = 20 μm and L = 20 μm.
得られた電界効果型トランジスタについて実施例31と同様にして評価した。
その結果、電界効果移動度18cm2/Vs、オンオフ比が108以上、閾値電圧が0.3V、S値が0.2V/decadeであった。The obtained field effect transistor was evaluated in the same manner as in Example 31.
As a result, the field effect mobility was 18 cm 2 / Vs, the on / off ratio was 10 8 or more, the threshold voltage was 0.3 V, and the S value was 0.2 V / decade.
実施例34
図1の成膜装置を用い、幅1100mm、長さ1250mm、厚さ0.7mmのガラス基板を加熱せずに表6の条件にてスパッタリングを行った。Example 34
Sputtering was performed using the film forming apparatus of FIG. 1 under the conditions shown in Table 6 without heating a glass substrate having a width of 1100 mm, a length of 1250 mm, and a thickness of 0.7 mm.
ここでは、In:Sn:Zn(原子比)=36:15:49であり、幅200mm、長さ1700mm、厚さ10mmの6枚のターゲット100a〜100fを用い、各ターゲット100a〜100fを基板の幅方向に平行に、ターゲット間の距離が2mmになるように配置した。磁界形成手段200a〜200fの幅はターゲット100a〜100fと同じ200nmとした。 Here, In: Sn: Zn (atomic ratio) = 36: 15: 49, six targets 100a to 100f having a width of 200 mm, a length of 1700 mm, and a thickness of 10 mm are used, and the targets 100a to 100f are formed on the substrate. Parallel to the width direction, the distance between the targets was 2 mm. The width of the magnetic field forming means 200a to 200f was set to 200 nm, which is the same as that of the targets 100a to 100f.
ガス供給系からスパッタガスであるArとH2Oをそれぞれ99:1の流量比で系内に導入した。このときの成膜雰囲気は0.5Paとなった。交流電源のパワーは3W/cm2(=10.2kW/3400cm2)とし、周波数は10kHzとした。
以上の条件で8秒成膜し、得られたITZOの膜厚を測定すると15nmであった。成膜速度は112.5nm/分と高速であり、量産に適した結果となった。
また、このようにして得られたITZO付きガラス基板電気炉に入れ、空気中400℃15分の条件で熱処理後、1cm2のサイズに切出し、4探針法によるホール測定を行った。その結果、キャリア濃度が2.5×1016cm−3となり、十分半導体化していることが確認できた。Ar and H 2 O, which are sputtering gases, were introduced from the gas supply system into the system at a flow rate ratio of 99: 1. The film forming atmosphere at this time was 0.5 Pa. The power of the AC power source was 3 W / cm 2 (= 10.2 kW / 3400 cm 2 ), and the frequency was 10 kHz.
The film was formed under the above conditions for 8 seconds, and the thickness of the obtained ITZO was measured to be 15 nm. The film formation rate was as high as 112.5 nm / min, which was suitable for mass production.
Moreover, it put into the glass substrate electric furnace with ITZO obtained in this way, and after heat-treating on the conditions of 400 degreeC for 15 minutes in air, it cut out to the size of 1 cm < 2 > and measured the hole by the 4-probe method. As a result, the carrier concentration was 2.5 × 10 16 cm −3 , and it was confirmed that the semiconductor was sufficiently semiconductorized.
実施例35〜実施例39
ターゲット組成とスパッタ条件を表6のように変更した他は実施例34と同様にして半導体薄膜を得た。また、実施例34と同様にして熱処理の後、ホール測定を行い、全て半導体化していることを確認した。Examples 35-39
A semiconductor thin film was obtained in the same manner as in Example 34 except that the target composition and sputtering conditions were changed as shown in Table 6. Further, after heat treatment in the same manner as in Example 34, hole measurement was performed, and it was confirmed that all semiconductors were formed.
比較例14
スパッタ条件を表6のように変更した他は実施例34と同様にして半導体薄膜を得た。導入ガスに水を使用せず、アルゴンと酸素を導入してITZOを成膜した。ホール測定の結果、キャリア濃度は2.5×1017cm−3であり、半導体化したが、成膜レートが36nm/分と遅かった。この成膜レートでは量産に課題を残すと考えられる。Comparative Example 14
A semiconductor thin film was obtained in the same manner as in Example 34 except that the sputtering conditions were changed as shown in Table 6. ITZO was formed by introducing argon and oxygen without using water as the introduced gas. As a result of the hole measurement, the carrier concentration was 2.5 × 10 17 cm −3 and the semiconductor was made, but the film formation rate was as slow as 36 nm / min. This film formation rate is considered to leave a problem in mass production.
比較例15
比較例14において出力パワーを20W/cm2に増加させ、高速成膜を行った。これにより成膜レートは90nm/分と上昇した。しかし、キャリア濃度が7.5×1018cm−3であり、半導体化しなかった。Comparative Example 15
In Comparative Example 14, the output power was increased to 20 W / cm 2 and high speed film formation was performed. As a result, the deposition rate increased to 90 nm / min. However, the carrier concentration was 7.5 × 10 18 cm −3 and it was not made into a semiconductor.
比較例16
スパッタ条件を表6のように変更した他は比較例14と同様にして半導体薄膜を得た。キャリア濃度が5.5×1019cm−3であり、半導体化しなかった。Comparative Example 16
A semiconductor thin film was obtained in the same manner as in Comparative Example 14 except that the sputtering conditions were changed as shown in Table 6. The carrier concentration was 5.5 × 10 19 cm −3 and it was not made semiconductor.
実施例40〜46
マグネトロンスパッタリング装置に、表7に示すターゲット組成を有する2インチのターゲットを装着し、基板A1として厚み100nmの熱酸化膜付シリコンウェハーを、及び基板B1としてスライドガラス(コーニング社製♯1737)をそれぞれ装着した。
基板をチャンバー内へ搬送後、所定の到達圧力とした後、表7に示す分圧比であるArガス及びH2Oガスを導入し、表7に示すスパッタ条件にて膜厚50nmの非晶質膜を基板A1及び基板B1上にそれぞれ成膜した。
得られた薄膜を表7に示すアニール条件でオーブン中でアニール処理を行い、基板A1及び基板B1上に積層してなる酸化物半導体を得た。Examples 40-46
A 2-inch target having the target composition shown in Table 7 was mounted on the magnetron sputtering apparatus, a silicon wafer with a thermal oxide film having a thickness of 100 nm was used as the substrate A1, and a slide glass (# 1737 manufactured by Corning) was used as the substrate B1. Installed.
After transporting the substrate into the chamber and setting it to a predetermined ultimate pressure, Ar gas and H 2 O gas having a partial pressure ratio shown in Table 7 were introduced, and an amorphous film having a film thickness of 50 nm under the sputtering conditions shown in Table 7 A film was formed on each of the substrate A1 and the substrate B1.
The obtained thin film was annealed in an oven under the annealing conditions shown in Table 7 to obtain an oxide semiconductor laminated on the substrate A1 and the substrate B1.
加熱処理後の酸化物半導体を備えてなる基板B1を1cm2にカットし、4隅にAu電極をつけた。Au電極と銅線を銀ペーストにより接着してホール効果測定用素子B1とし、キャリア濃度を評価した。結果を表7に示す。
尚、キャリア濃度の測定は、室温にてResiTest8300型(東陽テクニカ社製)を用いてホール効果測定を行うことにより求めた。The substrate B1 including the oxide semiconductor after the heat treatment was cut into 1 cm 2 and Au electrodes were attached to the four corners. An Au electrode and a copper wire were bonded with a silver paste to form a Hall effect measuring element B1, and the carrier concentration was evaluated. The results are shown in Table 7.
The carrier concentration was measured by performing Hall effect measurement using a ReiTest 8300 type (manufactured by Toyo Technica Co., Ltd.) at room temperature.
加熱処理後の酸化物半導体を備えてなる基板A1を2インチカソードのマグネトロンスパッタリング装置に再度装着し、カソードにAuターゲットを装着して、専用のメタルマスクを用いて、W/L=1000/200μmとなるようにAu電極を成膜し、TFT素子A1を製造した。
得られたTFT素子A1をケースレー4200SCSにセットし、ドレイン電圧Vds=10V及びゲート電圧Vgs=−20〜20Vの条件で伝達特性を評価した。結果を表7に示す。The substrate A1 including the oxide semiconductor after the heat treatment is mounted again on the 2-inch cathode magnetron sputtering apparatus, an Au target is mounted on the cathode, and a dedicated metal mask is used, and W / L = 1000/200 μm. An Au electrode was formed so that the TFT element A1 was manufactured.
The obtained TFT element A1 was set to Keithley 4200SCS, and the transfer characteristics were evaluated under the conditions of drain voltage Vds = 10V and gate voltage Vgs = -20 to 20V. The results are shown in Table 7.
実施例47〜51
表8に示すターゲット組成を有するターゲットを用い、表8に示す分圧比であるArガス及びH2Oガスを導入し、表8に示す条件で非晶質膜の成膜及びアニール処理を行なった他は実施例40〜46と同様にして酸化物半導体を製造し、実施例40〜46と同様にしてホール効果測定用素子B1を製造してキャリア濃度を評価し、及びTFT素子A1を製造して伝達特性を評価した。結果を表8に示す。Examples 47-51
Using a target having the target composition shown in Table 8, Ar gas and H 2 O gas having a partial pressure ratio shown in Table 8 were introduced, and an amorphous film was formed and annealed under the conditions shown in Table 8. Others manufacture oxide semiconductor like Example 40-46, manufacture Hall effect measuring element B1 like Example 40-46, evaluate carrier concentration, and manufacture TFT element A1 The transfer characteristics were evaluated. The results are shown in Table 8.
本発明の酸化物半導体の製造方法により得られる酸化物半導体は、薄膜トランジスタ等の電界効果型トランジスタの半導体薄膜として広く利用することができる。 The oxide semiconductor obtained by the oxide semiconductor manufacturing method of the present invention can be widely used as a semiconductor thin film of a field effect transistor such as a thin film transistor.
上記に本発明の実施形態及び/又は実施例を幾つか詳細に説明したが、当業者は、本発明の新規な教示及び効果から実質的に離れることなく、これら例示である実施形態及び/又は実施例に多くの変更を加えることが容易である。従って、これらの多くの変更は本発明の範囲に含まれる。
この明細書に記載の文献の内容を全てここに援用する。Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will appreciate that these exemplary embodiments and / or embodiments are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many changes to the embodiment. Accordingly, many of these modifications are within the scope of the present invention.
The entire contents of the documents described in this specification are incorporated herein by reference.
Claims (19)
前記各ターゲットに交流電源から負電位及び正電位を交互に印加して前記ターゲット上にプラズマを発生させて前記基板表面上に薄膜を成膜する成膜方法であって、
前記成膜は、前記交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら行う、請求項4に記載の成膜方法。The substrate is sequentially transferred to a position facing three or more targets arranged in parallel in the vacuum chamber at a predetermined interval,
A method of forming a thin film on the surface of the substrate by alternately applying a negative potential and a positive potential to each target from an AC power source to generate plasma on the target,
5. The film formation according to claim 4, wherein the film formation is performed while switching a target to which a potential is applied between two or more targets branched and connected to at least one of the outputs from the AC power source. Membrane method.
ターゲット中のインジウム元素の含有量が、下記原子比を満たす請求項1〜11のいずれかに記載の成膜方法。
0.2≦[In]/全金属原子≦0.8
(式中、[In]はターゲット中のインジウム元素の原子数である。
全金属原子とは、ターゲットに含まれる全ての金属原子の原子数である。)The metal oxide contains at least one element selected from the group consisting of gallium element (Ga), zinc element (Zn) and tin element (Sn), and indium element (In),
The film forming method according to claim 1, wherein the content of indium element in the target satisfies the following atomic ratio.
0.2 ≦ [In] / all metal atoms ≦ 0.8
(In the formula, [In] is the number of atoms of indium element in the target.
The total metal atom is the number of atoms of all metal atoms included in the target. )
ターゲット中のインジウム元素、ガリウム元素及び亜鉛元素の含有量が、下記原子比を満たす請求項1〜11のいずれかに記載の成膜方法。
0<[In]/[Ga]<0.5
0.2<[In]/([In]+[Ga]+[Zn])<0.9
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Ga]はターゲット中のガリウム元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)The metal oxide contains indium element (In), gallium element (Ga) and zinc element (Zn);
The film-forming method in any one of Claims 1-11 with which content of the indium element in a target, a gallium element, and a zinc element satisfy | fills the following atomic ratio.
0 <[In] / [Ga] <0.5
0.2 <[In] / ([In] + [Ga] + [Zn]) <0.9
(In the formula, [In] is the number of atoms of indium element in the target, [Ga] is the number of atoms of gallium element in the target, and [Zn] is the number of atoms of zinc element in the target.)
ターゲット中のインジウム元素、スズ元素及び亜鉛元素の含有量が、下記原子比を満たす請求項1〜11のいずれかに記載の成膜方法。
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.5
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Sn]はターゲット中のスズ元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)The metal oxide contains indium element (In), tin element (Sn), and zinc element (Zn),
The film forming method according to claim 1, wherein the contents of indium element, tin element and zinc element in the target satisfy the following atomic ratio.
0.2 <[In] / ([In] + [Sn] + [Zn]) <0.9
0 <[Sn] / ([In] + [Sn] + [Zn]) <0.5
(In the formula, [In] is the number of atoms of indium element in the target, [Sn] is the number of atoms of tin element in the target, and [Zn] is the number of atoms of zinc element in the target.)
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WO2009075281A1 (en) * | 2007-12-13 | 2009-06-18 | Idemitsu Kosan Co., Ltd. | Field effect transistor using oxide semiconductor and method for manufacturing the same |
WO2009084537A1 (en) * | 2007-12-27 | 2009-07-09 | Nippon Mining & Metals Co., Ltd. | Process for producing thin film of a-igzo oxide |
JP2010080936A (en) * | 2008-08-28 | 2010-04-08 | Canon Inc | Amorphous oxide semiconductor and thin film transistor using the same |
Also Published As
Publication number | Publication date |
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KR20170092716A (en) | 2017-08-11 |
CN102859670A (en) | 2013-01-02 |
CN102859670B (en) | 2015-09-02 |
KR20130079348A (en) | 2013-07-10 |
WO2011132418A1 (en) | 2011-10-27 |
TW201142054A (en) | 2011-12-01 |
TWI525205B (en) | 2016-03-11 |
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